diff options
133 files changed, 5244 insertions, 413 deletions
@@ -653,6 +653,8 @@ $(eval $(call assert_booleans,\ LFA_SUPPORT \ SUPPORT_SP_LIVE_ACTIVATION \ TEST_IO_SHORT_READ_FI \ + SDEI_SUPPORT \ + SMC_PCI_SUPPORT \ ))) # Numeric_Flags @@ -738,6 +740,7 @@ $(eval $(call assert_numerics,\ IMPDEF_SYSREG_TRAP \ W \ TEST_IO_SHORT_READ_FI_IMAGE_ID \ + USE_GIC_DRIVER \ ))) ifdef KEY_SIZE @@ -936,6 +939,9 @@ $(eval $(call add_defines,\ SUPPORT_SP_LIVE_ACTIVATION \ TEST_IO_SHORT_READ_FI \ TEST_IO_SHORT_READ_FI_IMAGE_ID \ + SDEI_SUPPORT \ + USE_GIC_DRIVER \ + SMC_PCI_SUPPORT \ ))) ifeq (${PLATFORM_REPORT_CTX_MEM_USE}, 1) diff --git a/bl31/bl31.mk b/bl31/bl31.mk index 69c348f9a..29b79e173 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -216,7 +216,8 @@ endif ifeq (${FIRME_SUPPORT},1) BL31_SOURCES += services/std_svc/firme/firme_main.c \ services/std_svc/firme/firme_base_service.c \ - services/std_svc/firme/firme_granule_management_service.c + services/std_svc/firme/firme_granule_management_service.c \ + services/std_svc/firme/firme_mecid.c endif BL31_DEFAULT_LINKER_SCRIPT_SOURCE := bl31/bl31.ld.S @@ -243,7 +244,6 @@ $(eval $(call assert_booleans,\ CRASH_REPORTING \ EL3_EXCEPTION_HANDLING \ FIRME_SUPPORT \ - SDEI_SUPPORT \ USE_DSU_DRIVER \ ))) @@ -257,7 +257,6 @@ $(eval $(call add_defines,\ $(sort \ CRASH_REPORTING \ EL3_EXCEPTION_HANDLING \ - SDEI_SUPPORT \ USE_DSU_DRIVER \ FIRME_SUPPORT \ ))) diff --git a/changelog.yaml b/changelog.yaml index 9c7c75b57..16eee6cb1 100644 --- a/changelog.yaml +++ b/changelog.yaml @@ -643,6 +643,9 @@ subsections: - title: RK3588 scope: rk3588 + - title: RV1126B + scope: rv1126b + - title: Socionext scope: socionext diff --git a/docs/components/context-management-library.rst b/docs/components/context-management-library.rst index e613bc4e0..9417a4b89 100644 --- a/docs/components/context-management-library.rst +++ b/docs/components/context-management-library.rst @@ -252,30 +252,9 @@ CPU Context and Memory allocation CPU Context ~~~~~~~~~~~ The members of the context structure used by the EL3 firmware to preserve the -state of CPU across exception levels for a given security state are listed below. - -.. code:: c - - typedef struct cpu_context { - gp_regs_t gpregs_ctx; - el3_state_t el3state_ctx; - - cve_2018_3639_t cve_2018_3639_ctx; - - #if ERRATA_SPECULATIVE_AT - errata_speculative_at_t errata_speculative_at_ctx; - #endif - - #if CTX_INCLUDE_PAUTH_REGS - pauth_t pauth_ctx; - #endif - - #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) - el2_sysregs_t el2_sysregs_ctx; - #else - el1_sysregs_t el1_sysregs_ctx; - #endif - } cpu_context_t; +state of CPU across exception levels for a given security state are listed in +the cpu_context structure, located in `lib/el3_runtime/aarch32/context.h`_ or +`lib/el3_runtime/aarch64/context.h`_. Context Memory Allocation ~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -521,7 +500,7 @@ structure and is intended to manage specific EL3 registers. typedef struct per_world_context { uint64_t ctx_cptr_el3; uint64_t ctx_mpam3_el3; - #if (ENABLE_FEAT_IDTE3 && IMAGE_BL31) + #if (ENABLE_FEAT_IDTE3 && defined(IMAGE_BL31)) perworld_idregs_t idregs; #endif } per_world_context_t; @@ -598,4 +577,6 @@ entrypaths and at all the possible exception handlers routing to EL3 at runtime. .. |Root Context Sequence| image:: ../resources/diagrams/root_context_sequence.png .. _Trustzone for AArch64: https://developer.arm.com/documentation/102418/0101/TrustZone-in-the-processor/Switching-between-Security-states .. _Security States with RME: https://developer.arm.com/documentation/den0126/0100/Security-states -.. _lib/el3_runtime/(aarch32/aarch64): https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/el3_runtime +.. _lib/el3_runtime/(aarch32/aarch64): https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/+/master/lib/el3_runtime +.. _lib/el3_runtime/aarch32/context.h: https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a.git/+/master/include/lib/el3_runtime/aarch32/context.h +.. _lib/el3_runtime/aarch64/context.h: https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a.git/+/master/include/lib/el3_runtime/aarch64/context.h diff --git a/docs/components/firme.rst b/docs/components/firme.rst index ad090b85a..7ab5211a5 100644 --- a/docs/components/firme.rst +++ b/docs/components/firme.rst @@ -58,7 +58,7 @@ Current status operation. - The IDE key management, MECID management, attestation, and integrated device management services are not implemented yet. -- ``FIRME_GM_GPI_OP_CONTINUE`` is mandatory in the ``1.0 alp2`` specification, +- ``FIRME_GM_GPI_OP_CONTINUE_FID`` is mandatory in the ``1.0 alp2`` specification, but it is not implemented yet. As a result, the current implementation tracks FIRME ``1.0 alp2`` for diff --git a/docs/plat/rockchip.rst b/docs/plat/rockchip.rst index 016bed707..2e130a790 100644 --- a/docs/plat/rockchip.rst +++ b/docs/plat/rockchip.rst @@ -13,6 +13,7 @@ This includes right now: - rk3566/rk3568: Quad-Core Cortex-A55 - rk3576: Octa-Core Cortex-A53/A72 - rk3588: Octa-Core Cortex-A55/A76 +- rv1126b: Quad-Core Cortex-A53 Boot Sequence diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index 9dcb72f93..67d7769f4 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -515,17 +515,6 @@ must also be defined: With this macro, multiple block devices could be supported at the same time. -If the platform needs to allocate data within the per-cpu data framework in -BL31, it should define the following macro. Currently this is only required if -the platform decides not to use the coherent memory section by undefining the -``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the -required memory within the the per-cpu data to minimize wastage. - -- **#define : PLAT_PCPU_DATA_SIZE** - - Defines the memory (in bytes) to be reserved within the per-cpu data - structure for use by the platform layer. - The following constants are optional. They should be defined when the platform memory layout implies some image overlaying like in Arm standard platforms. @@ -2365,24 +2354,54 @@ RMM image and stores it in the area specified by manifest. When ENABLE_RMM is disabled, this function is not used. -Function : plat_rmmd_mecid_key_update() [when ENABLE_RMM == 1] +Function : plat_firme_get_common_mecid_width() [when FIRME_SUPPORT == 1] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : uint8_t + +This function is invoked by BL31's FIRME MECID management service during +initialization to obtain the system MECID width. This is the smallest supported +MECID width for the entire system. + +The returned value uses the same encoding as ``MECIDR_EL2.MECIDWidthm1``. That +is, it is the system MECID width minus one. The common MECID width is defined as +the smallest MECID width supported across the entire system (see rule IQDYKJ in +the M.b version of the Arm ARM for details). The FIRME MECID management service +advertises the returned value in FIRME MECID feature register 1. + +This function needs to be implemented by a platform if it enables FIRME support +and advertises the FIRME MECID management service. + +Function : plat_firme_mec_refresh() [when FIRME_SUPPORT == 1] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: - Argument : uint16_t, unsigned int + Argument : uint16_t, uint8_t Return : int -This function is invoked by BL31's RMMD when there is a request from the RMM -monitor to update the tweak for the encryption key associated to a MECID. +This function is invoked by BL31's FIRME MECID management service when there is +a request to refresh the Memory Encryption Context (MEC) associated with a +MECID. + +The first parameter (``uint16_t mecid``) contains the MECID whose associated +MEC is to be refreshed. The second parameter (``uint8_t reason``) specifies the +reason for the refresh. Possible values are: +``MEC_REFRESH_REASON_REALM_CREATE`` for Realm creation and +``MEC_REFRESH_REASON_REALM_DESTROY`` for Realm destruction. -The first parameter (``uint16_t mecid``) contains the MECID for which the -encryption key is to be updated. The second argument specifies the reason -for key update. Possible values are: 0 - Realm creation, 1 - Realm destruction. +The FIRME MECID management service validates that FEAT_MEC is supported and +that the MECID fits within the common MECID width before calling this function. -Return value is 0 upon success and -EFAULT otherwise. +The function returns a FIRME status code. It should return ``FIRME_SUCCESS`` on +success, or an appropriate negative FIRME error code such as +``FIRME_INVALID_PARAMETERS``, ``FIRME_DENIED`` or ``FIRME_RETRY`` on failure. -This function needs to be implemented by a platform if it enables RME. +This function needs to be implemented by a platform if it enables FIRME support +and advertises the FIRME MECID management service. Function : plat_rmmd_reserve_memory() [when ENABLE_RMM == 1] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/drivers/arm/gic/gic.mk b/drivers/arm/gic/gic.mk index 8b28f219b..a79537f5f 100644 --- a/drivers/arm/gic/gic.mk +++ b/drivers/arm/gic/gic.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2025-2026, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -38,7 +38,3 @@ BL31_SOURCES += ${GIC_SOURCES} else BL32_SOURCES += ${GIC_SOURCES} endif - -$(eval $(call add_defines,\ - USE_GIC_DRIVER \ -)) diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c index 4c3b49891..2e97f42c6 100644 --- a/drivers/auth/auth_mod.c +++ b/drivers/auth/auth_mod.c @@ -390,13 +390,13 @@ static int auth_nvctr(const auth_method_param_nv_ctr_t *param, /* Invalid NV-counter */ return 1; } else if (*cert_nv_ctr > plat_nv_ctr) { -#if PSA_FWU_SUPPORT && IMAGE_BL2 +#if PSA_FWU_SUPPORT && defined(IMAGE_BL2) if (fwu_get_active_bank_state() == FWU_BANK_STATE_ACCEPTED) { *need_nv_ctr_upgrade = true; } else { *need_nv_ctr_upgrade = false; } -#elif PSA_FWU_SUPPORT && IMAGE_BL1 +#elif PSA_FWU_SUPPORT && defined(IMAGE_BL1) /* The check is for bl1 only */ if (bl1_plat_is_shared_nv_ctr() == false) { /* If NV ctr is not shared, it can be upgraded */ @@ -407,7 +407,7 @@ static int auth_nvctr(const auth_method_param_nv_ctr_t *param, } #else *need_nv_ctr_upgrade = true; -#endif /* PSA_FWU_SUPPORT && IMAGE_BL2 */ +#endif /* PSA_FWU_SUPPORT && defined(IMAGE_BL2) */ } return 0; diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c index dd7800507..f06e98a2f 100644 --- a/drivers/io/io_fip.c +++ b/drivers/io/io_fip.c @@ -309,7 +309,7 @@ static int fip_file_open(io_dev_info_t *dev_info, const uintptr_t spec, int result; uintptr_t backend_handle; const io_uuid_spec_t *uuid_spec = (io_uuid_spec_t *)spec; - static const uuid_t uuid_null = { {0} }; /* Double braces for clang */ + static const uuid_t uuid_null = { 0U }; size_t bytes_read; size_t toc_offset; size_t fip_size; diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.c b/drivers/nxp/ddr/nxp-ddr/ddr.c index 17c2bbb2a..4346ce646 100644 --- a/drivers/nxp/ddr/nxp-ddr/ddr.c +++ b/drivers/nxp/ddr/nxp-ddr/ddr.c @@ -6,6 +6,7 @@ #include <errno.h> #include <inttypes.h> +#include <stdbool.h> #include <stdint.h> #include <stdio.h> #include <stdlib.h> @@ -571,8 +572,85 @@ static int parse_spd(struct ddr_info *priv) if (spd_idx != 0 && spd_checksum[0] != spd_checksum[spd_idx]) { +#if defined(NXP_DDR_DUAL_DIMM_TOLERANT) + /* DDR4 SPD bytes that have impacts */ + static const unsigned int timing_bytes[] = { + + /* device key + organisation */ + 2, /* mem_type DDR3 / DDR4 / LPDDR4 key */ + 4, /* density_banks SDRAM density + bank groups */ + 5, /* addressing row/col bit counts */ + 6, /* package_type SDP / DDP / 3DS / QDP */ + 7, /* opt_feature MAW, fault detect */ + 8, /* thermal_ref refresh interval mode */ + 9, /* oth_opt_features PPR / soft-PPR */ + 11, /* module_vdd nominal voltage (DDR4 = 1.2 V) */ + 12, /* organization ranks + DRAM width (x4/x8/x16) */ + 13, /* bus_width primary bus width + ECC bit */ + 14, /* therm_sensor on-DIMM temp-sensor presence */ + + /* DDR4 base timing block - MTB units (MTB = 125 ps) */ + 17, /* timebases MTB/FTB select (0x00 on DDR4) */ + 18, /* tck_min min SDRAM cycle time -> speed bin */ + 19, /* tck_max max SDRAM cycle time */ + 20, /* caslat_b1 supported CAS latencies, byte 1 */ + 21, /* caslat_b2 supported CAS latencies, byte 2 */ + 22, /* caslat_b3 supported CAS latencies, byte 3 */ + 23, /* caslat_b4 supported CAS latencies, byte 4 */ + 24, /* taa_min min CAS latency time -> CL pick */ + 25, /* trcd_min RAS-to-CAS delay */ + 26, /* trp_min row precharge time */ + 27, /* tras_trc_ext upper nibbles for tRAS / tRC */ + 28, /* tras_min_lsb active-to-precharge LSB */ + 29, /* trc_min_lsb row-cycle time LSB */ + 30, /* trfc1_min_lsb refresh recovery 1x mode LSB */ + 31, /* trfc1_min_msb refresh recovery 1x mode MSB */ + 32, /* trfc2_min_lsb refresh recovery 2x mode LSB */ + 33, /* trfc2_min_msb refresh recovery 2x mode MSB */ + 34, /* trfc4_min_lsb refresh recovery 4x mode LSB */ + 35, /* trfc4_min_msb refresh recovery 4x mode MSB */ + 36, /* tfaw_msb four-activate-window upper nibble */ + 37, /* tfaw_min four-activate-window LSB */ + 38, /* trrds_min act-to-act, different bank groups */ + 39, /* trrdl_min act-to-act, same bank group */ + 40, /* tccdl_min CAS-to-CAS, same bank group */ + + /* DDR4 fine timing - FTB units (1 ps), signed deltas */ + 117, /* fine_tccdl_min adds to byte 40 (tccdl_min) */ + 118, /* fine_trrdl_min adds to byte 39 (trrdl_min) */ + 119, /* fine_trrds_min adds to byte 38 (trrds_min) */ + 120, /* fine_trc_min adds to byte 27/29 (trc) */ + 121, /* fine_trp_min adds to byte 26 (trp) */ + 122, /* fine_trcd_min adds to byte 25 (trcd) */ + 123, /* fine_taa_min adds to byte 24 (taa) */ + 124, /* fine_tck_max adds to byte 19 (tck_max) */ + 125, /* fine_tck_min adds to byte 18 (tck_min) */ + }; + const unsigned char *pa = + (const unsigned char *)&spd[0]; + const unsigned char *pb = + (const unsigned char *)&spd[spd_idx]; + bool timing_ok = true; + unsigned int t; + + for (t = 0U; t < ARRAY_SIZE(timing_bytes); t++) { + unsigned int bx = timing_bytes[t]; + + if (pa[bx] != pb[bx]) { + ERROR("DDR SPD timing byte %u: 0x%02x vs 0x%02x\n", + bx, pa[bx], pb[bx]); + timing_ok = false; + } + } + if (!timing_ok) { + ERROR("Not identical DIMMs (timing-relevant mismatch).\n"); + return -EINVAL; + } + NOTICE("DDR SPDs differ for non-timing bytes only -> accepting\n"); +#else ERROR("Not identical DIMMs.\n"); return -EINVAL; +#endif } conf->dimm_in_use[j] = 1; valid_mask |= 1 << addr_idx; diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.mk b/drivers/nxp/ddr/nxp-ddr/ddr.mk index be9163384..35d615dbd 100644 --- a/drivers/nxp/ddr/nxp-ddr/ddr.mk +++ b/drivers/nxp/ddr/nxp-ddr/ddr.mk @@ -74,6 +74,14 @@ ifeq ($(DEBUG_DDR_INPUT_CONFIG), yes) $(eval $(call add_define, DEBUG_DDR_INPUT_CONFIG)) endif +# Tolerant SPD compare workaround is for a dual-DIMM pair whose +# base/module CRCs differ but whose timing-relevant bytes match +# Default off: a CRC mismatch is a hard error unless a board +# wants to be tolerant for such cases. +ifeq ($(NXP_DDR_DUAL_DIMM_TOLERANT), yes) +$(eval $(call add_define,NXP_DDR_DUAL_DIMM_TOLERANT)) +endif + DDR_CNTLR_SOURCES := $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/ddr.c \ $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/ddrc.c \ $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/dimm.c \ diff --git a/drivers/nxp/ddr/nxp-ddr/ddrc.c b/drivers/nxp/ddr/nxp-ddr/ddrc.c index 4133fac1a..24cc0775e 100644 --- a/drivers/nxp/ddr/nxp-ddr/ddrc.c +++ b/drivers/nxp/ddr/nxp-ddr/ddrc.c @@ -426,19 +426,18 @@ after_reset: mb(); isb(); } else { - /* wait for PHY complete */ - timeout = 40; - while (((ddr_in32(&ddr->ddr_dsr2) & 0x4) != 0) && + /* Wait up to 50 ms for DDR_DSR2[2] PHY_INIT_CMPLT to be set. */ + timeout = 100; + while (((ddr_in32(&ddr->ddr_dsr2) & 0x4) == 0) && (timeout > 0)) { udelay(500); timeout--; } - if (timeout <= 0) { - printf("PHY handshake timeout, ddr_dsr2 = %x\n", - ddr_in32(&ddr->ddr_dsr2)); + if (timeout > 0) { + debug("PHY init complete (DSR2[2]=1) in ~%d ms\n", + (100 - timeout) / 2); } else { - debug("PHY handshake completed, timer remains %d\n", - timeout); + WARN("PHY init NOT complete after 50 ms (DSR2[2]=0) -> proceeding, training will report any real fault\n"); } } diff --git a/drivers/st/bsec/bsec3.c b/drivers/st/bsec/bsec3.c index 67370278f..a6b2717f8 100644 --- a/drivers/st/bsec/bsec3.c +++ b/drivers/st/bsec/bsec3.c @@ -42,7 +42,7 @@ static uint32_t otp_bank(uint32_t otp) static uint32_t otp_bit_mask(uint32_t otp) { - return BIT(otp & BSEC_OTP_MASK); + return BIT_32(otp & BSEC_OTP_MASK); } /* diff --git a/drivers/st/clk/clk-stm32-core.c b/drivers/st/clk/clk-stm32-core.c index a4bddbf4d..a5e6b1de6 100644 --- a/drivers/st/clk/clk-stm32-core.c +++ b/drivers/st/clk/clk-stm32-core.c @@ -71,7 +71,7 @@ static int clk_gate_enable(struct stm32_clk_priv *priv, int id) const struct clk_stm32 *clk = _clk_get(priv, id); struct clk_gate_cfg *cfg = clk->clock_cfg; - mmio_setbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx)); + mmio_setbits_32(priv->base + cfg->offset, BIT_32(cfg->bit_idx)); /* Make sure the clock register has been written */ (void)mmio_read_32(priv->base + cfg->offset); @@ -86,7 +86,7 @@ static void clk_gate_disable(struct stm32_clk_priv *priv, int id) dmbsy(); /* Ensure previous transactions are performed. */ - mmio_clrbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx)); + mmio_clrbits_32(priv->base + cfg->offset, BIT_32(cfg->bit_idx)); /* Make sure the clock register has been written */ (void)mmio_read_32(priv->base + cfg->offset); @@ -97,7 +97,7 @@ static bool clk_gate_is_enabled(struct stm32_clk_priv *priv, int id) const struct clk_stm32 *clk = _clk_get(priv, id); struct clk_gate_cfg *cfg = clk->clock_cfg; - return ((mmio_read_32(priv->base + cfg->offset) & BIT(cfg->bit_idx)) != 0U); + return ((mmio_read_32(priv->base + cfg->offset) & BIT_32(cfg->bit_idx)) != 0U); } const struct stm32_clk_ops clk_gate_ops = { @@ -112,9 +112,9 @@ void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id) uintptr_t addr = priv->base + gate->offset; if (gate->set_clr != 0U) { - mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT(gate->bit_idx)); + mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT_32(gate->bit_idx)); } else { - mmio_clrbits_32(addr, BIT(gate->bit_idx)); + mmio_clrbits_32(addr, BIT_32(gate->bit_idx)); } } @@ -124,10 +124,10 @@ int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id) uintptr_t addr = priv->base + gate->offset; if (gate->set_clr != 0U) { - mmio_write_32(addr, BIT(gate->bit_idx)); + mmio_write_32(addr, BIT_32(gate->bit_idx)); } else { - mmio_setbits_32(addr, BIT(gate->bit_idx)); + mmio_setbits_32(addr, BIT_32(gate->bit_idx)); } return 0; @@ -151,7 +151,7 @@ static const struct stm32_clk_ops *_clk_get_ops(struct stm32_clk_priv *priv, int return priv->ops_array[clk->ops]; } -#define clk_div_mask(_width) GENMASK(((_width) - 1U), 0U) +#define clk_div_mask(_width) GENMASK_32(((_width) - 1U), 0U) static unsigned int _get_table_div(const struct clk_div_table *table, unsigned int val) @@ -176,11 +176,11 @@ static unsigned int _get_div(const struct clk_div_table *table, } if ((flags & CLK_DIVIDER_POWER_OF_TWO) != 0UL) { - return BIT(val); + return BIT_32(val); } if ((flags & CLK_DIVIDER_MAX_AT_ZERO) != 0UL) { - return (val != 0U) ? val : BIT(width); + return (val != 0U) ? val : BIT_32(width); } if (table != NULL) { @@ -208,7 +208,7 @@ int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel) timeout = timeout_init_us(CLKSRC_TIMEOUT); - mask = BIT(mux->bitrdy); + mask = BIT_32(mux->bitrdy); while ((mmio_read_32(address) & mask) == 0U) { if (timeout_elapsed(timeout)) { @@ -708,7 +708,7 @@ int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t val } timeout = timeout_init_us(CLKSRC_TIMEOUT); - mask = BIT(divider->bitrdy); + mask = BIT_32(divider->bitrdy); while ((mmio_read_32(address) & mask) == 0U) { if (timeout_elapsed(timeout)) { @@ -724,12 +724,12 @@ int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id, { const struct gate_cfg *gate = &priv->gates[gate_id]; uintptr_t address = priv->base + gate->offset; - uint32_t mask_rdy = BIT(gate->bit_idx); + uint32_t mask_rdy = BIT_32(gate->bit_idx); uint64_t timeout; uint32_t mask_test; if (ready_on) { - mask_test = BIT(gate->bit_idx); + mask_test = BIT_32(gate->bit_idx); } else { mask_test = 0U; } @@ -757,10 +757,10 @@ int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int id) uintptr_t addr = priv->base + gate->offset; if (gate->set_clr != 0U) { - mmio_write_32(addr, BIT(gate->bit_idx)); + mmio_write_32(addr, BIT_32(gate->bit_idx)); } else { - mmio_setbits_32(addr, BIT(gate->bit_idx)); + mmio_setbits_32(addr, BIT_32(gate->bit_idx)); } return 0; @@ -774,21 +774,21 @@ void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int id) uintptr_t addr = priv->base + gate->offset; if (gate->set_clr != 0U) { - mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT(gate->bit_idx)); + mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT_32(gate->bit_idx)); } else { - mmio_clrbits_32(addr, BIT(gate->bit_idx)); + mmio_clrbits_32(addr, BIT_32(gate->bit_idx)); } } bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id) { const struct gate_cfg *gate; - uint32_t addr; + uintptr_t addr; gate = &priv->gates[gate_id]; addr = priv->base + gate->offset; - return ((mmio_read_32(addr) & BIT(gate->bit_idx)) != 0U); + return ((mmio_read_32(addr) & BIT_32(gate->bit_idx)) != 0U); } bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int id) @@ -826,8 +826,8 @@ unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv, return (unsigned long)(rate / cfg->div); }; -#define APB_DIV_MASK GENMASK(2, 0) -#define TIM_PRE_MASK BIT(0) +#define APB_DIV_MASK GENMASK_32(2, 0) +#define TIM_PRE_MASK BIT_32(0) static unsigned long timer_recalc_rate(struct stm32_clk_priv *priv, int id, unsigned long prate) diff --git a/drivers/st/clk/clk-stm32-core.h b/drivers/st/clk/clk-stm32-core.h index 93d4c37e4..0f8878594 100644 --- a/drivers/st/clk/clk-stm32-core.h +++ b/drivers/st/clk/clk-stm32-core.h @@ -139,7 +139,7 @@ struct clk_gate_cfg { #define DIV_NO_BIT_RDY UINT8_MAX #define MASK_WIDTH_SHIFT(_width, _shift) \ - GENMASK(((_width) + (_shift) - 1U), (_shift)) + GENMASK_32(((_width) + (_shift) - 1U), (_shift)) void clk_stm32_rcc_regs_lock(void); void clk_stm32_rcc_regs_unlock(void); diff --git a/drivers/st/clk/clk-stm32mp2.c b/drivers/st/clk/clk-stm32mp2.c index f9460016d..f34739ae9 100644 --- a/drivers/st/clk/clk-stm32mp2.c +++ b/drivers/st/clk/clk-stm32mp2.c @@ -727,11 +727,11 @@ static void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id, address = priv->base + bypass_data->offset; if (digbyp) { - mmio_setbits_32(address, BIT(bypass_data->bit_digbyp)); + mmio_setbits_32(address, BIT_32(bypass_data->bit_digbyp)); } if (bypass || digbyp) { - mmio_setbits_32(address, BIT(bypass_data->bit_byp)); + mmio_setbits_32(address, BIT_32(bypass_data->bit_byp)); } } @@ -750,7 +750,7 @@ static void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id, address = priv->base + css_data->offset; if (css) { - mmio_setbits_32(address, BIT(css_data->bit_css)); + mmio_setbits_32(address, BIT_32(css_data->bit_css)); } } @@ -770,7 +770,7 @@ static void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id, address = priv->base + drive_data->offset; - mask = (BIT(drive_data->drv_width) - 1U) << drive_data->drv_shift; + mask = (BIT_32(drive_data->drv_width) - 1U) << drive_data->drv_shift; /* * Warning: not recommended to switch directly from "high drive" @@ -2137,10 +2137,10 @@ static int wait_predivsr(uint16_t channel) if (channel < __WORD_BIT) { previvsr = rcc_base + RCC_PREDIVSR1; - channel_bit = BIT(channel); + channel_bit = BIT_32(channel); } else { previvsr = rcc_base + RCC_PREDIVSR2; - channel_bit = BIT(channel - __WORD_BIT); + channel_bit = BIT_32(channel - __WORD_BIT); } timeout = timeout_init_us(CLKDIV_TIMEOUT); @@ -2165,10 +2165,10 @@ static int wait_findivsr(uint16_t channel) if (channel < __WORD_BIT) { finvivsr = rcc_base + RCC_FINDIVSR1; - channel_bit = BIT(channel); + channel_bit = BIT_32(channel); } else { finvivsr = rcc_base + RCC_FINDIVSR2; - channel_bit = BIT(channel - __WORD_BIT); + channel_bit = BIT_32(channel - __WORD_BIT); } timeout = timeout_init_us(CLKDIV_TIMEOUT); diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index 45bdc88ba..1c50d75da 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -211,22 +211,6 @@ static const struct mux_cfg parent_mp15[MUX_NB] = { #define MASK_WIDTH_SHIFT(_width, _shift) \ GENMASK(((_width) + (_shift) - 1U), (_shift)) -int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id) -{ - const struct mux_cfg *mux; - uint32_t mask; - - if (mux_id >= priv->nb_parents) { - panic(); - } - - mux = &priv->parents[mux_id]; - - mask = MASK_WIDTH_SHIFT(mux->width, mux->shift); - - return (mmio_read_32(priv->base + mux->offset) & mask) >> mux->shift; -} - static int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel) { const struct mux_cfg *mux = &priv->parents[pid]; @@ -264,7 +248,7 @@ static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t val) return clk_mux_set_parent(priv, mux, sel); } -int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value) +static int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value) { const struct div_cfg *divider; uintptr_t address; diff --git a/drivers/st/crypto/stm32_rng.c b/drivers/st/crypto/stm32_rng.c index 9e5135869..c6e89a105 100644 --- a/drivers/st/crypto/stm32_rng.c +++ b/drivers/st/crypto/stm32_rng.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2025, STMicroelectronics - All Rights Reserved + * Copyright (c) 2022-2026, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -320,14 +320,14 @@ int stm32_rng_init(void) if (dt_rng.reset >= 0) { - ret = stm32mp_reset_assert((unsigned long)dt_rng.reset, TIMEOUT_US_1MS); + ret = stm32mp_reset_assert((uint32_t)dt_rng.reset, TIMEOUT_US_1MS); if (ret != 0) { panic(); } udelay(20); - ret = stm32mp_reset_deassert((unsigned long)dt_rng.reset, TIMEOUT_US_1MS); + ret = stm32mp_reset_deassert((uint32_t)dt_rng.reset, TIMEOUT_US_1MS); if (ret != 0) { panic(); } diff --git a/drivers/st/ddr/stm32mp_ddr.c b/drivers/st/ddr/stm32mp_ddr.c index d25c22572..bbe29da72 100644 --- a/drivers/st/ddr/stm32mp_ddr.c +++ b/drivers/st/ddr/stm32mp_ddr.c @@ -44,7 +44,7 @@ void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_r ddr_registers[type].name, i); panic(); } else { -#ifdef STM32MP2X +#if STM32MP2X if (desc[i].qd) { stm32mp_ddr_start_sw_done(priv->ctl); } @@ -52,7 +52,7 @@ void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_r value = *((uint32_t *)((uintptr_t)param + desc[i].par_offset)); mmio_write_32(ptr, value); -#ifdef STM32MP2X +#if STM32MP2X if (desc[i].qd) { stm32mp_ddr_wait_sw_done_ack(priv->ctl); } diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c index 2d64de322..45b28ff1a 100644 --- a/drivers/st/gpio/stm32_gpio.c +++ b/drivers/st/gpio/stm32_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2024, STMicroelectronics - All Rights Reserved + * Copyright (c) 2016-2026, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -282,16 +282,16 @@ static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type, clk_disable(clock); -#ifdef STM32MP1X +#if STM32MP1X if (status == DT_SECURE) { stm32mp_register_secure_gpio(bank, pin); -#if !IMAGE_BL2 +#ifndef IMAGE_BL2 set_gpio_secure_cfg(bank, pin, true); #endif } else { stm32mp_register_non_secure_gpio(bank, pin); -#if !IMAGE_BL2 +#ifndef IMAGE_BL2 set_gpio_secure_cfg(bank, pin, false); #endif } @@ -310,9 +310,9 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure) clk_enable(clock); if (secure) { - mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); + mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT_32(pin)); } else { - mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); + mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT_32(pin)); } clk_disable(clock); @@ -336,9 +336,9 @@ void set_gpio_level(uint32_t bank, uint32_t pin, enum gpio_level level) clk_enable(clock); if (level == GPIO_LEVEL_HIGH) { - mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin)); + mmio_write_32(base + GPIO_BSRR_OFFSET, BIT_32(pin)); } else { - mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin + 16U)); + mmio_write_32(base + GPIO_BSRR_OFFSET, BIT_32(pin + 16U)); } VERBOSE("GPIO %u level set to 0x%x\n", bank, @@ -357,7 +357,7 @@ enum gpio_level get_gpio_level(uint32_t bank, uint32_t pin) clk_enable(clock); - if (mmio_read_32(base + GPIO_IDR_OFFSET) & BIT(pin)) { + if (mmio_read_32(base + GPIO_IDR_OFFSET) & BIT_32(pin)) { level = GPIO_LEVEL_HIGH; } diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c index e07d9e7f8..d3db6ce13 100644 --- a/drivers/st/mmc/stm32_sdmmc2.c +++ b/drivers/st/mmc/stm32_sdmmc2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2024, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2026, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -129,7 +129,7 @@ #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" #endif -#ifdef STM32MP1X +#if STM32MP1X #define SDMMC_FIFO_SIZE 64U #else #define SDMMC_FIFO_SIZE 1024U @@ -163,7 +163,7 @@ static struct stm32_sdmmc2_params sdmmc2_params; static bool next_cmd_is_acmd; #pragma weak plat_sdmmc2_use_dma -bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) +bool plat_sdmmc2_use_dma(uintptr_t instance, uintptr_t memory) { return false; } diff --git a/drivers/st/pmic/stm32mp_pmic2.c b/drivers/st/pmic/stm32mp_pmic2.c index 27488ee88..3309311c2 100644 --- a/drivers/st/pmic/stm32mp_pmic2.c +++ b/drivers/st/pmic/stm32mp_pmic2.c @@ -23,7 +23,7 @@ #define PMIC_NODE_NOT_FOUND 1 struct regul_handle_s { - const uint32_t id; + const uint8_t id; uint16_t bypass_mv; }; @@ -198,11 +198,6 @@ void pmic_switch_off(void) panic(); } -int pmic_voltages_init(void) -{ - return 0; -} - static int pmic2_set_state(const struct regul_description *desc, bool enable) { struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data; @@ -310,26 +305,25 @@ static int pmic2_list_voltages(const struct regul_description *desc, static int pmic2_set_flag(const struct regul_description *desc, uint16_t flag) { struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data; - uint32_t id = regul->id; int ret = -EPERM; VERBOSE("%s: set_flag 0x%x\n", desc->node_name, flag); switch (flag) { case REGUL_PULL_DOWN: - ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_PULL_DOWN, 1U); + ret = stpmic2_regulator_set_prop(pmic2, regul->id, STPMIC2_PULL_DOWN, 1U); break; case REGUL_OCP: - ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_OCP, 1U); + ret = stpmic2_regulator_set_prop(pmic2, regul->id, STPMIC2_OCP, 1U); break; case REGUL_SINK_SOURCE: - ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_SINK_SOURCE, 1U); + ret = stpmic2_regulator_set_prop(pmic2, regul->id, STPMIC2_SINK_SOURCE, 1U); break; case REGUL_ENABLE_BYPASS: - ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_BYPASS, 1U); + ret = stpmic2_regulator_set_prop(pmic2, regul->id, STPMIC2_BYPASS, 1U); break; case REGUL_MASK_RESET: - ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_MASK_RESET, 1U); + ret = stpmic2_regulator_set_prop(pmic2, regul->id, STPMIC2_MASK_RESET, 1U); break; default: ERROR("Invalid flag %u", flag); @@ -546,7 +540,7 @@ void initialize_pmic(void) return; } -#if IMAGE_BL2 +#ifdef IMAGE_BL2 #if LOG_LEVEL >= LOG_LEVEL_INFO if (stpmic2_get_version(pmic2, &val) != 0) { ERROR("Failed to access PMIC\n"); diff --git a/drivers/st/reset/stm32mp2_reset.c b/drivers/st/reset/stm32mp2_reset.c index 0918df59e..d8619aa6b 100644 --- a/drivers/st/reset/stm32mp2_reset.c +++ b/drivers/st/reset/stm32mp2_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, STMicroelectronics - All Rights Reserved + * Copyright (c) 2024-2026, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,7 +28,7 @@ static uint8_t id2reg_bit_pos(unsigned int reset_id) static int reset_toggle(uint32_t id, unsigned int to_us, bool reset_status) { uint32_t offset = id2reg_offset(id); - uint32_t bitmsk = BIT(id2reg_bit_pos(id)); + uint32_t bitmsk = BIT_32(id2reg_bit_pos(id)); uint32_t bit_check; uintptr_t rcc_base = stm32mp_rcc_base(); diff --git a/drivers/st/rif/stm32_rifsc.c b/drivers/st/rif/stm32_rifsc.c index f025c31bd..977781745 100644 --- a/drivers/st/rif/stm32_rifsc.c +++ b/drivers/st/rif/stm32_rifsc.c @@ -29,7 +29,7 @@ void stm32_rifsc_ip_configure(int rimu_id, int rifsc_id, uint32_t param) assert(rifsc_id < STM32MP25_RIFSC_MAX_ID); #endif /* STM32MP25 */ - bit = BIT(rifsc_id % U(32)); + bit = BIT_32(rifsc_id % U(32)); /* Set peripheral accesses to Secure/Privilege only */ mmio_setbits_32(RIFSC_BASE + _RIFSC_RISC_SECCFGR(rifsc_id), bit); diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 3f0d3a7d2..0ddad2733 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -80,6 +80,15 @@ #endif /******************************************************************************* + * Definitions for CPU system register interface to GIC + ******************************************************************************/ +/* ICC_SRE bit definitions */ +#define ICC_SRE_EN_BIT BIT_32(3) +#define ICC_SRE_DIB_BIT BIT_32(2) +#define ICC_SRE_DFB_BIT BIT_32(1) +#define ICC_SRE_SRE_BIT BIT_32(0) + +/******************************************************************************* * Generic timer memory mapped registers & offsets ******************************************************************************/ #define CNTCR_OFF U(0x000) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index bbd04ded1..4dbf8c0a1 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -124,6 +124,12 @@ #define ICC_EOIR1_EL1 S3_0_c12_c12_1 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 +/* ICC_SRE bit definitions */ +#define ICC_SRE_EN_BIT BIT_32(3) +#define ICC_SRE_DIB_BIT BIT_32(2) +#define ICC_SRE_DFB_BIT BIT_32(1) +#define ICC_SRE_SRE_BIT BIT_32(0) + /******************************************************************************* * Definitions for EL2 system registers for save/restore routine ******************************************************************************/ @@ -1992,8 +1998,9 @@ * FEAT_MEC - Memory Encryption Contexts ******************************************************************************/ #define MECIDR_EL2 S3_4_C10_C8_7 -#define MECIDR_EL2_MECIDWidthm1_MASK U(0xf) #define MECIDR_EL2_MECIDWidthm1_SHIFT U(0) +#define MECIDR_EL2_MECIDWidthm1_WIDTH U(4) +#define MECIDR_EL2_MECIDWidthm1_MASK GENMASK(3, 0) /****************************************************************************** * FEAT_FGWTE3 - Fine Grained Write Trap diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index c799b0c53..ba2a627c8 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -272,7 +272,7 @@ void disable_mpu_icache_el2(void); #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) -#if ENABLE_FEAT_D128 && !IMAGE_BL32 +#if ENABLE_FEAT_D128 && !defined(IMAGE_BL32) /* Don't use mrrs/msrr read/write implementation with tspd, * While using SPD=tspd, tspd compiles with current arch_helpers * thus trying to use mrrs/msrr read/write from Secure-world. @@ -305,7 +305,7 @@ DEFINE_SYSREG_RW_FUNCS(vttbr_el2) DEFINE_RENAME_SYSREG_RW_FUNCS(rcwmask_el1, RCWMASK_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(rcwsmask_el1, RCWSMASK_EL1) -#endif /* ENABLE_FEAT_D128 && !IMAGE_BL32 */ +#endif /* ENABLE_FEAT_D128 && !defined(IMAGE_BL32) */ DEFINE_IDREG_READ_FUNC(id_pfr0_el1) DEFINE_IDREG_READ_FUNC(id_pfr1_el1) diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index aa1d197fb..2181b731a 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -78,7 +78,7 @@ feat_sctlr2_not_supported\@: * --------------------------------------------------------------------- */ mov_imm x0, SCR_RESET_VAL -#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 +#if defined(IMAGE_BL31) && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 mrs x1, id_aa64pfr0_el1 and x1, x1, #MASK(ID_AA64PFR0_SEL2) cbz x1, 1f diff --git a/include/common/bl_common.ld.h b/include/common/bl_common.ld.h index 2273bc54b..282751b5c 100644 --- a/include/common/bl_common.ld.h +++ b/include/common/bl_common.ld.h @@ -84,7 +84,7 @@ /* * The base xlat table * - * It is put into the rodata section if PLAT_RO_XLAT_TABLES=1, + * It is put into the rodata section if PLAT_RO_XLAT_TABLES is defined, * or into the bss section otherwise. */ #define BASE_XLAT_TABLE \ @@ -93,7 +93,7 @@ *(.base_xlat_table) \ __BASE_XLAT_TABLE_END__ = .; -#if PLAT_RO_XLAT_TABLES +#ifdef PLAT_RO_XLAT_TABLES #define BASE_XLAT_TABLE_RO BASE_XLAT_TABLE #define BASE_XLAT_TABLE_BSS #else diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 07d632f8f..8669f97f4 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -274,12 +274,6 @@ /******************************************************************************* * GICv3 and 3.1 CPU interface registers & constants ******************************************************************************/ -/* ICC_SRE bit definitions */ -#define ICC_SRE_EN_BIT BIT_32(3) -#define ICC_SRE_DIB_BIT BIT_32(2) -#define ICC_SRE_DFB_BIT BIT_32(1) -#define ICC_SRE_SRE_BIT BIT_32(0) - /* ICC_IGRPEN1_EL3 bit definitions */ #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 diff --git a/include/drivers/auth/auth_mod.h b/include/drivers/auth/auth_mod.h index 28aa40784..a58aa76de 100644 --- a/include/drivers/auth/auth_mod.h +++ b/include/drivers/auth/auth_mod.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,7 +18,7 @@ */ #define IMG_FLAG_AUTHENTICATED (1 << 0) -#if COT_DESC_IN_DTB && !IMAGE_BL1 +#if COT_DESC_IN_DTB && !defined(IMAGE_BL1) /* * Authentication image descriptor */ @@ -40,7 +40,7 @@ typedef struct auth_img_desc_s { const auth_method_desc_t *const img_auth_methods; const auth_param_desc_t *const authenticated_data; } auth_img_desc_t; -#endif /* COT_DESC_IN_DTB && !IMAGE_BL1 */ +#endif /* COT_DESC_IN_DTB && !defined(IMAGE_BL1) */ /* Public functions */ #if TRUSTED_BOARD_BOOT diff --git a/include/drivers/partition/partition.h b/include/drivers/partition/partition.h index ed6d13399..6c5b40a73 100644 --- a/include/drivers/partition/partition.h +++ b/include/drivers/partition/partition.h @@ -13,13 +13,13 @@ #include <drivers/partition/efi.h> #include <tools_share/uuid.h> -#if !PLAT_PARTITION_MAX_ENTRIES +#if !defined(PLAT_PARTITION_MAX_ENTRIES) || !PLAT_PARTITION_MAX_ENTRIES # define PLAT_PARTITION_MAX_ENTRIES 128 #endif /* PLAT_PARTITION_MAX_ENTRIES */ CASSERT(PLAT_PARTITION_MAX_ENTRIES <= 128, assert_plat_partition_max_entries); -#if !PLAT_PARTITION_BLOCK_SIZE +#if !defined(PLAT_PARTITION_BLOCK_SIZE) || !PLAT_PARTITION_BLOCK_SIZE # define PLAT_PARTITION_BLOCK_SIZE 512 #endif /* PLAT_PARTITION_BLOCK_SIZE */ diff --git a/include/drivers/st/regulator.h b/include/drivers/st/regulator.h index bf583e224..d07f84912 100644 --- a/include/drivers/st/regulator.h +++ b/include/drivers/st/regulator.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2021-2026, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -68,7 +68,7 @@ int regulator_set_flag(struct rdev *rdev, uint16_t flag); struct regul_description { const char *node_name; const struct regul_ops *ops; - const void *driver_data; + void *driver_data; const char *supply_name; const uint32_t enable_ramp_delay; }; diff --git a/include/drivers/st/stm32_sdmmc2.h b/include/drivers/st/stm32_sdmmc2.h index c83f62509..9f5e7af66 100644 --- a/include/drivers/st/stm32_sdmmc2.h +++ b/include/drivers/st/stm32_sdmmc2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2026, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,6 +30,6 @@ struct stm32_sdmmc2_params { unsigned long long stm32_sdmmc2_mmc_get_device_size(void); int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params); -bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory); +bool plat_sdmmc2_use_dma(uintptr_t instance, uintptr_t memory); #endif /* STM32_SDMMC2_H */ diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h index 970ff19e8..d1bbd2b1f 100644 --- a/include/drivers/st/stm32mp_ddr.h +++ b/include/drivers/st/stm32mp_ddr.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved + * Copyright (C) 2022-2026, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -28,7 +28,7 @@ enum stm32mp_ddr_reg_type { struct stm32mp_ddr_reg_desc { uint16_t offset; /* Offset for base address */ uint8_t par_offset; /* Offset for parameter array */ -#ifdef STM32MP2X +#if STM32MP2X bool qd; /* quasi-dynamic register if true */ #endif }; diff --git a/include/drivers/st/stm32mp_pmic.h b/include/drivers/st/stm32mp_pmic.h index ba25a6ed1..cd185497d 100644 --- a/include/drivers/st/stm32mp_pmic.h +++ b/include/drivers/st/stm32mp_pmic.h @@ -33,7 +33,7 @@ bool initialize_pmic_i2c(void); */ void initialize_pmic(void); -#if DEBUG +#if DEBUG && !STM32MP_STPMIC1L void print_pmic_info_and_debug(void); #else static inline void print_pmic_info_and_debug(void) @@ -46,7 +46,14 @@ static inline void print_pmic_info_and_debug(void) * * Returns 0 on success, and negative values on errors */ +#if STM32MP_STPMIC1L +static inline int pmic_voltages_init(void) +{ + return 0; +} +#else int pmic_voltages_init(void); +#endif /* * pmic_switch_off - switch off the platform with PMIC diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index a25e20cfb..334ab7cc4 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -547,7 +547,7 @@ .endm -#if __clang_major__ < 17 +#if defined(__clang_major__) && __clang_major__ < 17 /* * A problem with clang version < 17 can cause resolving nested * 'cfi_startproc' to fail compilation. diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index 7a6eebacc..bf08036b0 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -7,15 +7,15 @@ #ifndef CONTEXT_H #define CONTEXT_H -#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) -#include <lib/el3_runtime/context_el2.h> -#else +#if !(CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) /** * El1 context is required either when: - * IMAGE_BL1 || ((!CTX_INCLUDE_EL2_REGS) && IMAGE_BL31) + * defined(IMAGE_BL1) || ((!CTX_INCLUDE_EL2_REGS) && defined(IMAGE_BL31)) */ #include <lib/el3_runtime/context_el1.h> -#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ +#else +#include <lib/el3_runtime/context_el2.h> +#endif /* !(CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) */ #include <lib/el3_runtime/simd_ctx.h> #include <lib/utils_def.h> @@ -188,12 +188,12 @@ ******************************************************************************/ #define CTX_CPTR_EL3 U(0x0) #define CTX_MPAM3_EL3 U(0x8) -#if (ENABLE_FEAT_IDTE3 && IMAGE_BL31) +#if (ENABLE_FEAT_IDTE3 && defined(IMAGE_BL31)) #define CTX_IDREGS_EL3 U(0x10) #define CTX_PERWORLD_EL3STATE_END U(0x80) #else #define CTX_PERWORLD_EL3STATE_END U(0x10) -#endif /* ENABLE_FEAT_IDTE3 && IMAGE_BL31 */ +#endif /* ENABLE_FEAT_IDTE3 && defined(IMAGE_BL31) */ #ifndef __ASSEMBLER__ @@ -315,7 +315,7 @@ typedef struct cpu_context { ddc_cap_t ddc_el0; -#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) +#if (CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) el2_sysregs_t el2_sysregs_ctx; #else /* El1 context should be included only either for IMAGE_BL1, @@ -339,7 +339,7 @@ typedef struct cpu_context { typedef struct per_world_context { uint64_t ctx_cptr_el3; uint64_t ctx_mpam3_el3; -#if (ENABLE_FEAT_IDTE3 && IMAGE_BL31) +#if (ENABLE_FEAT_IDTE3 && defined(IMAGE_BL31)) perworld_idregs_t idregs; #endif } per_world_context_t; @@ -363,7 +363,7 @@ extern per_world_context_t per_world_context[CPU_CONTEXT_NUM]; /* Macros to access members of the 'cpu_context_t' structure */ #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) -#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) +#if (CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) #define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx) #else #define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) @@ -434,7 +434,7 @@ void fpregs_context_restore(simd_regs_t *regs); * |______________________|______________________|____________________________| * ============================================================================ ******************************************************************************/ -#if (IMAGE_BL1 || ((ERRATA_SPECULATIVE_AT) || (!CTX_INCLUDE_EL2_REGS))) +#if (defined(IMAGE_BL1) || ((ERRATA_SPECULATIVE_AT) || (!CTX_INCLUDE_EL2_REGS))) static inline void write_ctx_sctlr_el1_reg_errata(cpu_context_t *ctx, u_register_t val) { @@ -476,7 +476,7 @@ static inline u_register_t read_ctx_tcr_el1_reg_errata(cpu_context_t *ctx) #endif /* ERRATA_SPECULATIVE_AT */ } -#endif /* (IMAGE_BL1 || ((ERRATA_SPECULATIVE_AT) || (!CTX_INCLUDE_EL2_REGS))) */ +#endif /* (defined(IMAGE_BL1) || ((ERRATA_SPECULATIVE_AT) || (!CTX_INCLUDE_EL2_REGS))) */ #endif /* __ASSEMBLER__ */ diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h index 99bfbbab3..013d60dd2 100644 --- a/include/lib/el3_runtime/context_mgmt.h +++ b/include/lib/el3_runtime/context_mgmt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,7 +41,7 @@ void cm_init_percpu_once_regs(void); void cm_sysregs_context_save_amu(unsigned int security_state); void cm_sysregs_context_restore_amu(unsigned int security_state); -#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) +#if (CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) void cm_el2_sysregs_context_save_gic(uint32_t security_state); void cm_el2_sysregs_context_restore_gic(uint32_t security_state); void cm_el2_sysregs_context_save(uint32_t security_state); @@ -49,7 +49,7 @@ void cm_el2_sysregs_context_restore(uint32_t security_state); #else void cm_el1_sysregs_context_save(uint32_t security_state); void cm_el1_sysregs_context_restore(uint32_t security_state); -#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ +#endif /* (CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) */ void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint); void cm_set_elr_spsr_el3(uint32_t security_state, diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h index 3f9c2f9f4..ef25b3a4d 100644 --- a/include/lib/el3_runtime/cpu_data.h +++ b/include/lib/el3_runtime/cpu_data.h @@ -48,13 +48,6 @@ #define CPU_DATA_CPU_DATA_PMF_TS_SIZE 0 #define CPU_DATA_CPU_DATA_PMF_TS_ALIGN 1 #endif /* ENABLE_RUNTIME_INSTRUMENTATION */ -#ifdef PLAT_PCPU_DATA_SIZE -#define CPU_DATA_PLATFORM_CPU_DATA_SIZE PLAT_PCPU_DATA_SIZE -#define CPU_DATA_PLATFORM_CPU_DATA_ALIGN 1 -#else /* PLAT_PCPU_DATA_SIZE */ -#define CPU_DATA_PLATFORM_CPU_DATA_SIZE 0 -#define CPU_DATA_PLATFORM_CPU_DATA_ALIGN 1 -#endif /* PLAT_PCPU_DATA_SIZE */ #if EL3_EXCEPTION_HANDLING /* buffer space for EHF data is sizeof(pe_exc_data_t) */ #define CPU_DATA_EHF_DATA_SIZE 8 @@ -80,8 +73,7 @@ #define CPU_DATA_PSCI_SVC_CPU_DATA ROUND_UP_2EVAL((CPU_DATA_CPU_OPS_PTR + CPU_DATA_CPU_OPS_PTR_SIZE), CPU_DATA_PSCI_SVC_CPU_DATA_ALIGN) #define CPU_DATA_APIAKEY ROUND_UP_2EVAL((CPU_DATA_PSCI_SVC_CPU_DATA + CPU_DATA_PSCI_SVC_CPU_DATA_SIZE), CPU_DATA_APIAKEY_ALIGN) #define CPU_DATA_CPU_DATA_PMF_TS ROUND_UP_2EVAL((CPU_DATA_APIAKEY + CPU_DATA_APIAKEY_SIZE), CPU_DATA_CPU_DATA_PMF_TS_ALIGN) -#define CPU_DATA_PLATFORM_CPU_DATA ROUND_UP_2EVAL((CPU_DATA_CPU_DATA_PMF_TS + CPU_DATA_CPU_DATA_PMF_TS_SIZE), CPU_DATA_PLATFORM_CPU_DATA_ALIGN) -#define CPU_DATA_EHF_DATA ROUND_UP_2EVAL((CPU_DATA_PLATFORM_CPU_DATA + CPU_DATA_PLATFORM_CPU_DATA_SIZE), CPU_DATA_EHF_DATA_ALIGN) +#define CPU_DATA_EHF_DATA ROUND_UP_2EVAL((CPU_DATA_CPU_DATA_PMF_TS + CPU_DATA_CPU_DATA_PMF_TS_SIZE), CPU_DATA_EHF_DATA_ALIGN) #define CPU_DATA_PCPU_IDREGS ROUND_UP_2EVAL((CPU_DATA_EHF_DATA + CPU_DATA_EHF_DATA_SIZE), CPU_DATA_PCPU_IDREGS_ALIGN) #define CPU_DATA_SIZE ROUND_UP_2EVAL((CPU_DATA_PCPU_IDREGS + CPU_DATA_PCPU_IDREGS_SIZE), CPU_DATA_SIZE_ALIGN) @@ -132,9 +124,6 @@ typedef struct cpu_data { #if ENABLE_RUNTIME_INSTRUMENTATION uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT]; #endif -#if PLAT_PCPU_DATA_SIZE - uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE]; -#endif #if EL3_EXCEPTION_HANDLING pe_exc_data_t ehf_data; #endif @@ -160,9 +149,6 @@ CPU_DATA_ASSERT_OFFSET(APIAKEY, apiakey); #if ENABLE_RUNTIME_INSTRUMENTATION CPU_DATA_ASSERT_OFFSET(CPU_DATA_PMF_TS, cpu_data_pmf_ts); #endif -#if PLAT_PCPU_DATA_SIZE -CPU_DATA_ASSERT_OFFSET(PLATFORM_CPU_DATA, platform_cpu_data); -#endif #if EL3_EXCEPTION_HANDLING CPU_DATA_ASSERT_OFFSET(EHF_DATA, ehf_data); #endif diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h index 04e6e1521..bfc4e5ce0 100644 --- a/include/lib/xlat_tables/xlat_tables_v2.h +++ b/include/lib/xlat_tables/xlat_tables_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -390,7 +390,7 @@ int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, size_t size, uint32_t attr); int xlat_change_mem_attributes(uintptr_t base_va, size_t size, uint32_t attr); -#if PLAT_RO_XLAT_TABLES +#ifdef PLAT_RO_XLAT_TABLES /* * Change the memory attributes of the memory region encompassing the higher * level translation tables to secure read-only data. diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h index 992c94e58..77277615f 100644 --- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h +++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -71,7 +71,7 @@ struct xlat_ctx { */ uint64_t (*tables)[XLAT_TABLE_ENTRIES]; int tables_num; -#if PLAT_RO_XLAT_TABLES +#ifdef PLAT_RO_XLAT_TABLES bool readonly_tables; #endif /* @@ -126,7 +126,7 @@ struct xlat_ctx { /* do nothing */ #endif /* PLAT_XLAT_TABLES_DYNAMIC */ -#if PLAT_RO_XLAT_TABLES +#ifdef PLAT_RO_XLAT_TABLES #define XLAT_CTX_INIT_TABLE_ATTR() \ .readonly_tables = false, #else diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index 4d4682cd6..b953c2893 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -409,7 +409,6 @@ int plat_rmmd_el3_token_sign_push_req( int plat_rmmd_el3_token_sign_pull_resp(struct el3_token_sign_response *resp); size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared); int plat_rmmd_load_manifest(struct rmm_manifest *manifest); -int plat_rmmd_mecid_key_update(uint16_t mecid, unsigned int reason); uintptr_t plat_rmmd_reserve_memory(size_t size, unsigned long alignment); /* The following 4 functions are to be implemented if diff --git a/include/services/firme/firme_mecid.h b/include/services/firme/firme_mecid.h new file mode 100644 index 000000000..7ec043350 --- /dev/null +++ b/include/services/firme/firme_mecid.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2026, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FIRME_MEC_H +#define FIRME_MEC_H + +#include <stdint.h> + +#include <services/firme/firme_abi.h> + +#define FIRME_MECID_MGMT_VERSION_MAJOR U(1) +#define FIRME_MECID_MGMT_VERSION_MINOR U(0) + +#define FIRME_MEC_FNUM_REFRESH U(0x7) + +/* + * FIRME_MEC_REFRESH + * + * This function refreshes the MEC linked to a given MECID by invalidating the + * existing MEC, generating a new one, and associating the new MEC with that MECID. + * + * Supported from v1.0 + * + * Arguments + * arg0(w0): Function ID 0xC4000407 + * arg1(x1): MEC params Bits[63:48]: Reserved (SBZ). + * Bits[47:32]: MECID. + * Bits[31:1]: Reserved (SBZ). + * Bits[0]: MEC refresh reason. + * – 0b’0: Realm creation. + * – 0b’1: Realm destruction + * + * Return + * ret0(x0): Status FIRME_SUCCESS + * FIRME_NOT_SUPPORTED + * FIRME_INVALID_PARAMETERS + * FIRME_RETRY + */ +#define FIRME_MEC_REFRESH_FID FIRME_FID(FIRME_MEC_FNUM_REFRESH) + +#define MEC_REFRESH_REASON_REALM_CREATE U(0) +#define MEC_REFRESH_REASON_REALM_DESTROY U(1) + +#define MEC_PARAM_MECID_SHIFT U(32) +#define MEC_PARAM_MECID_WIDTH U(16) +#define MEC_PARAM_MECID_MASK MASK(MEC_PARAM_MECID) + +#define FIRME_MECID_FEATURE_REG_COUNT U(2) +#define FIRME_MECID_FEAT_REG0_MEC_REFRESH_BIT BIT(0) +#define FIRME_MECID_FEAT_REG1_COMMON_MECID_WIDTH_BITS_SHIFT U(0) +#define FIRME_MECID_FEAT_REG1_COMMON_MECID_WIDTH_BITS_WIDTH U(4) +#define FIRME_MECID_FEAT_REG1_COMMON_MECID_WIDTH_BITS_MASK MASK(FIRME_MECID_FEAT_REG1_COMMON_MECID_WIDTH_BITS) + +int32_t firme_mecid_service_init(void); +int plat_firme_mec_refresh(uint16_t mecid, uint8_t reason); +uint8_t plat_firme_get_common_mecid_width(void); + +#endif /* FIRME_MEC_H */ diff --git a/include/services/firme_svc.h b/include/services/firme_svc.h index c229d116b..483de0862 100644 --- a/include/services/firme_svc.h +++ b/include/services/firme_svc.h @@ -110,7 +110,10 @@ typedef struct { #define FIRME_BASE_MAX_SH_BUF_PG_CNT_MASK U(0x3FFF) #define FIRME_BASE_SERVICE_LIST_SHIFT U(16) #define FIRME_BASE_SERVICE_LIST_MASK U(0xFFFF) -#define FIRME_BASE_SERVICE_GRANULE_MGMT_BIT BIT(16) +#define FIRME_BASE_SERVICE_BIT(_id) BIT((_id) + \ + FIRME_BASE_SERVICE_LIST_SHIFT) +#define FIRME_BASE_SERVICE_GRANULE_MGMT_BIT FIRME_BASE_SERVICE_BIT(0) +#define FIRME_BASE_SERVICE_MECID_BIT FIRME_BASE_SERVICE_BIT(2) /* Granule management service feature register definitions. */ #define FIRME_GM_GPI_SET_BIT BIT(0) @@ -194,36 +197,56 @@ typedef struct { /* These are unimplemented so far and will be added in the future. */ /* Granule management service ABIs */ -#define FIRME_GM_GPI_OP_CONTINUE SMC64_FIRME_FID(U(0x12)) -#define FIRME_GM_L1_GPT_CREATE SMC64_FIRME_FID(U(0xE)) -#define FIRME_GM_L1_GPT_DESTROY SMC64_FIRME_FID(U(0xF)) +#define FIRME_GM_GPI_OP_CONTINUE_FID SMC64_FIRME_FID(U(0x12)) +#define FIRME_GM_L1_GPT_CREATE_FID SMC64_FIRME_FID(U(0xE)) +#define FIRME_GM_L1_GPT_DESTROY_FID SMC64_FIRME_FID(U(0xF)) /* IDE key management service */ -#define FIRME_IDE_KEYSET_PROG SMC64_FIRME_FID(U(0x3)) -#define FIRME_IDE_KEYSET_GO SMC64_FIRME_FID(U(0x4)) -#define FIRME_IDE_KEYSET_STOP SMC64_FIRME_FID(U(0x5)) -#define FIRME_IDE_KEYSET_POLL SMC64_FIRME_FID(U(0x6)) +#define FIRME_IDE_KEYSET_PROG_FID SMC64_FIRME_FID(U(0x3)) +#define FIRME_IDE_KEYSET_GO_FID SMC64_FIRME_FID(U(0x4)) +#define FIRME_IDE_KEYSET_STOP_FID SMC64_FIRME_FID(U(0x5)) +#define FIRME_IDE_KEYSET_POLL_FID SMC64_FIRME_FID(U(0x6)) /* MECID management service */ -#define FIRME_MEC_REFRESH SMC64_FIRME_FID(U(0x7)) +#define FIRME_MEC_REFRESH_FID SMC64_FIRME_FID(U(0x7)) + +#define MEC_REFRESH_REASON_REALM_CREATE U(0) +#define MEC_REFRESH_REASON_REALM_DESTROY U(1) + +#define MEC_PARAM_MECID_SHIFT U(32) +#define MEC_PARAM_MECID_WIDTH U(16) +#define MEC_PARAM_MECID_MASK MASK(MEC_PARAM_MECID) + +#define FIRME_MECID_FEATURE_REG_COUNT U(2) +#define FIRME_MECID_FEAT_REG0_MEC_REFRESH_BIT BIT(0) +#define FIRME_MECID_FEAT_REG1_COMMON_MECID_WIDTH_BITS_SHIFT U(0) +#define FIRME_MECID_FEAT_REG1_COMMON_MECID_WIDTH_BITS_WIDTH U(4) +#define FIRME_MECID_FEAT_REG1_COMMON_MECID_WIDTH_BITS_MASK MASK(FIRME_MECID_FEAT_REG1_COMMON_MECID_WIDTH_BITS) /* Attestation service */ -#define FIRME_ATTEST_PAT_GET SMC64_FIRME_FID(U(0x8)) -#define FIRME_ATTEST_RAK_GET SMC64_FIRME_FID(U(0x9)) -#define FIRME_ATTEST_RAT_SIGN SMC64_FIRME_FID(U(0xA)) -#define FIRME_ATTEST_PAT_EXT_CLAIMS_STAGE SMC64_FIRME_FID(U(0xB)) -#define FIRME_ATTEST_PAT_EXT_CLAIMS_CLEAR SMC64_FIRME_FID(U(0xC)) -#define FIRME_ATTEST_PAT_EXT_CLAIMS_FINALISE SMC64_FIRME_FID(U(0xD)) +#define FIRME_ATTEST_PAT_GET_FID SMC64_FIRME_FID(U(0x8)) +#define FIRME_ATTEST_RAK_GET_FID SMC64_FIRME_FID(U(0x9)) +#define FIRME_ATTEST_RAT_SIGN_FID SMC64_FIRME_FID(U(0xA)) +#define FIRME_ATTEST_PAT_EXT_CLAIMS_STAGE_FID SMC64_FIRME_FID(U(0xB)) +#define FIRME_ATTEST_PAT_EXT_CLAIMS_CLEAR_FID SMC64_FIRME_FID(U(0xC)) +#define FIRME_ATTEST_PAT_EXT_CLAIMS_FINALISE_FID SMC64_FIRME_FID(U(0xD)) /* Integrated device management service */ -#define FIRME_IDEV_OP_START SMC64_FIRME_FID(U(0x10)) -#define FIRME_IDEV_OP_CONTINUE SMC64_FIRME_FID(U(0x11)) +#define FIRME_IDEV_OP_START_FID SMC64_FIRME_FID(U(0x10)) +#define FIRME_IDEV_OP_CONTINUE_FID SMC64_FIRME_FID(U(0x11)) /* Top level handler for FIRME SMC calls. */ +int32_t firme_init(void); + uint64_t firme_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *cookie, void *handle, uint64_t flags); firme_service_info_t *firme_granule_mgmt_service_get_info(void); +firme_service_info_t *firme_mecid_service_get_info(void); + +int32_t firme_mecid_service_init(void); +int plat_firme_mec_refresh(uint16_t mecid, uint8_t reason); +uint8_t plat_firme_get_common_mecid_width(void); u_register_t firme_base_service_handler(firme_instance_e instance, uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, @@ -236,4 +259,10 @@ u_register_t firme_granule_mgmt_service_handler(firme_instance_e instance, uint64_t x4, void *cookie, void *handle, uint64_t flags); +u_register_t firme_mecid_service_handler(firme_instance_e instance, + uint32_t smc_fid, uint64_t x1, + uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, + void *handle, uint64_t flags); + #endif /* FIRME_SVC_H */ diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S index 53489ad19..f0f9c7039 100644 --- a/lib/cpus/aarch32/cortex_a15.S +++ b/lib/cpus/aarch32/cortex_a15.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -124,7 +124,7 @@ func cortex_a15_reset_func bl errata_a15_827671_wa #endif -#if IMAGE_BL32 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) +#if defined(IMAGE_BL32) && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) ldcopr r0, ACTLR orr r0, #CORTEX_A15_ACTLR_INV_BTB_BIT stcopr r0, ACTLR diff --git a/lib/cpus/aarch32/cortex_a17.S b/lib/cpus/aarch32/cortex_a17.S index 05e96169e..910962918 100644 --- a/lib/cpus/aarch32/cortex_a17.S +++ b/lib/cpus/aarch32/cortex_a17.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -121,7 +121,7 @@ func cortex_a17_reset_func bl errata_a17_852423_wa #endif -#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 +#if defined(IMAGE_BL32) && WORKAROUND_CVE_2017_5715 ldr r0, =wa_cve_2017_5715_bpiall_vbar stcopr r0, VBAR stcopr r0, MVBAR diff --git a/lib/cpus/aarch32/cortex_a9.S b/lib/cpus/aarch32/cortex_a9.S index dc5ff2703..526433f68 100644 --- a/lib/cpus/aarch32/cortex_a9.S +++ b/lib/cpus/aarch32/cortex_a9.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -58,7 +58,7 @@ endfunc check_errata_cve_2017_5715 add_erratum_entry cortex_a9, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 func cortex_a9_reset_func -#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 +#if defined(IMAGE_BL32) && WORKAROUND_CVE_2017_5715 ldr r0, =wa_cve_2017_5715_bpiall_vbar stcopr r0, VBAR stcopr r0, MVBAR diff --git a/lib/cpus/aarch64/c1_premium.S b/lib/cpus/aarch64/c1_premium.S index 38bc0561f..f6683eeef 100644 --- a/lib/cpus/aarch64/c1_premium.S +++ b/lib/cpus/aarch64/c1_premium.S @@ -110,7 +110,7 @@ check_erratum_ls c1_premium, CVE(2024, 7881), CPU_REV(0, 0) * Enables mitigation for CVE-2025-0647. */ workaround_reset_start c1_premium, CVE(2025, 647), WORKAROUND_CVE_2025_0647 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 mov x0, #WA_PATCH_SLOT(3) bl wa_cve_2025_0647_instruction_patch #endif /* IMAGE_BL31 */ @@ -174,7 +174,7 @@ func c1_premium_cpu_reg_dump ret endfunc c1_premium_cpu_reg_dump -#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 +#if WORKAROUND_CVE_2025_0647 && defined(IMAGE_BL31) declare_cpu_ops_eh c1_premium, C1_PREMIUM_MIDR, \ c1_premium_reset_func, \ c1_premium_impl_defined_el3_handler, \ diff --git a/lib/cpus/aarch64/c1_ultra.S b/lib/cpus/aarch64/c1_ultra.S index c02c787c6..e593bc4dd 100644 --- a/lib/cpus/aarch64/c1_ultra.S +++ b/lib/cpus/aarch64/c1_ultra.S @@ -113,7 +113,7 @@ check_erratum_ls c1_ultra, CVE(2024, 7881), CPU_REV(0, 0) * Enables mitigation for CVE-2025-0647. */ workaround_reset_start c1_ultra, CVE(2025, 647), WORKAROUND_CVE_2025_0647 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 mov x0, #WA_PATCH_SLOT(3) bl wa_cve_2025_0647_instruction_patch #endif /* IMAGE_BL31 */ @@ -183,7 +183,7 @@ func c1_ultra_cpu_reg_dump ret endfunc c1_ultra_cpu_reg_dump -#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 +#if WORKAROUND_CVE_2025_0647 && defined(IMAGE_BL31) declare_cpu_ops_eh c1_ultra, C1_ULTRA_MIDR, \ c1_ultra_reset_func, \ c1_ultra_impl_defined_el3_handler, \ diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 53621d1a7..d93017ce1 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -162,7 +162,7 @@ check_erratum_chosen cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537 add_erratum_entry cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537 workaround_reset_start cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 override_vector_table wa_cve_2017_5715_mmu_vbar #endif workaround_reset_end cortex_a57, CVE(2017, 5715) @@ -178,7 +178,7 @@ workaround_reset_end cortex_a57, CVE(2018, 3639) check_erratum_chosen cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 workaround_reset_start cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 override_vector_table wa_cve_2017_5715_mmu_vbar #endif workaround_reset_end cortex_a57, CVE(2022, 23960) diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index 4e919d467..13c056316 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -300,7 +300,7 @@ add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772 check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Cortex-A710 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. @@ -323,7 +323,7 @@ check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1) * Enables mitigation for CVE-2025-0647. */ workaround_reset_start cortex_a710, CVE(2025, 647), WORKAROUND_CVE_2025_0647 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 mov x0, #(WA_USE_T32_OPCODE | WA_PATCH_SLOT(0)) bl wa_cve_2025_0647_instruction_patch #endif /* IMAGE_BL31 */ @@ -391,7 +391,7 @@ func cortex_a710_cpu_reg_dump ret endfunc cortex_a710_cpu_reg_dump -#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 +#if WORKAROUND_CVE_2025_0647 && defined(IMAGE_BL31) declare_cpu_ops_eh cortex_a710, CORTEX_A710_MIDR, \ cortex_a710_reset_func, \ cortex_a710_impl_defined_el3_handler, \ diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S index f744c59d0..520be90bd 100644 --- a/lib/cpus/aarch64/cortex_a715.S +++ b/lib/cpus/aarch64/cortex_a715.S @@ -212,7 +212,7 @@ workaround_reset_end cortex_a715, ERRATUM(3711916) check_erratum_ls cortex_a715, ERRATUM(3711916), CPU_REV(1, 3) workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Cortex-A715 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S index c6fe63169..2c4be6af4 100644 --- a/lib/cpus/aarch64/cortex_a72.S +++ b/lib/cpus/aarch64/cortex_a72.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -81,7 +81,7 @@ check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367 add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367 workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 override_vector_table wa_cve_2017_5715_mmu_vbar #endif workaround_reset_end cortex_a72, CVE(2017, 5715) @@ -97,7 +97,7 @@ workaround_reset_end cortex_a72, CVE(2018, 3639) check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* Skip installing vector table again if already done for CVE(2017, 5715) */ /* * The Cortex-A72 generic vectors are overridden to apply the diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S index 3af37d471..fcc29f40c 100644 --- a/lib/cpus/aarch64/cortex_a73.S +++ b/lib/cpus/aarch64/cortex_a73.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,7 +41,7 @@ workaround_reset_end cortex_a73, ERRATUM(855423) check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1) workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 override_vector_table wa_cve_2017_5715_bpiall_vbar #endif /* IMAGE_BL31 */ workaround_reset_end cortex_a73, CVE(2017, 5715) @@ -56,7 +56,7 @@ workaround_reset_end cortex_a73, CVE(2018, 3639) check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* Skip installing vector table again for CVE_2022_23960 */ adr x0, wa_cve_2017_5715_bpiall_vbar mrs x1, vbar_el3 diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index c835d94b1..e3bf290b0 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -56,7 +56,7 @@ check_erratum_custom_start cortex_a75, ERRATUM(936184) check_erratum_custom_end cortex_a75, ERRATUM(936184) workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 override_vector_table wa_cve_2017_5715_bpiall_vbar #endif /* IMAGE_BL31 */ workaround_reset_end cortex_a75, CVE(2017, 5715) @@ -71,7 +71,7 @@ workaround_reset_end cortex_a75, CVE(2018, 3639) check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* Skip installing vector table again if already done for CVE(2017, 5715) */ adr x0, wa_cve_2017_5715_bpiall_vbar mrs x1, vbar_el3 diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 49af2ed1b..18ec13007 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -521,7 +521,7 @@ cpu_reset_func_start cortex_a76 #endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */ #endif /* WORKAROUND_CVE_2018_3639 */ -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 +#if defined(IMAGE_BL31) && WORKAROUND_CVE_2022_23960 /* * The Cortex-A76 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. This will be bypassed diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S index 5d7bc4a23..5b48d92ce 100644 --- a/lib/cpus/aarch64/cortex_a76ae.S +++ b/lib/cpus/aarch64/cortex_a76ae.S @@ -94,7 +94,7 @@ add_erratum_entry cortex_a76ae, CVE(2025, 10263), WORKAROUND_CVE_2025_10263 check_erratum_chosen cortex_a76ae, CVE(2025, 10263), WORKAROUND_CVE_2025_10263 workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Cortex-A76ae generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S index a0127bfd3..4a242d870 100644 --- a/lib/cpus/aarch64/cortex_a77.S +++ b/lib/cpus/aarch64/cortex_a77.S @@ -174,7 +174,7 @@ workaround_reset_end cortex_a77, ERRATUM(3888015) check_erratum_chosen cortex_a77, ERRATUM(3888015), ERRATA_A77_3888015 workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Cortex-A77 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index b1ecc93a9..b3b3156d1 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S @@ -244,7 +244,7 @@ workaround_reset_end cortex_a78, ERRATUM(4302972) check_erratum_chosen cortex_a78, ERRATUM(4302972), ERRATA_A78_4302972 workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Cortex-X1 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S index a53aba048..4a682c154 100644 --- a/lib/cpus/aarch64/cortex_a78_ae.S +++ b/lib/cpus/aarch64/cortex_a78_ae.S @@ -151,7 +151,7 @@ workaround_reset_end cortex_a78_ae, ERRATUM(4302973) check_erratum_chosen cortex_a78_ae, ERRATUM(4302973), ERRATA_A78_AE_4302973 workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Cortex-A78AE generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S index a8303de18..074f81d8c 100644 --- a/lib/cpus/aarch64/cortex_a78c.S +++ b/lib/cpus/aarch64/cortex_a78c.S @@ -182,7 +182,7 @@ check_erratum_chosen cortex_a78c, ERRATUM(4302974), ERRATA_A78C_4302974 check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Cortex-A78c generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. diff --git a/lib/cpus/aarch64/cortex_x1.S b/lib/cpus/aarch64/cortex_x1.S index 17c7ccad0..de96fcf77 100644 --- a/lib/cpus/aarch64/cortex_x1.S +++ b/lib/cpus/aarch64/cortex_x1.S @@ -1,5 +1,6 @@ /* * Copyright (c) 2022-2024, Google LLC. All rights reserved. + * Copyright (c) 2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -223,7 +224,7 @@ check_erratum_chosen cortex_x1, ERRATUM(4302972), ERRATA_X1_4302972 check_erratum_chosen cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 workaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Cortex-X1 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index d7bfea7be..b6aa8f7e1 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S @@ -281,7 +281,7 @@ workaround_reset_end cortex_x2, ERRATUM(4302969) check_erratum_ls cortex_x2, ERRATUM(4302969), CPU_REV(2, 1) workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Cortex-X2 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. @@ -304,7 +304,7 @@ check_erratum_chosen cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 * Enables mitigation for CVE-2025-0647. */ workaround_reset_start cortex_x2, CVE(2025, 647), WORKAROUND_CVE_2025_0647 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 mov x0, #(WA_USE_T32_OPCODE | WA_PATCH_SLOT(0)) bl wa_cve_2025_0647_instruction_patch #endif /* IMAGE_BL31 */ @@ -372,7 +372,7 @@ func cortex_x2_cpu_reg_dump ret endfunc cortex_x2_cpu_reg_dump -#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 +#if WORKAROUND_CVE_2025_0647 && defined(IMAGE_BL31) declare_cpu_ops_eh cortex_x2, CORTEX_X2_MIDR, \ cortex_x2_reset_func, \ cortex_x2_impl_defined_el3_handler, \ diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 7c01bccd4..71f4d18a1 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -169,7 +169,7 @@ workaround_reset_end cortex_x3, ERRATUM(4302966) check_erratum_ls cortex_x3, ERRATUM(4302966), CPU_REV(1, 2) workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 override_vector_table wa_cve_vbar_cortex_x3 #endif /* IMAGE_BL31 */ workaround_reset_end cortex_x3, CVE(2022, 23960) @@ -200,7 +200,7 @@ check_erratum_ls cortex_x3, CVE(2024, 7881), CPU_REV(1, 2) * Enables mitigation for CVE-2025-0647. */ workaround_reset_start cortex_x3, CVE(2025, 647), WORKAROUND_CVE_2025_0647 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 mov x0, #WA_PATCH_SLOT(3) bl wa_cve_2025_0647_instruction_patch #endif /* IMAGE_BL31 */ @@ -264,7 +264,7 @@ func cortex_x3_cpu_reg_dump ret endfunc cortex_x3_cpu_reg_dump -#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 +#if WORKAROUND_CVE_2025_0647 && defined(IMAGE_BL31) declare_cpu_ops_eh cortex_x3, CORTEX_X3_MIDR, \ cortex_x3_reset_func, \ cortex_x3_impl_defined_el3_handler, \ diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S index 5b2c7902d..75526a814 100644 --- a/lib/cpus/aarch64/cortex_x4.S +++ b/lib/cpus/aarch64/cortex_x4.S @@ -191,7 +191,7 @@ check_erratum_ls cortex_x4, CVE(2024, 7881), CPU_REV(0, 2) * Enables mitigation for CVE-2025-0647. */ workaround_reset_start cortex_x4, CVE(2025, 647), WORKAROUND_CVE_2025_0647 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 mov x0, #WA_PATCH_SLOT(3) bl wa_cve_2025_0647_instruction_patch #endif /* IMAGE_BL31 */ @@ -256,7 +256,7 @@ func cortex_x4_cpu_reg_dump ret endfunc cortex_x4_cpu_reg_dump -#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 +#if WORKAROUND_CVE_2025_0647 && defined(IMAGE_BL31) declare_cpu_ops_eh cortex_x4, CORTEX_X4_MIDR, \ cortex_x4_reset_func, \ cortex_x4_impl_defined_el3_handler, \ diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S index 98b2d9e64..e5ff2f751 100644 --- a/lib/cpus/aarch64/cortex_x925.S +++ b/lib/cpus/aarch64/cortex_x925.S @@ -123,7 +123,7 @@ check_erratum_ls cortex_x925, CVE(2024, 7881), CPU_REV(0, 1) * Enables mitigation for CVE-2025-0647. */ workaround_reset_start cortex_x925, CVE(2025, 647), WORKAROUND_CVE_2025_0647 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 mov x0, #WA_PATCH_SLOT(3) bl wa_cve_2025_0647_instruction_patch #endif /* IMAGE_BL31 */ @@ -186,7 +186,7 @@ func cortex_x925_cpu_reg_dump ret endfunc cortex_x925_cpu_reg_dump -#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 +#if WORKAROUND_CVE_2025_0647 && defined(IMAGE_BL31) declare_cpu_ops_eh cortex_x925, CORTEX_X925_MIDR, \ cortex_x925_reset_func, \ cortex_x925_impl_defined_el3_handler, \ diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index 22cd3ba4b..ffb9326e8 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -210,7 +210,7 @@ func denver_disable_dco endfunc denver_disable_dco workaround_reset_start denver, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 adr x1, workaround_bpflush_runtime_exceptions msr vbar_el3, x1 #endif diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 2db854018..729b1f5d3 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -204,7 +204,7 @@ workaround_reset_end neoverse_n1, ERRATUM(3888013) check_erratum_chosen neoverse_n1, ERRATUM(3888013), ERRATA_N1_3888013 workaround_reset_start neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Neoverse-N1 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index a3d3f470b..e81c9872e 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -250,7 +250,7 @@ workaround_reset_end neoverse_n2, ERRATUM(4302970) check_erratum_ls neoverse_n2, ERRATUM(4302970), CPU_REV(0, 3) workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Neoverse-N2 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. @@ -273,7 +273,7 @@ check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3) * Enables mitigation for CVE-2025-0647. */ workaround_reset_start neoverse_n2, CVE(2025, 647), WORKAROUND_CVE_2025_0647 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 mov x0, #(WA_USE_T32_OPCODE | WA_PATCH_SLOT(0)) bl wa_cve_2025_0647_instruction_patch #endif /* IMAGE_BL31 */ @@ -370,7 +370,7 @@ func neoverse_n2_cpu_reg_dump ret endfunc neoverse_n2_cpu_reg_dump -#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 +#if WORKAROUND_CVE_2025_0647 && defined(IMAGE_BL31) declare_cpu_ops_eh neoverse_n2, NEOVERSE_N2_MIDR, \ neoverse_n2_reset_func, \ neoverse_n2_impl_defined_el3_handler, \ diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index aaf3f201c..9ecc8d137 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -268,7 +268,7 @@ workaround_reset_end neoverse_v1, ERRATUM(3888016) check_erratum_chosen neoverse_v1, ERRATUM(3888016), ERRATA_V1_3888016 workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Neoverse-V1 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S index 64570057a..a4eede382 100644 --- a/lib/cpus/aarch64/neoverse_v2.S +++ b/lib/cpus/aarch64/neoverse_v2.S @@ -116,7 +116,7 @@ workaround_reset_end neoverse_v2, ERRATUM(4302968) check_erratum_ls neoverse_v2, ERRATUM(4302968), CPU_REV(0, 2) workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* * The Neoverse-V2 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. @@ -155,7 +155,7 @@ check_erratum_ls neoverse_v2, CVE(2024, 7881), CPU_REV(0, 2) * Enables mitigation for CVE-2025-0647. */ workaround_reset_start neoverse_v2, CVE(2025, 647), WORKAROUND_CVE_2025_0647 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 mov x0, #WA_PATCH_SLOT(3) bl wa_cve_2025_0647_instruction_patch #endif /* IMAGE_BL31 */ @@ -223,7 +223,7 @@ func neoverse_v2_cpu_reg_dump ret endfunc neoverse_v2_cpu_reg_dump -#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 +#if WORKAROUND_CVE_2025_0647 && defined(IMAGE_BL31) declare_cpu_ops_eh neoverse_v2, NEOVERSE_V2_MIDR, \ neoverse_v2_reset_func, \ neoverse_v2_impl_defined_el3_handler, \ diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S index da99801f4..1528486c2 100644 --- a/lib/cpus/aarch64/neoverse_v3.S +++ b/lib/cpus/aarch64/neoverse_v3.S @@ -122,7 +122,7 @@ check_erratum_ls neoverse_v3, CVE(2024, 7881), CPU_REV(0, 1) * Enables mitigation for CVE-2025-0647. */ workaround_reset_start neoverse_v3, CVE(2025, 647), WORKAROUND_CVE_2025_0647 -#if IMAGE_BL31 +#ifdef IMAGE_BL31 mov x0, #WA_PATCH_SLOT(3) bl wa_cve_2025_0647_instruction_patch #endif /* IMAGE_BL31 */ @@ -186,7 +186,7 @@ func neoverse_v3_cpu_reg_dump ret endfunc neoverse_v3_cpu_reg_dump -#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 +#if WORKAROUND_CVE_2025_0647 && defined(IMAGE_BL31) declare_cpu_ops_eh neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ neoverse_v3_reset_func, \ neoverse_v3_impl_defined_el3_handler, \ diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c index 7d0843086..9ac9908e6 100644 --- a/lib/cpus/errata_report.c +++ b/lib/cpus/errata_report.c @@ -96,7 +96,7 @@ static void generic_errata_report(struct cpu_ops *cpu_ops) */ void print_errata_status(void) { -#if IMAGE_BL1 +#ifdef IMAGE_BL1 struct cpu_ops *cpu_ops = get_cpu_ops_ptr(); #else struct cpu_ops *cpu_ops = get_cpu_data(cpu_ops_ptr); @@ -104,7 +104,7 @@ void print_errata_status(void) assert(cpu_ops != NULL); -#if !IMAGE_BL1 +#ifndef IMAGE_BL1 /* * Try to acquire the lock. The first CPU of each type to do so will * report errata. The others need not do anything. Never release the diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c index 3ff367049..942f7d2dd 100644 --- a/lib/el3_runtime/aarch32/context_mgmt.c +++ b/lib/el3_runtime/aarch32/context_mgmt.c @@ -136,7 +136,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) ******************************************************************************/ static void enable_extensions_nonsecure(bool el2_unused) { -#if IMAGE_BL32 +#ifdef IMAGE_BL32 if (is_feat_amu_supported()) { amu_enable(el2_unused); } diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index ff4ea2b90..e9438bad6 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -379,14 +379,14 @@ no_amu_save_\@: stp x26, x27, [x19, #CTX_PACDBKEY_LO] stp x28, x29, [x19, #CTX_PACGAKEY_LO] #if ENABLE_PAUTH -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* tpidr_el3 contains the address of the cpu_data structure */ per_cpu_cur percpu_data, x9, x10 /* Load APIAKey from cpu_data */ ldp x10, x11, [x9, #CPU_DATA_APIAKEY] #endif /* IMAGE_BL31 */ -#if IMAGE_BL1 +#ifdef IMAGE_BL1 /* BL1 does not use cpu_data and has dedicated storage */ adr_l x9, bl1_apiakey ldp x10, x11, [x9] @@ -645,7 +645,7 @@ func el3_exit ldp x19, x20, [x9, #CTX_CPTR_EL3] msr cptr_el3, x19 -#if ENABLE_FEAT_MPAM && IMAGE_BL31 +#if ENABLE_FEAT_MPAM && defined(IMAGE_BL31) #if ENABLE_FEAT_MPAM == 2 is_feat_mpam_present_asm x7, x8 cbz x7, no_mpam @@ -655,7 +655,7 @@ func el3_exit no_mpam: #endif -#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 +#if defined(IMAGE_BL31) && DYNAMIC_WORKAROUND_CVE_2018_3639 /* ---------------------------------------------------------- * Restore mitigation state as it was on entry to EL3 * ---------------------------------------------------------- @@ -666,7 +666,7 @@ no_mpam: 1: #endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */ -#if IMAGE_BL31 +#ifdef IMAGE_BL31 synchronize_errors #endif /* IMAGE_BL31 */ diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 44dbb4ee1..044efa37c 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -18,7 +18,6 @@ #include <common/bl_common.h> #include <common/debug.h> #include <context.h> -#include <drivers/arm/gicv3.h> #include <lib/cpus/cpu_ops.h> #include <lib/cpus/errata.h> #include <lib/el3_runtime/context_mgmt.h> @@ -60,7 +59,7 @@ static void manage_extensions_secure(cpu_context_t *ctx); */ static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) { -#if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) +#if (defined(IMAGE_BL1) || (defined(IMAGE_BL31) && (!CTX_INCLUDE_EL2_REGS))) u_register_t sctlr_elx, actlr_elx; /* @@ -115,7 +114,7 @@ static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info */ actlr_elx = read_actlr_el1(); write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); -#endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ +#endif /* (defined(IMAGE_BL1) || (defined(IMAGE_BL31) && (!CTX_INCLUDE_EL2_REGS)) */ } /* @@ -126,7 +125,7 @@ static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info */ static void setup_el2_context(cpu_context_t *ctx) { -#if CTX_INCLUDE_EL2_REGS && IMAGE_BL31 +#if CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31) el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); /* @@ -181,7 +180,7 @@ static void setup_el2_context(cpu_context_t *ctx) */ static void setup_el2_regs(void) { -#if !(CTX_INCLUDE_EL2_REGS && IMAGE_BL31) +#if !(CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) if (is_feat_hcx_supported()) { write_hcrx_el2(HCRX_EL2_INIT_VAL); } @@ -232,7 +231,7 @@ static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_in manage_extensions_secure(ctx); } -#if ENABLE_RMM && IMAGE_BL31 +#if ENABLE_RMM && defined(IMAGE_BL31) /****************************************************************************** * This function performs initializations that are specific to REALM state * and updates the cpu context specified by 'ctx'. @@ -304,7 +303,7 @@ static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_inf trbe_disable_realm(ctx); } } -#endif /* ENABLE_RMM && IMAGE_BL31 */ +#endif /* ENABLE_RMM && defined(IMAGE_BL31) */ /****************************************************************************** * This function performs initializations that are specific to NON-SECURE state @@ -597,7 +596,7 @@ static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *e scr_el3 |= SCR_TWEDEn_BIT; } -#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 +#if defined(IMAGE_BL31) && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ if (is_feat_sel2_supported()) { scr_el3 |= SCR_EEL2_BIT; @@ -647,7 +646,7 @@ static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *e write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ if (is_feat_trf_supported()) { trf_enable(ctx); @@ -725,7 +724,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) case SECURE: setup_secure_context(ctx, ep); break; -#if ENABLE_RMM && IMAGE_BL31 +#if ENABLE_RMM && defined(IMAGE_BL31) case REALM: setup_realm_context(ctx, ep); break; @@ -751,7 +750,7 @@ void __no_pauth cm_manage_extensions_el3(unsigned int my_idx) pauth_init_enable_el3(); } -#if IMAGE_BL31 +#ifdef IMAGE_BL31 if (is_feat_sve_supported()) { sve_init_el3(); } @@ -822,7 +821,7 @@ static void manage_extensions_nonsecure_per_world(void) { cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); -#if IMAGE_BL31 +#ifdef IMAGE_BL31 if (is_feat_sme_supported()) { sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); } @@ -858,7 +857,7 @@ static void manage_extensions_secure_per_world(void) { cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); -#if IMAGE_BL31 +#ifdef IMAGE_BL31 if (is_feat_sme_supported()) { if (ENABLE_SME_FOR_SWD) { @@ -904,7 +903,7 @@ static void manage_extensions_secure_per_world(void) static void manage_extensions_realm_per_world(void) { -#if ENABLE_RMM && IMAGE_BL31 +#if ENABLE_RMM && defined(IMAGE_BL31) cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); if (is_feat_sve_supported()) { @@ -943,7 +942,7 @@ static void manage_extensions_realm_per_world(void) if (is_feat_idte3_supported()) { idte3_init_cached_idregs_per_world(CPU_CONTEXT_REALM); } -#endif /* ENABLE_RMM && IMAGE_BL31 */ +#endif /* ENABLE_RMM && defined(IMAGE_BL31) */ } void cm_manage_extensions_per_world(void) @@ -955,7 +954,7 @@ void cm_manage_extensions_per_world(void) void cm_init_percpu_once_regs(void) { -#if IMAGE_BL31 +#ifdef IMAGE_BL31 if (is_feat_idte3_supported()) { idte3_init_percpu_once_regs(CPU_CONTEXT_NS); idte3_init_percpu_once_regs(CPU_CONTEXT_SECURE); @@ -971,7 +970,7 @@ void cm_init_percpu_once_regs(void) ******************************************************************************/ static void manage_extensions_nonsecure(cpu_context_t *ctx) { -#if IMAGE_BL31 +#ifdef IMAGE_BL31 /* NOTE: registers are not context switched */ if (is_feat_amu_supported()) { amu_enable(ctx); @@ -1014,7 +1013,7 @@ static void manage_extensions_nonsecure(cpu_context_t *ctx) ******************************************************************************/ static void manage_extensions_nonsecure_el2_unused(void) { -#if IMAGE_BL31 +#ifdef IMAGE_BL31 if (is_feat_spe_supported()) { spe_init_el2_unused(); } @@ -1065,7 +1064,7 @@ static void manage_extensions_nonsecure_el2_unused(void) ******************************************************************************/ static void manage_extensions_secure(cpu_context_t *ctx) { -#if IMAGE_BL31 +#ifdef IMAGE_BL31 if (is_feat_sme_supported()) { if (ENABLE_SME_FOR_SWD) { /* @@ -1267,7 +1266,7 @@ void cm_prepare_el3_exit(size_t security_state) write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); } } -#if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1 +#if !CTX_INCLUDE_EL2_REGS || defined(IMAGE_BL1) /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ cm_el1_sysregs_context_restore(security_state); #endif @@ -1291,7 +1290,7 @@ void cm_sysregs_context_restore_amu(unsigned int security_state) write_amevcntr03_el0(ctx->amevcntr03_el0); } -#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) +#if (CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) { @@ -1788,7 +1787,7 @@ void cm_el2_sysregs_context_restore(uint32_t security_state) ******************************************************************************/ void cm_prepare_el3_exit_ns(void) { -#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) +#if (CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) #if ENABLE_ASSERTIONS cpu_context_t *ctx = cm_get_context(NON_SECURE); assert(ctx != NULL); @@ -1805,14 +1804,14 @@ void cm_prepare_el3_exit_ns(void) cm_set_next_eret_context(NON_SECURE); #else cm_prepare_el3_exit(NON_SECURE); -#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ +#endif /* (CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) */ if (is_feat_amu_supported()) { cm_sysregs_context_restore_amu(NON_SECURE); } } -#if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) +#if (defined(IMAGE_BL1) || (defined(IMAGE_BL31) && (!CTX_INCLUDE_EL2_REGS))) /******************************************************************************* * The next set of six functions are used by runtime services to save and restore * EL1 context on the 'cpu_context' structure for the specified security state. @@ -2057,7 +2056,7 @@ void cm_el1_sysregs_context_save(uint32_t security_state) el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); -#if IMAGE_BL31 +#ifdef IMAGE_BL31 if (is_feat_amu_supported()) { cm_sysregs_context_save_amu(security_state); } @@ -2079,7 +2078,7 @@ void cm_el1_sysregs_context_restore(uint32_t security_state) el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); -#if IMAGE_BL31 +#ifdef IMAGE_BL31 if (is_feat_amu_supported()) { cm_sysregs_context_restore_amu(security_state); } diff --git a/lib/extensions/pauth/pauth.c b/lib/extensions/pauth/pauth.c index 0a99dcfac..03d81f0d8 100644 --- a/lib/extensions/pauth/pauth.c +++ b/lib/extensions/pauth/pauth.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2025-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,7 +33,7 @@ void pauth_init(void) write_apiakeylo_el1(key_lo); write_apiakeyhi_el1(key_hi); -#if IMAGE_BL31 +#if defined(IMAGE_BL31) /* * In the warmboot entrypoint, cpu_data may have been used before data * caching was enabled. Flush the caches so nothing stale is @@ -48,7 +48,7 @@ void pauth_init(void) #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) flush_cpu_data(apiakey); #endif -#elif IMAGE_BL1 +#elif defined(IMAGE_BL1) bl1_apiakey[0] = key_lo; bl1_apiakey[1] = key_hi; #endif diff --git a/lib/extensions/pmuv3/aarch64/pmuv3.c b/lib/extensions/pmuv3/aarch64/pmuv3.c index 4cd81e42c..cde891f91 100644 --- a/lib/extensions/pmuv3/aarch64/pmuv3.c +++ b/lib/extensions/pmuv3/aarch64/pmuv3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024, Arm Limited. All rights reserved. + * Copyright (c) 2023-2026, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,13 +37,13 @@ static u_register_t mtpmu_disable_el3(u_register_t mdcr_el3) void pmuv3_enable(cpu_context_t *ctx) { -#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) +#if (CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) u_register_t mdcr_el2_val; mdcr_el2_val = read_el2_ctx_common(get_el2_sysregs_ctx(ctx), mdcr_el2); mdcr_el2_val = init_mdcr_el2_hpmn(mdcr_el2_val); write_el2_ctx_common(get_el2_sysregs_ctx(ctx), mdcr_el2, mdcr_el2_val); -#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ +#endif /* (CTX_INCLUDE_EL2_REGS && defined(IMAGE_BL31)) */ el3_state_t *state = get_el3state_ctx(ctx); u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3); diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 8afc13b0e..d0ab2132a 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -751,6 +751,10 @@ int psci_validate_state_coordination(unsigned int cpu_idx, unsigned int end_pwrl * specified power level. */ lvl = state_info->last_at_pwrlvl; + if (lvl > PLAT_MAX_PWR_LVL) { + return PSCI_E_INVALID_PARAMS; + } + if (lvl > end_pwrlvl) { if (!psci_is_last_cpu_to_idle_at_pwrlvl(cpu_idx, lvl)) { rc = PSCI_E_DENIED; diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c index 81e53eeae..d6f809006 100644 --- a/lib/xlat_tables_v2/xlat_tables_context.c +++ b/lib/xlat_tables_v2/xlat_tables_context.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -120,7 +120,7 @@ int xlat_change_mem_attributes(uintptr_t base_va, size_t size, uint32_t attr) return xlat_change_mem_attributes_ctx(&tf_xlat_ctx, base_va, size, attr); } -#if PLAT_RO_XLAT_TABLES +#ifdef PLAT_RO_XLAT_TABLES /* Change the memory attributes of the descriptors which resolve the address * range that belongs to the translation tables themselves, which are by default * mapped as part of read-write data in the BL image's memory. diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index af32ad20f..0e8f0ac14 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -1,10 +1,11 @@ /* - * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> +#include <stdint.h> #include <string.h> #include <arch.h> @@ -23,6 +24,7 @@ #include <platform_def.h> #include <services/arm_arch_svc.h> #include <services/rmm_core_manifest.h> +#include <services/firme_svc.h> #if SPM_MM #include <services/spm_mm_partition.h> #endif @@ -1065,7 +1067,7 @@ int plat_rmmd_load_manifest(struct rmm_manifest *manifest) /* * Update encryption key associated with @mecid. */ -int plat_rmmd_mecid_key_update(uint16_t mecid, unsigned int reason) +int plat_firme_mec_refresh(uint16_t mecid, uint8_t reason) { /* * FVP does not provide an interface to change the encryption key associated @@ -1073,4 +1075,14 @@ int plat_rmmd_mecid_key_update(uint16_t mecid, unsigned int reason) */ return 0; } + +uint8_t plat_firme_get_common_mecid_width(void) +{ + + /* + * Use the PE MECID width as the system MECID width is expected to be the same for all + * system components on FVP. + */ + return (uint8_t)EXTRACT(MECIDR_EL2_MECIDWidthm1, read_mecidr_el2()); +} #endif /* ENABLE_RMM */ diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c index 8a7ddc420..d0c3a7dd6 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c +++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c @@ -4,12 +4,15 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <stdint.h> + #include <common/debug.h> #include <drivers/arm/gic600_multichip.h> #include <drivers/arm/mhu.h> #include <drivers/arm/sfcp.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/platform.h> +#include <services/firme_svc.h> #include <platform_def.h> #include <nrd_plat.h> @@ -188,15 +191,22 @@ int plat_rmmd_load_manifest(struct rmm_manifest *manifest) /* * Update encryption key associated with @mecid. */ -int plat_rmmd_mecid_key_update(uint16_t mecid, unsigned int reason) +int plat_firme_mec_refresh(uint16_t mecid, uint8_t reason) { /* * RDV3 does not support FEAT_MEC. - * This empty hook is for compilation to succeed. + * FIXME: This hook is needed to maintain backward compatibility with RMMD. Drop once we + * have more fine grained control over what services are exposed and how. */ return 0; } +uint8_t plat_firme_get_common_mecid_width(void) +{ + /* RDV3 does not support FEAT_MEC. */ + return 0U; +} + int plat_spmd_handle_group0_interrupt(uint32_t intid) { /* diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index ced1a2805..f9f10146c 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -443,7 +443,7 @@ void arm_bl31_plat_runtime_setup(void) arm_free_init_memory(); #endif -#if PLAT_RO_XLAT_TABLES +#ifdef PLAT_RO_XLAT_TABLES arm_xlat_make_tables_readonly(); #endif } diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 3c92ef268..115290ddc 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -44,7 +44,7 @@ uintptr_t arm_gicr_base_addrs[2] = { * image's translation tables are located such that the tables will have * read-only permissions. ******************************************************************************/ -#if PLAT_RO_XLAT_TABLES +#ifdef PLAT_RO_XLAT_TABLES void arm_xlat_make_tables_readonly(void) { int rc = xlat_make_tables_readonly(); diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index c5ea6b0bc..ba171015a 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -359,10 +359,18 @@ BL31_SOURCES += plat/arm/common/aarch64/execution_state_switch.c\ plat/arm/common/arm_sip_svc_validation.c \ plat/arm/common/plat_arm_sip_svc.c \ ${ARM_SVC_HANDLER_SRCS} + +ifeq ($(SMC_PCI_SUPPORT), 1) +BL31_SOURCES += plat/arm/common/arm_pci_svc.c +endif else BL32_SOURCES += plat/arm/common/arm_sip_svc.c \ plat/arm/common/plat_arm_sip_svc.c \ ${ARM_SVC_HANDLER_SRCS} + +ifeq ($(SMC_PCI_SUPPORT), 1) +BL32_SOURCES += plat/arm/common/arm_pci_svc.c +endif endif endif diff --git a/plat/arm/common/arm_pci_svc.c b/plat/arm/common/arm_pci_svc.c new file mode 100644 index 000000000..879910b28 --- /dev/null +++ b/plat/arm/common/arm_pci_svc.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2026, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include <services/pci_svc.h> + +uint32_t pci_read_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t *val) +{ + uint32_t ret = SMC_PCI_CALL_SUCCESS; + + (void)addr; + (void)off; + (void)sz; + (void)val; + + return ret; +} + +uint32_t pci_write_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t val) +{ + uint32_t ret = SMC_PCI_CALL_SUCCESS; + + (void)addr; + (void)off; + (void)sz; + (void)val; + + return ret; +} + +uint32_t pci_get_bus_for_seg(uint32_t seg, uint32_t *bus_range, uint32_t *nseg) +{ + uint32_t ret = SMC_PCI_CALL_SUCCESS; + + (void)seg; + (void)bus_range; + (void)nseg; + + return ret; +} diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index e8d15f76e..b98c7a16a 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -103,6 +103,9 @@ int arm_validate_power_state(unsigned int power_state, } #if PSCI_OS_INIT_MODE req_state->last_at_pwrlvl = state_id & ARM_LOCAL_PSTATE_MASK; + if (req_state->last_at_pwrlvl > PLAT_MAX_PWR_LVL) { + return PSCI_E_INVALID_PARAMS; + } #endif /* __PSCI_OS_INIT_MODE__ */ return PSCI_E_SUCCESS; diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c index 763f2e296..9eb516094 100644 --- a/plat/arm/common/sp_min/arm_sp_min_setup.c +++ b/plat/arm/common/sp_min/arm_sp_min_setup.c @@ -193,7 +193,7 @@ void arm_sp_min_plat_runtime_setup(void) /* Initialize the runtime console */ arm_console_runtime_init(); -#if PLAT_RO_XLAT_TABLES +#ifdef PLAT_RO_XLAT_TABLES arm_xlat_make_tables_readonly(); #endif } diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c index f804edbc4..82c944c91 100644 --- a/plat/arm/common/tsp/arm_tsp_setup.c +++ b/plat/arm/common/tsp/arm_tsp_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -128,7 +128,7 @@ void tsp_plat_arch_setup(void) setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_el1(0); -#if PLAT_RO_XLAT_TABLES +#ifdef PLAT_RO_XLAT_TABLES arm_xlat_make_tables_readonly(); #endif } diff --git a/plat/imx/imx8m/imx8m_smc_validation.c b/plat/imx/imx8m/imx8m_smc_validation.c new file mode 100644 index 000000000..5efe33250 --- /dev/null +++ b/plat/imx/imx8m/imx8m_smc_validation.c @@ -0,0 +1,42 @@ +/* + * Copyright 2026 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +#include <common/smc_validation_framework.h> + +#include <platform_def.h> + +/* + * plat_is_valid_ns_address_range() - i.MX8M override. + * + * Accept only the DRAM region as valid Non-Secure memory, excluding the + * BL32 (OP-TEE) carve-out. This prevents NS callers from passing + * pointers into OCRAM (BL31), ROM, MMIO, or secure BL32 memory + * regions through SMC arguments. + */ +bool plat_is_valid_ns_address_range(uintptr_t base, size_t size) +{ + uintptr_t end = base + size; + + /* Reject addresses outside DRAM */ + if ((base < IMX_DRAM_BASE) || + (end > ((uintptr_t)IMX_DRAM_BASE + IMX_DRAM_SIZE))) { + return false; + } + +#if defined(BL32_BASE) && defined(BL32_SIZE) + /* Reject addresses that overlap the BL32 (OP-TEE) region */ + if ((end > BL32_BASE) && + (base < (BL32_BASE + BL32_SIZE))) { + return false; + } +#endif + + return true; +} diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk index f494e47b8..4cad97697 100644 --- a/plat/imx/imx8m/imx8mm/platform.mk +++ b/plat/imx/imx8m/imx8mm/platform.mk @@ -34,6 +34,7 @@ BL31_SOURCES += common/desc_image_load.c \ plat/imx/common/imx8_helpers.S \ plat/imx/imx8m/gpc_common.c \ plat/imx/imx8m/imx_hab.c \ + plat/imx/imx8m/imx8m_smc_validation.c \ plat/imx/imx8m/imx_aipstz.c \ plat/imx/imx8m/imx_rdc.c \ plat/imx/imx8m/imx8m_csu.c \ diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk index 6a9d22e12..9cf5b05a6 100644 --- a/plat/imx/imx8m/imx8mn/platform.mk +++ b/plat/imx/imx8m/imx8mn/platform.mk @@ -29,6 +29,7 @@ BL31_SOURCES += common/desc_image_load.c \ plat/imx/common/imx8_helpers.S \ plat/imx/imx8m/gpc_common.c \ plat/imx/imx8m/imx_hab.c \ + plat/imx/imx8m/imx8m_smc_validation.c \ plat/imx/imx8m/imx_aipstz.c \ plat/imx/imx8m/imx_rdc.c \ plat/imx/imx8m/imx8m_caam.c \ diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk index 11fc01b0b..7ec417f63 100644 --- a/plat/imx/imx8m/imx8mp/platform.mk +++ b/plat/imx/imx8m/imx8mp/platform.mk @@ -31,6 +31,7 @@ BL31_SOURCES += common/desc_image_load.c \ plat/imx/common/imx8_helpers.S \ plat/imx/imx8m/gpc_common.c \ plat/imx/imx8m/imx_hab.c \ + plat/imx/imx8m/imx8m_smc_validation.c \ plat/imx/imx8m/imx_aipstz.c \ plat/imx/imx8m/imx_rdc.c \ plat/imx/imx8m/imx8m_caam.c \ diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk index 76fc07107..17437da04 100644 --- a/plat/imx/imx8m/imx8mq/platform.mk +++ b/plat/imx/imx8m/imx8mq/platform.mk @@ -30,6 +30,7 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ plat/imx/imx8m/imx8mq/imx8mq_psci.c \ plat/imx/imx8m/gpc_common.c \ plat/imx/imx8m/imx_hab.c \ + plat/imx/imx8m/imx8m_smc_validation.c \ plat/imx/imx8m/imx_aipstz.c \ plat/imx/imx8m/imx8m_caam.c \ plat/imx/imx8m/imx8m_ccm.c \ diff --git a/plat/imx/imx8m/imx_hab.c b/plat/imx/imx8m/imx_hab.c index 222046fb9..d34d495bf 100644 --- a/plat/imx/imx8m/imx_hab.c +++ b/plat/imx/imx8m/imx_hab.c @@ -5,7 +5,10 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <common/debug.h> #include <common/runtime_svc.h> +#include <common/smc_validation_framework.h> + #include <imx_sip_svc.h> #define HAB_CID_ATF U(2) /* TF-A Caller ID */ @@ -80,7 +83,8 @@ struct hab_rvt_api { size_t *bytes, hab_loader_callback_f_t loader, uint32_t srkmask, int skip_dcd); }; -struct hab_rvt_api *g_hab_rvt_api = (struct hab_rvt_api *)HAB_RVT_BASE; +static const struct hab_rvt_api *g_hab_rvt_api = + (const struct hab_rvt_api *)HAB_RVT_BASE; /******************************************************************************* * Handler for servicing HAB SMC calls @@ -102,12 +106,66 @@ int imx_hab_handler(uint32_t smc_fid, case IMX_SIP_HAB_AUTH_IMG: return (unsigned long)g_hab_rvt_api->authenticate_image(HAB_CID_ATF, x2, (void **)x3, (size_t *)x4, NULL); + case IMX_SIP_HAB_REPORT_EVENT: - return g_hab_rvt_api->report_event(HAB_FAILURE, - (uint32_t)x2, (uint8_t *)x3, (size_t *)x4); + { + uintptr_t event_buf = (uintptr_t)x3; + uintptr_t bytes_ptr = (uintptr_t)x4; + + if (smc_validate_mem_range(bytes_ptr, sizeof(size_t)) != SMC_OK) { + WARN("HAB: REPORT_EVENT bytes_ptr 0x%lx failed NS check\n", + bytes_ptr); + return (int)HAB_FAILURE; + } + + size_t max_bytes = *(size_t *)bytes_ptr; + + if (smc_validate_mem_range(event_buf, max_bytes) != SMC_OK) { + WARN("HAB: REPORT_EVENT buf 0x%lx+0x%zx failed NS check\n", + event_buf, max_bytes); + return (int)HAB_FAILURE; + } + + enum hab_status status = g_hab_rvt_api->report_event( + HAB_FAILURE, (uint32_t)x2, + (uint8_t *)event_buf, &max_bytes); + + *(size_t *)bytes_ptr = max_bytes; + + return (int)status; + } + case IMX_SIP_HAB_REPORT_STATUS: - return g_hab_rvt_api->report_status((enum hab_config *)x2, - (enum hab_state *)x3); + { + uintptr_t config_ptr = (uintptr_t)x2; + uintptr_t state_ptr = (uintptr_t)x3; + + if (smc_validate_mem_range(config_ptr, + sizeof(enum hab_config)) != SMC_OK) { + WARN("HAB: REPORT_STATUS config_ptr 0x%lx failed NS check\n", + config_ptr); + return (int)HAB_FAILURE; + } + + if (smc_validate_mem_range(state_ptr, + sizeof(enum hab_state)) != SMC_OK) { + WARN("HAB: REPORT_STATUS state_ptr 0x%lx failed NS check\n", + state_ptr); + return (int)HAB_FAILURE; + } + + enum hab_config config_local; + enum hab_state state_local; + + enum hab_status status = g_hab_rvt_api->report_status( + &config_local, &state_local); + + *(enum hab_config *)config_ptr = config_local; + *(enum hab_state *)state_ptr = state_local; + + return (int)status; + } + case IMX_SIP_HAB_FAILSAFE: g_hab_rvt_api->failsafe(); break; diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c index f5e19b9b1..3c19f6ba5 100644 --- a/plat/qemu/common/qemu_common.c +++ b/plat/qemu/common/qemu_common.c @@ -1,18 +1,21 @@ /* - * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <stdint.h> #include <string.h> #include <platform_def.h> +#include <arch.h> #include <arch_helpers.h> #include <common/bl_common.h> #include <lib/xlat_tables/xlat_tables_v2.h> #include <services/el3_spmc_ffa_memory.h> +#include <services/firme_svc.h> #if ENABLE_RMM #include <services/rmm_core_manifest.h> #endif @@ -760,7 +763,7 @@ int plat_rmmd_load_manifest(struct rmm_manifest *manifest) /* * Update encryption key associated with @mecid. */ -int plat_rmmd_mecid_key_update(uint16_t mecid, unsigned int reason) +int plat_firme_mec_refresh(uint16_t mecid, uint8_t reason) { /* * QEMU does not provide an interface to change the encryption key @@ -768,6 +771,12 @@ int plat_rmmd_mecid_key_update(uint16_t mecid, unsigned int reason) */ return 0; } + +uint8_t plat_firme_get_common_mecid_width(void) +{ + /* Safe default value for common MECID width. */ + return (uint8_t)EXTRACT(MECIDR_EL2_MECIDWidthm1, read_mecidr_el2()); +} #endif /* ENABLE_RMM */ /** diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h index 72f343eb5..14e3823d3 100644 --- a/plat/qemu/qemu/include/platform_def.h +++ b/plat/qemu/qemu/include/platform_def.h @@ -112,9 +112,11 @@ #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) #define TB_FW_CONFIG_BASE BL_RAM_BASE -#define TB_FW_CONFIG_LIMIT (TB_FW_CONFIG_BASE + PAGE_SIZE) +#define TB_FW_CONFIG_SIZE PAGE_SIZE +#define TB_FW_CONFIG_LIMIT (TB_FW_CONFIG_BASE + TB_FW_CONFIG_SIZE) #define TOS_FW_CONFIG_BASE TB_FW_CONFIG_LIMIT -#define TOS_FW_CONFIG_LIMIT (TOS_FW_CONFIG_BASE + PAGE_SIZE) +#define TOS_FW_CONFIG_SIZE PAGE_SIZE +#define TOS_FW_CONFIG_LIMIT (TOS_FW_CONFIG_BASE + TOS_FW_CONFIG_SIZE) /* * BL1 specific defines. diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h index 7dcbec9c9..9df44094a 100644 --- a/plat/rockchip/common/include/plat_private.h +++ b/plat/rockchip/common/include/plat_private.h @@ -145,6 +145,19 @@ uint32_t rockchip_get_uart_baudrate(void); uint32_t rockchip_get_uart_clock(void); void rockchip_init_scmi_server(void); + +static inline uint64_t rockchip_get_sp(void) +{ + uint64_t save_sp; + + __asm__ volatile("mov %0, sp" : "=r" (save_sp) : :); + return save_sp; +} + +static inline void rockchip_set_sp(uint64_t set_sp) +{ + __asm__ volatile("mov sp, %0" : : "r" (set_sp) :); +} #endif /* __ASSEMBLER__ */ /****************************************************************************** diff --git a/plat/rockchip/rv1126b/drivers/dmc/dmc_ddrc_rv1126b.h b/plat/rockchip/rv1126b/drivers/dmc/dmc_ddrc_rv1126b.h new file mode 100644 index 000000000..29e49b0a3 --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/dmc/dmc_ddrc_rv1126b.h @@ -0,0 +1,352 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#ifndef __PLAT_ROCKCHIP_DMC_DDRC_RV1126B_H__ +#define __PLAT_ROCKCHIP_DMC_DDRC_RV1126B_H__ + +/* DDR pctl registers define */ +#define DDRC_REGS_FREQ(n) (((n) > 0) ? (0x1000 * ((n) + 1)) : 0) + +#define DDRC_MSTR 0x0 +#define DDRC_STAT 0x4 +#define DDRC_MSTR1 0x8 +#define DDRC_MRCTRL0 0x10 +#define DDRC_MRCTRL1 0x14 +#define DDRC_MRSTAT 0x18 +#define DDRC_MRCTRL2 0x1c +#define DDRC_DERATEEN 0x20 +#define DDRC_DERATEINT 0x24 +#define DDRC_MSTR2 0x28 +#define DDRC_PWRCTL 0x30 +#define DDRC_PWRTMG 0x34 +#define DDRC_HWLPCTL 0x38 +#define DDRC_RFSHCTL0 0x50 +#define DDRC_RFSHCTL1 0x54 +#define DDRC_RFSHCTL2 0x58 +#define DDRC_RFSHCTL4 0x5c +#define DDRC_RFSHCTL3 0x60 +#define DDRC_RFSHTMG 0x64 +#define DDRC_RFSHTMG1 0x68 +#define DDRC_RFSHCTL5 0x6c +#define DDRC_ECCCFG0 0x70 +#define DDRC_ECCCFG1 0x74 +#define DDRC_ECCSTAT 0x78 +#define DDRC_ECCCTL 0x7c +#define DDRC_ECCERRCNT 0x80 +#define DDRC_ECCCADDR0 0x84 +#define DDRC_ECCCADDR1 0x88 +#define DDRC_ECCCSYN0 0x8c +#define DDRC_ECCCSYN1 0x90 +#define DDRC_ECCCSYN2 0x94 +#define DDRC_ECCBITMASK0 0x98 +#define DDRC_ECCBITMASK1 0x9c +#define DDRC_ECCBITMASK2 0xa0 +#define DDRC_ECCUADR0 0xa4 +#define DDRC_ECCUADR1 0xa8 +#define DDRC_ECCUSYNC0 0xac +#define DDRC_ECCUSYNC1 0xb0 +#define DDRC_ECCUSYNC2 0xb4 +#define DDRC_ECCPOSISONADDR0 0xb8 +#define DDRC_ECCPOSISONADDR1 0xbc +#define DDRC_INIT0 0xd0 +#define DDRC_INIT1 0xd4 +#define DDRC_INIT2 0xd8 +#define DDRC_INIT3 0xdc +#define DDRC_INIT4 0xe0 +#define DDRC_INIT5 0xe4 +#define DDRC_INIT6 0xe8 +#define DDRC_INIT7 0xec +#define DDRC_DIMMCTL 0xf0 +#define DDRC_RANKCTL 0xf4 +#define DDRC_RANKCTL1 0xf8 +#define DDRC_CHCTL 0xfc +#define DDRC_DRAMTMG0 0x100 +#define DDRC_DRAMTMG1 0x104 +#define DDRC_DRAMTMG2 0x108 +#define DDRC_DRAMTMG3 0x10c +#define DDRC_DRAMTMG4 0x110 +#define DDRC_DRAMTMG5 0x114 +#define DDRC_DRAMTMG6 0x118 +#define DDRC_DRAMTMG7 0x11c +#define DDRC_DRAMTMG8 0x120 +#define DDRC_DRAMTMG9 0x124 +#define DDRC_DRAMTMG10 0x128 +#define DDRC_DRAMTMG11 0x12c +#define DDRC_DRAMTMG12 0x130 +#define DDRC_DRAMTMG13 0x134 +#define DDRC_DRAMTMG14 0x138 +#define DDRC_DRAMTMG15 0x13c +#define DDRC_DRAMTMG16 0x140 +#define DDRC_ZQCTL0 0x180 +#define DDRC_ZQCTL1 0x184 +#define DDRC_ZQCTL2 0x188 +#define DDRC_ZQSTAT 0x18c +#define DDRC_DFITMG0 0x190 +#define DDRC_DFITMG1 0x194 +#define DDRC_DFILPCFG0 0x198 +#define DDRC_DFILPCFG1 0x19c +#define DDRC_DFIUPD0 0x1a0 +#define DDRC_DFIUPD1 0x1a4 +#define DDRC_DFIUPD2 0x1a8 +#define DDRC_DFIMISC 0x1b0 +#define DDRC_DFITMG2 0x1b4 +#define DDRC_DFITMG3 0x1b8 +#define DDRC_DFISTAT 0x1bc +#define DDRC_DBICTL 0x1c0 +#define DDRC_ADDRMAP0 0x200 +#define DDRC_ADDRMAP1 0x204 +#define DDRC_ADDRMAP2 0x208 +#define DDRC_ADDRMAP3 0x20c +#define DDRC_ADDRMAP4 0x210 +#define DDRC_ADDRMAP5 0x214 +#define DDRC_ADDRMAP6 0x218 +#define DDRC_ADDRMAP7 0x21c +#define DDRC_ADDRMAP8 0x220 +#define DDRC_ADDRMAP9 0x224 +#define DDRC_ADDRMAP10 0x228 +#define DDRC_ADDRMAP11 0x22c +#define DDRC_ODTCFG 0x240 +#define DDRC_ODTMAP 0x244 +#define DDRC_SCHED 0x250 +#define DDRC_SCHED1 0x254 +#define DDRC_PERFHPR1 0x25c +#define DDRC_PERFLPR1 0x264 +#define DDRC_PERFWR1 0x26c +#define DDRC_SCHED3 0x270 +#define DDRC_SCHED4 0x274 +#define DDRC_DQMAP0 0x280 +#define DDRC_DQMAP1 0x284 +#define DDRC_DQMAP2 0x288 +#define DDRC_DQMAP3 0x28c +#define DDRC_DQMAP4 0x290 +#define DDRC_DQMAP5 0x294 +#define DDRC_DBG0 0x300 +#define DDRC_DBG1 0x304 +#define DDRC_DBGCAM 0x308 +#define DDRC_DBGCMD 0x30c +#define DDRC_DBGSTAT 0x310 +#define DDRC_SWCTL 0x320 +#define DDRC_SWSTAT 0x324 +#define DDRC_POISONCFG 0x36c +#define DDRC_POISONSTAT 0x370 +#define DDRC_ADVECCINDEX 0x374 +#define DDRC_ADVECCSTAT 0x378 +#define DDRC_PSTAT 0x3fc +#define DDRC_PCCFG 0x400 +#define DDRC_PCFGR(n) (0x404 + (n) * 0xb0) +#define DDRC_PCFGW(n) (0x408 + (n) * 0xb0) +#define DDRC_PCTRL(n) (0x490 + (n) * 0xb0) +#define DDRC_PCFGQOS0(n) (0x494 + (n) * 0xb0) +#define DDRC_PCFGQOS1(n) (0x498 + (n) * 0xb0) +#define DDRC_PCFGWQOS0(n) (0x49c + (n) * 0xb0) +#define DDRC_PCFGWQOS1(n) (0x4a0 + (n) * 0xb0) +#define DDRC_SBRCTL 0xf24 +#define DDRC_SBRSTAT 0xf28 +#define DDRC_SBRWDATA0 0xf2c +#define DDRC_SBRWDATA1 0xf30 +#define DDRC_PDCH 0xf34 +#define DDRC_SBRSTART0 0xf38 +#define DDRC_SBRSTART1 0xf3c +#define DDRC_SBRRANGE0 0xf40 +#define DDRC_SBRRANGE1 0xf44 +#define DDRC_SBRSTART0DCH1 0xf48 +#define DDRC_SBRSTART1DCH1 0xf4c +#define DDRC_SBRRANGE0DCH1 0xf50 +#define DDRC_SBRRANGE1DCH1 0xf54 + +/* DDRC_MSTR */ +#define DDRC_FREQUENCY_MODE_MASK (0x1) +#define DDRC_FREQUENCY_MODE_SHIFT (29) +#define DDRC_FREQUENCY_MODE BIT(29) +#define DDRC_DLL_OFF_MODE BIT(15) +/* DDRC_MRSTAT */ +#define DDRC_MR_WR_BUSY BIT(0) +/* DDRC_STAT */ +#define DDRC_SELFREF_TYPE_MASK (0x3 << 4) +#define DDRC_SELFREF_TYPE_SR_NOT_AUTO (0x2 << 4) +#define DDRC_OPERATING_MODE_MASK (7) +#define DDRC_OPERATING_MODE_INIT (0x1) +#define DDRC_OPERATING_MODE_SR (3) +/* DDRC_MRCTRL0 */ +#define DDRC_MR_WR BIT(31) +#define DDRC_MR_ADDR_SHIFT (12) +#define DDRC_MR_RANK_SHIFT (4) +#define DDRC_MR_TYPE_WR (0) +#define DDRC_MR_TYPE_RD (1) +/* DDRC_MRCTRL1 */ +#define DDRC_MR_ADDRESS_SHIFT (8) +#define DDRC_MR_DATA_MASK (0xff) +/* DDRC_MRSTAT */ +#define DDRC_MR_WR_BUSY BIT(0) +/* DDRC_DERATEEN */ +#define DDRC_DERATE_MR4_PAUSE_FC BIT(13) +#define DDRC_DERATE_ENABLE (1) +/* DDRC_MSTR2 */ +#define DDRC_TARGET_FREQUENCY_SHIFT (0) +#define DDRC_TARGET_FREQUENCY_MASK (0x3) +/* DDRC_PWRCTL */ +#define DDRC_SELFREF_SW BIT(5) +#define DDRC_DFI_DRAM_CLK_DIS BIT(3) +#define DDRC_POWERDOWN_EN BIT(1) +#define DDRC_SELFREF_EN (1) +#define DDRC_POWERDOWN_MASK (0x1) +#define DDRC_POWERDOWN_SHIFT (1) +#define DDRC_SELFREF_MASK (0x1) +#define DDRC_SELFREF_SHIFT (0) +/* DDRC_RFSHCTL0 */ +#define DDRC_PER_BANK_REFRESH BIT(2) +/* DDRC_PWRTMG */ +#define DDRC_SELFREF_TO_X32_MASK (0xff) +#define DDRC_SELFREF_TO_X32_SHIFT (16) +#define DDRC_POWERDOWN_TO_X32_MASK (0x1f) +#define DDRC_POWERDOWN_TO_X32_SHIFT (0) +/* ECCCFG0 */ +#define DDRC_ECC_MODE_MASK (0x7) +#define DDRC_ECC_MODE_DIS (0) +#define DDRC_ECC_MODE_SEC (0x4) +#define DDRC_ECC_MODE_ADV (0x5) +/* ECCERRCNT */ +#define DDRC_ECC_UNCORR_ERR_CNT_MASK (0xffff) +#define DDRC_ECC_UNCORR_ERR_CNT_SHIFT (16) +#define DDRC_ECC_CORR_ERR_CNT_MASK (0xffff) +#define DDRC_ECC_CORR_ERR_CNT_SHIFT (0) +/* ECCCADDR0 */ +#define ECC_CORR_RANK_SHIFT (24) +#define ECC_CORR_RANK_MASK (0x3) +#define ECC_CORR_ROW_MASK (0x3ffff) +/* ECCCADDR1 */ +#define ECC_CORR_CID_SHIFT (28) +#define ECC_CORR_CID_MASK (0x3) +#define ECC_CORR_BG_SHIFT (24) +#define ECC_CORR_BG_MASK (0x3) +#define ECC_CORR_BANK_SHIFT (16) +#define ECC_CORR_BANK_MASK (0x7) +#define ECC_CORR_COL_MASK (0xfff) +/* ECCUADDR0 */ +#define ECC_UNCORR_RANK_SHIFT (24) +#define ECC_UNCORR_RANK_MASK (0x3) +#define ECC_UNCORR_ROW_MASK (0x3ffff) +/* ECCUADDR1 */ +#define ECC_UNCORR_CID_SHIFT (28) +#define ECC_UNCORR_CID_MASK (0x3) +#define ECC_UNCORR_BG_SHIFT (24) +#define ECC_UNCORR_BG_MASK (0x3) +#define ECC_UNCORR_BANK_SHIFT (16) +#define ECC_UNCORR_BANK_MASK (0x7) +#define ECC_UNCORR_COL_MASK (0xfff) +/* DDRC_ECCPOISONADDR0 */ +#define ECC_POISON_RANK_SHIFT (24) +#define ECC_POISON_COL_SHIFT (0) +#define ECC_POISON_RANK_MASK (1) +#define ECC_POISON_COL_MASK (0xfff) +/* DDRC_ECCPOISONADDR1 */ +#define ECC_POISON_BG_SHIFT (28) +#define ECC_POISON_BK_SHIFT (24) +#define ECC_POISON_ROW_SHIFT (0) +#define ECC_POISON_BG_MASK (0x3) +#define ECC_POISON_BK_MASK (0x7) +#define ECC_POISON_ROW_MASK (0x3ffff) +/* DDRC_INIT0 */ +#define DDRC_POST_CKE_X1024_MASK (0x3ff) +#define DDRC_POST_CKE_X1024_SHIFT (16) +/* DDRC_INIT2 */ +#define DDRC_IDLE_AFTR_RST_X32_MASK (0xff) +#define DDRC_IDLE_AFTR_RST_X32_SHIFT (8) +/* DDRC_INIT3 */ +#define DDRC_DDR34_MR0_SHIFT (16) +#define DDRC_LPDDR234_MR1_SHIFT (16) +#define DDRC_DDR34_MR1_SHIFT (0) +#define DDRC_LPDDR234_MR2_SHIFT (0) +/* DDRC_INIT4 */ +#define DDRC_DDR34_MR2_SHIFT (16) +#define DDRC_LPDDR234_MR3_SHIFT (16) +#define DDRC_DDR34_MR3_SHIFT (0) +#define DDRC_LPDDR4_MR13_SHIFT (0) +/* DDRC_INIT5 */ +#define DDRC_DEV_ZQINIT_X32_MASK (0xff) +#define DDRC_DEV_ZQINIT_X32_SHIFT (16) +#define DDRC_MAX_AUTO_INIT_X1024_MASK (0x3ff) +#define DDRC_MAX_AUTO_INIT_X1024_SHIFT (0) +/* DDRC_INIT6 */ +#define DDRC_DDR4_MR4_SHIFT (16) +#define DDRC_LPDDR4_MR11_SHIFT (16) +#define DDRC_DDR4_MR5_SHIFT (0) +#define DDRC_LPDDR4_MR12_SHIFT (0) +/* DDRC_INIT7 */ +#define DDRC_LPDDR4_MR22_SHIFT (16) +#define DDRC_DDR4_MR6_SHIFT (0) +#define DDRC_LPDDR4_MR14_SHIFT (0) +#define DDRC_MR_MASK (0xffff) +/* DDRC_RFSHCTL3 */ +#define DDRC_DIS_AUTO_REFRESH BIT(0) +/* DDRC_ZQCTL0 */ +#define DDRC_DIS_AUTO_ZQ BIT(31) +#define DDRC_DIS_SRX_ZQCL BIT(30) +#define ZQ_RESISTOR_SHARED BIT(29) +/* DDRC_DFILPCFG0 */ +#define DDRC_DFI_LP_EN_SR BIT(8) +#define DDRC_DFI_LP_EN_SR_MASK BIT(8) +#define DDRC_DFI_LP_EN_SR_SHIFT (8) +/* DDRC_DFIMISC */ +#define DDRC_DFI_INIT_START BIT(5) +#define DDRC_DFI_INIT_COMPLETE_EN BIT(0) +/* DDRC_DFISTAT */ +#define DDRC_DFI_LP_ACK BIT(1) +#define DDRC_DFI_INIT_COMPLETE (1) +/* DDRC_DBG1 */ +#define DDRC_DIS_HIF BIT(1) +/* DDRC_DBGCAM */ +#define DDRC_DBG_WR_Q_EMPTY BIT(26) +#define DDRC_DBG_RD_Q_EMPTY BIT(25) +#define DDRC_DBG_W_Q_DEPTH_MASK (0xff << 16) +#define DDRC_DBG_W_Q_DEPTH_EMPTY (0x0 << 16) +#define DDRC_DBG_LPR_Q_DEPTH_MASK (0xff << 8) +#define DDRC_DBG_LPR_Q_DEPTH_EMPTY (0x0 << 8) +#define DDRC_DBG_MASK (DDRC_DBG_WR_Q_EMPTY | DDRC_DBG_RD_Q_EMPTY | \ + DDRC_DBG_W_Q_DEPTH_MASK | DDRC_DBG_LPR_Q_DEPTH_MASK) +#define DDRC_DBG_EMPTY (DDRC_DBG_WR_Q_EMPTY | DDRC_DBG_RD_Q_EMPTY | \ + DDRC_DBG_W_Q_DEPTH_EMPTY | DDRC_DBG_LPR_Q_DEPTH_EMPTY) +/* DDRC_DBGCMD */ +#define DDRC_RANK1_REFRESH BIT(1) +#define DDRC_RANK0_REFRESH BIT(0) +/* DDRC_DBGSTAT */ +#define DDRC_RANK1_REFRESH_BUSY BIT(1) +#define DDRC_RANK0_REFRESH_BUSY BIT(0) +/* DDRC_SWCTL */ +#define DDRC_SW_DONE (0x1) +#define DDRC_SW_DONE_CLEAR (0x0) +/* DDRC_SWSTAT */ +#define DDRC_SW_DONE_ACK BIT(0) +/* DDRC_PSTAT */ +#define DDRC_WR_PORT_BUSY_0 BIT(16) +#define DDRC_RD_PORT_BUSY_0 BIT(0) +/* DDRC_PCTRLn */ +#define DDRC_PORT_EN BIT(0) +/* DDRC_ECCCFG0 */ +#define DDRC_ECC_MODE_MASK (0x7) +#define DDRC_ECC_MODE_DIS (0) +#define DDRC_ECC_MODE_SEC (0x4) +#define DDRC_ECC_MODE_ADV (0x5) +#define DDRC_ECC_MODE_SHIFT (0) +#define DDRC_ECC_TEST_MODE BIT(3) +#define DDRC_ECC_DIS_SCRUB BIT(4) +#define DDRC_ECC_TYPE_SIDEBAND (0) +#define DDRC_ECC_TYPE_INLINE (1) +#define DDRC_ECC_TYPE_MASK (1) +#define DDRC_ECC_TYPE_SHIFT (5) +/* DDRC_ECCPOISONADDR0 */ +#define DDRC_ECC_POISON_RANK_SHIFT (24) +#define DDRC_ECC_POISON_COL_SHIFT (0) +#define DDRC_ECC_POISON_RANK_MASK (1) +#define DDRC_ECC_POISON_COL_MASK (0xfff) +/* DDRC_ECCPOISONADDR1 */ +#define DDRC_ECC_POISON_BG_SHIFT (28) +#define DDRC_ECC_POISON_BK_SHIFT (24) +#define DDRC_ECC_POISON_ROW_SHIFT (0) +#define DDRC_ECC_POISON_BG_MASK (0x3) +#define DDRC_ECC_POISON_BK_MASK (0x7) +#define DDRC_ECC_POISON_ROW_MASK (0x3ffff) + +#endif /* __PLAT_ROCKCHIP_DMC_DDRC_RV1126B_H__ */ diff --git a/plat/rockchip/rv1126b/drivers/dmc/dmc_rv1126b.h b/plat/rockchip/rv1126b/drivers/dmc/dmc_rv1126b.h new file mode 100644 index 000000000..8f6fcee07 --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/dmc/dmc_rv1126b.h @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#ifndef __PLAT_ROCKCHIP_DMC_RV1126B_H__ +#define __PLAT_ROCKCHIP_DMC_RV1126B_H__ + +#include <plat_private.h> + +enum { + DLL_ON_2_ON, + DLL_ON_2_OFF, + DLL_OFF_2_ON, + DLL_OFF_2_OFF, +}; + +/* DDR PHY Register */ +#define PHY_BYTE_REG_OFS(n) ((n) * 0x180 + 0x400) +/* PHY_REG0x0 */ +#define PHY_MAX_BYTE (4) +#define PHY_DQ_WIDTH_MASK (0xf) +#define PHY_DQ_WIDTH_SHIFT (8) +/* PHY_REG0x44 */ +#define PHY_FREQ_CHOOSE_OP_T_SHIFT 30 +/* PHY_REG0x84 */ +#define PHY_TRAIN_REG_UPDATE_EN BIT(18) +/* PHY_REG0xd0 */ +#define PHY_POSTDIV_EN_SHIFT(fsp) (3 + 8 * (fsp)) +#define PHY_POSTDIV_EN_MASK (1) +#define PHY_POSTDIV_SHIFT(fsp) (4 + 8 * (fsp)) +#define PHY_POSTDIV_MASK (0x7) + +/* TOPCRU*/ +#define TOPCRU_GATE_CON06 0x818 +/* TOPCRU_GATE_CON06 */ +#define DCLK_VOP_SRC_EN BIT(12) + +/* DDRGRF Register */ +/* DDR_GRF_CON0 */ +#define GRF_CON_DFI_INIT_START(n) BITS_WITH_WMASK(n, 0x1, 1) +#define DFI_INIT_START_SEL_DDRCTL BIT_CLR_WMSK(0) +#define DFI_INIT_START_SEL_GRF BIT_SET_WMSK(0) +/* DDR_GRF_CON21 */ +#define CSYSREQ_DDRC_PMU (((0x1 << 12) << 16) | (0x1 << 12)) +#define CSYSREQ_DDRC_CTL (((0x1 << 12) << 16) | (0x0 << 12)) + +/* DDR_CRU */ +#define DDR_CRU_DDR_SOFTRST_CON00 0xa00 +/* DDR_CRU_DDR_SOFTRST_CON00 */ +#define PRESETN_DDRPHY(n) ((0x1 << (8 + 16)) | ((n) << 8)) +#define PRESETN_DDRC(n) ((0x1 << (2 + 16)) | ((n) << 2)) +#define PRESETN_DDR_BIU(n) ((0x1 << (1 + 16)) | ((n) << 1)) + +/* SUBDDR_CRU */ +#define SUBDDR_CRU_DPLL_CON(n) ((n) * 4) +#define SUBDDR_CLKSEL_CON00 0x300 +#define SUBDDR_GATE_CON00 0x800 +#define SUBDDR_SOFTRST_CON00 0xa00 +/* SUBDDR_CRU_DPLL_CON0 0x0000 */ +#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define POSTDIV1_SHIFT 12 +#define POSTDIV1_MASK 0x7 +#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) +#define FBDIV_SHIFT 0 +#define FBDIV_MASK 0xfff +#define FBDIV(n) ((0xfff << 16) | (n)) +/* SUBDDR_CRU_DPLL_CON1 0x0004 */ +#define PLLPDSEL(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define PLLPD1(n) ((0x1 << (14 + 16)) | ((n) << 14)) +#define PLLPD0(n) ((0x1 << (13 + 16)) | ((n) << 13)) +#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) +#define PLL_LOCK(n) (((n) >> 10) & 0x1) +#define POSTDIV2_SHIFT 6 +#define POSTDIV2_MASK 0x7 +#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) +#define REFDIV_SHIFT 0 +#define REFDIV_MASK 0x3f +#define REFDIV(n) ((0x3F << 16) | (n)) +/* SUBDDR_CRU_DPLL_CON3 0x000c */ +#define SSMOD_SPREAD(n) ((0x1f << (8 + 16)) | ((n) << 8)) +#define SSMOD_DIVVAL(n) ((0xf << (4 + 16)) | ((n) << 4)) +#define SSMOD_DOWNSPREAD(n) ((0x1 << (3 + 16)) | ((n) << 3)) +#define SSMOD_RESET(n) ((0x1 << (2 + 16)) | ((n) << 2)) +#define SSMOD_DIS_SSCG(n) ((0x1 << (1 + 16)) | ((n) << 1)) +#define SSMOD_BP(n) ((0x1 << (0 + 16)) | ((n) << 0)) +/* SUBDDR_CLKSEL_CON00 0x0300 */ +#define CLK_DPLL 0 +#define ACLK_SYSMEM_SRC 1 +#define CLK1X_PLL_ROOT_SEL(n) ((0x1 << (1 + 16)) | ((n) << 1)) +/* SUBDDR_SOFTRST_CON00 0x0a00 */ +#define RESETN_DDRPHY(n) ((0x1 << (13 + 16)) | ((n) << 13)) +#define RESETN_CORE_DDRC(n) ((0x1 << (7 + 16)) | ((n) << 7)) +#define ARESETN_DDRSCH(n) ((0xf << (3 + 16)) | (((n) == 0 ? 0x0 : 0xf) << 3)) +#define ARESETN_DDR_BIU(n) ((0x1 << (2 + 16)) | ((n) << 2)) + +/* PMU1 registers */ +#define PMU_DDR_PWR_SFTCON 0x110 +#define PMU_DDR_STS 0x144 +/* PMU_DDR_PWR_SFTCON */ +#define SW_DDRIO_RSTIOV_EXIT (BIT(4 + 16) | BIT(4)) +#define SW_DDRIO_RSTIOV_EN (BIT(3 + 16) | BIT(3)) +#define SW_DDRIO_RSTIOV_DIS (BIT(3 + 16)) +#define SW_DDRIO_RET_EXIT (BIT(2 + 16) | BIT(2)) +#define SW_DDRIO_RET_EN (BIT(1 + 16) | BIT(1)) +#define SW_DDRIO_RET_DIS (BIT(1 + 16)) +#define DDR_SREF_C_SFTENA (BIT(0 + 16) | BIT(0)) +#define DDR_SREF_C_SFTENA_DIS (BIT(0 + 16)) +/* PMU_DDR_STS */ +#define DDRCTL_C_SYSACTIVE BIT(3) +#define DDRCTL_C_SYSACK BIT(2) +#define DDRIO_RSTIOV BIT(1) +#define DDRIO_RETON BIT(0) + +/* PMU2 registers */ +#define PMU2_BIU_IDLE_SFTCON0 0x0110 +#define PMU2_BIU_IDLE_ACK_STS0 0x0120 +#define PMU2_BIU_IDLE_STS0 0x0128 +#define PMU2_BIU_GATEMASK_CON0 0x0130 +#define PMU2_PWR_GATE_STS 0x0230 +/* PMU2_BIU_IDLE_SFTCON0 */ +#define IDLE_REQ_DDR(set) ((set) << 0) +#define IDLE_REQ_DDR_MASK (0x1 << (0 + 16)) +#define IDLE_REQ_VEPU(set) ((set) << 4) +#define IDLE_REQ_VEPU_MASK (0x1 << (4 + 16)) +#define IDLE_REQ_VCP(set) ((set) << 5) +#define IDLE_REQ_VCP_MASK (0x1 << (5 + 16)) +#define IDLE_REQ_VDO(set) ((set) << 9) +#define IDLE_REQ_VDO_MASK (0x1 << (9 + 16)) +/* PMU2_BIU_IDLE_STS0 */ +#define IDLE_DDR (0x1 << 0) +#define IDLE_VEPU (0x1 << 4) +#define IDLE_VCP (0x1 << 5) +#define IDLE_VDO (0x1 << 9) +/* PMU2_BIU_GATEMASK_CON0 */ +#define BIT_AUTO_VDO_ENA ((0x1 << 9) | (0x1 << (9 + 16))) +#define BIT_AUTO_VCP_ENA ((0x1 << 5) | (0x1 << (5 + 16))) +#define BIT_AUTO_VEPU_ENA ((0x1 << 4) | (0x1 << (4 + 16))) +/* PMU2_PWR_GATE_STS */ +#define PD_VDO_DWN_STAT (0x1 << 1) + +/* SYSGRG */ +#define GRF_BIU_CON0 0x0030 +#define GRF_BIU_CON1 0x0034 + +/* SYS_SGRF */ +#define SYS_SGRF_AXI_SECURE_SGRF_CON0 0x0018 +/* SYS_SGRF_AXI_SECURE_SGRF_CON0 */ +#define SECURE_CTRL_AWPROT_DCF_SHIFT 3 +#define SECURE_CTRL_ARPROT_DCF_SHIFT 2 + +/* GRF_BIU_CONx */ +#define ERROR_RESPONSE 0 +#define STALL_RESPONSE 1 + +/* PMUGRF_SOC_CON0 */ +#define PMUGRF_DDRPHY_BUFFEREN_EN BITS_WITH_WMASK(0x1, 0x3, 9) +#define PMUGRF_DDRPHY_BUFFEREN_DIS BITS_WITH_WMASK(0x3, 0x3, 9) +#define PMUGRF_DDRPHY_BUFFEREN_SEL_PMU ((0x3 << (16 + 9)) | (0x2 << 9)) + +/* BUSCRU_BASE Register */ +#define BUSCRU_BUS_GATE_CON02 0x808 +/* BUSCRU_BUS_GATE_CON02 */ +#define ACLK_DCF_EN_SHIFT 1 +#define PCLK_DCF_EN_SHIFT 0 + +/* VDOCRU registers */ +#define VDO_GATE_CON00 0x800 +/* VDO_GATE_CON00 */ +#define HCLK_VOP_EN BIT(11) +#define ACLK_VOP_EN BIT(10) + +/* VOP_LITE registers */ +#define VOP_SYS_CTRL2 (0x18) +#define VOP_LINE_FLAG (0x30) +#define VOP_INTR_CLEAR (0x38) +#define VOP_INTR_STATUS (0x3c) +#define VOP_DSP_HTOTAL_HS_END (0x100) +#define VOP_DSP_VTOTAL_HS_END (0x108) +#define VOP_WIN2_CTRL0 (0x190) +#define VOP_SCAN_LINE_NUM (0x1f0) +/* VOP_SYS_CTRL2 */ +#define IMD_VOP_STANDBY_EN BIT(1) +/* VOP_INTR_CLEAR */ +#define LINE_FLAG0_INTR_CLR BIT_SET_WMSK(3) +/* VOP_INTR_STATUS */ +#define LINE_FLAG0_INTR_RAW_STS BIT(19) +#define LINE_FLAG0_INTR_STS BIT(3) +/* VOP_WIN2_CTRL0 */ +#define WIN_EN BIT(0) + +struct rv1126b_sdram_channel { + unsigned char rank; + unsigned char col; + /* 3:8bank, 2:4bank */ + unsigned char bk; + /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned char bw; + /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned char dbw; + unsigned char row_3_4; + unsigned char cs0_row; + unsigned char cs1_row; + unsigned char cs0_high16bit_row; + unsigned char cs1_high16bit_row; + unsigned int ddrconfig; +}; + +struct rv1126b_ddr_pctl_regs { + uint32_t pctl[95][2]; + /* for pctl_f1, pctl_f2, pctl_f3 */ + uint32_t pctl_f[3][28][2]; +}; + +struct rv1126b_ddr_phy_regs { + uint32_t phy[55][2]; +}; + +struct rv1126b_ddr_related_regs { + uint32_t noc_devicesize; + uint32_t ddrgrf[15][2]; + uint32_t cru_dpll_con[4]; + uint32_t subddrcru_subddrgate0; + uint32_t sgrf_soc_con2; +}; + +struct rv1126b_ddr_skew { + uint8_t ca_skew[32]; + uint8_t cs1_ca_skew[12]; + uint8_t cs2_3_ca_skew[2][12]; + uint8_t cs_dq_skew[4][4][22]; + uint8_t cs_rx_dqs_cyc[4][4]; + uint8_t cs_rx_dqs_oph[4][4]; + uint8_t cs_rx_dqs_dll[4][4]; +}; + +struct rv1126b_dmc_config { + unsigned int dramtype; +}; + +/* + * Same as struct rv1126b_fsp_param in + * u-boot-ddr/arch/arm/include/asm/arch-rockchip/sdram_rv1126b.h + */ +struct rv1126b_fsp_param { + uint32_t flag; + uint32_t freq_mhz; + + /* DPLL */ + uint32_t dpll_con[5]; + + /* dram size */ + uint32_t dq_odt; + uint32_t ca_odt; + uint32_t ds_pdds; + uint32_t vref_ca[2]; + uint32_t vref_dq[2]; + + /* phy side, [0] for pull up, [1] for pull down */ + uint32_t wr_dq_drv[2]; + uint32_t wr_ca_drv[2]; + uint32_t wr_ck_drv[2]; + uint32_t wr_cs_drv[2]; + uint32_t rd_odt[2]; + uint32_t vref_inner; + uint32_t vref_out; + uint32_t lp4_drv_pd_en; + uint32_t rx_rcv_mode; + uint32_t phy_wdqsoff_on_length; + uint32_t phy_hold_timing; + + uint32_t phy_pllpostdiv; + uint32_t phy_pllpostdiven; + uint32_t phy_al; + uint32_t phy_cl; + uint32_t phy_cwl; + uint32_t reserved[2]; + + struct rv1126b_ddr_skew skew; +}; + +#define MAX_IDX 4 +#define FSP_FLAG 0xfead0001 +/* + * Borrow share memory space to temporarily store FSP parame. + * In the stage of DDR init write FSP parame to this space. + * In the stage of trust init move FSP parame to SRAM space from share memory space. + */ +#define FSP_PARAM_BASE SHARE_MEM_BASE + +uint32_t dmc_get_dramtype(void); +__pmusramfunc void dmc_enter_lp(void); +void dmc_save(void); +__pmusramfunc void dmc_restore(void); +void dmc_init(void); + +#endif /* __PLAT_ROCKCHIP_DMC_RV1126B_H__ */ diff --git a/plat/rockchip/rv1126b/drivers/dmc/suspend.c b/plat/rockchip/rv1126b/drivers/dmc/suspend.c new file mode 100644 index 000000000..525b089eb --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/dmc/suspend.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#include <common/debug.h> + +#include <dmc_ddrc_rv1126b.h> +#include <dmc_rv1126b.h> +#include <plat_private.h> +#include <platform_def.h> +#include <pmu.h> +#include <soc.h> + +/* ddr phy registers define */ +#define PHY_REG(n) (DDRPHY_BASE + n) + +static __pmusramdata uint32_t save_lp_stat; + +static __pmusramfunc uint32_t low_power_update(uint32_t en) +{ + uint32_t lp_stat = 0; + + if (en == 1) { + mmio_clrbits_32(PHY_REG(0x84), BIT(15)); + mmio_setbits_32(DDRCTL_BASE + DDRC_PWRCTL, en & 0xf); + } else { + lp_stat = mmio_read_32(DDRCTL_BASE + DDRC_PWRCTL) & 0xf; + mmio_clrbits_32(DDRCTL_BASE + DDRC_PWRCTL, 0xf); + mmio_setbits_32(PHY_REG(0x84), BIT(15)); + } + + return lp_stat; +} + +__pmusramfunc void dmc_enter_lp(void) +{ + save_lp_stat = low_power_update(0); + + /* into self_refresh */ + mmio_write_32(PMU1_BASE + PMU_DDR_PWR_SFTCON, DDR_SREF_C_SFTENA); + while (!(mmio_read_32(PMU1_BASE + PMU_DDR_STS) & DDRCTL_C_SYSACK)) + continue; +} + +__pmusramfunc void dmc_restore(void) +{ + /* exit self_refresh */ + mmio_write_32(DDRGRF_BASE + DDRGRF_CON(21), CSYSREQ_DDRC_PMU); + mmio_write_32(PMU1_BASE + PMU_DDR_PWR_SFTCON, DDR_SREF_C_SFTENA_DIS); + while (mmio_read_32(PMU1_BASE + PMU_DDR_STS) & DDRCTL_C_SYSACK) + continue; + + low_power_update(save_lp_stat); +} diff --git a/plat/rockchip/rv1126b/drivers/pmu/plat_pmu_macros.S b/plat/rockchip/rv1126b/drivers/pmu/plat_pmu_macros.S new file mode 100644 index 000000000..a61cf80a1 --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/pmu/plat_pmu_macros.S @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#include <arch.h> +#include <asm_macros.S> +#include <platform_def.h> + +.globl clst_warmboot_data + +.macro func_rockchip_clst_warmboot +.endm + +.macro rockchip_clst_warmboot_data +.endm diff --git a/plat/rockchip/rv1126b/drivers/pmu/pm_pd_regs.c b/plat/rockchip/rv1126b/drivers/pmu/pm_pd_regs.c new file mode 100644 index 000000000..1854e4bf1 --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/pmu/pm_pd_regs.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#include <assert.h> +#include <errno.h> + +#include <arch_helpers.h> +#include <bl31/bl31.h> +#include <common/debug.h> +#include <drivers/console.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <platform.h> + +#include <plat_pm_helpers.h> +#include <plat_private.h> +#include <platform_def.h> +#include <pm_pd_regs.h> +#include <pmu.h> +#include <soc.h> + +#define WMSK_VAL 0xffff0000 + +static struct reg_region pd_aiisp_reg_rgns[] = { + /* qos */ + REG_REGION(0x08, 0x18, 4, 0x203b0000, 0) +}; + +static struct reg_region pd_vdo_reg_rgns[] = { + /* vdo_cru */ + REG_REGION(0x300, 0x300, 4, VDOCRU_BASE, WMSK_VAL), + + /* vdo_grf */ + REG_REGION(0x000, 0x014, 4, VDOGRF_BASE, WMSK_VAL), + + /* qos */ + REG_REGION(0x08, 0x18, 4, 0x20380000, 0), + REG_REGION(0x08, 0x18, 4, 0x20380100, 0), + REG_REGION(0x08, 0x18, 4, 0x20380200, 0), + REG_REGION(0x08, 0x18, 4, 0x20380300, 0), + REG_REGION(0x08, 0x18, 4, 0x20380400, 0), + + /* shaping */ + REG_REGION(0x08, 0x08, 4, 0x20380080, 0), + REG_REGION(0x08, 0x08, 4, 0x20380180, 0), + REG_REGION(0x08, 0x08, 4, 0x20380280, 0), + REG_REGION(0x08, 0x08, 4, 0x20380380, 0), + REG_REGION(0x08, 0x08, 4, 0x20380480, 0), +}; + +static struct reg_region vd_npu_reg_rgns[] = { + /* npu pvtpll*/ + REG_REGION(0x24, 0x24, 4, PVTPLL_NPU_BASE, WMSK_VAL), + REG_REGION(0x20, 0x20, 4, PVTPLL_NPU_BASE, WMSK_VAL), + + /* npu_cru */ + REG_REGION(0x300, 0x300, 4, NPUCRU_BASE, WMSK_VAL), + + /* npu_grf */ + REG_REGION(0x000, 0x004, 4, NPUGRF_BASE, WMSK_VAL), + REG_REGION(0x008, 0x00c, 4, NPUGRF_BASE, 0), + REG_REGION(0x010, 0x018, 4, NPUGRF_BASE, WMSK_VAL), + + /* qos */ + REG_REGION(0x08, 0x18, 4, 0x20340000, 0), + + /* shaping */ + REG_REGION(0x08, 0x08, 4, 0x20340080, 0), +}; + +static struct reg_region vd_core_reg_rgns[] = { + /* cpu pvtpll */ + REG_REGION(0x24, 0x24, 4, PVTPLL_CORE_BASE, WMSK_VAL), + REG_REGION(0x20, 0x20, 4, PVTPLL_CORE_BASE, WMSK_VAL), + + /* core_cru */ + REG_REGION(0x300, 0x308, 4, CORECRU_BASE, WMSK_VAL), + REG_REGION(0xd00, 0xd00, 4, CORECRU_BASE, 0), + REG_REGION(0xd04, 0xd04, 4, CORECRU_BASE, WMSK_VAL), + + /* core_grf */ + REG_REGION(0x000, 0x004, 4, COREGRF_BASE, WMSK_VAL), + + /* qos */ + REG_REGION(0x08, 0x18, 4, 0x20310000, 0), + + /* shaping */ + REG_REGION(0x08, 0x08, 4, 0x20310080, 0), +}; + +static uint32_t npu_clk_gt_save, vdo_clk_gt_save[VDO_CRU_CLKGATE_CON_CNT]; + +void pd_aiisp_save(void) +{ + rockchip_reg_rgn_save(pd_aiisp_reg_rgns, ARRAY_SIZE(pd_aiisp_reg_rgns)); +} + +void pd_aiisp_restore(void) +{ + rockchip_reg_rgn_restore(pd_aiisp_reg_rgns, ARRAY_SIZE(pd_aiisp_reg_rgns)); +} + +void pd_vdo_save(void) +{ + int i; + + for (i = 0; i < VDO_CRU_CLKGATE_CON_CNT; i++) { + vdo_clk_gt_save[i] = mmio_read_32(VDOCRU_BASE + VDO_CRU_CLKGATE_CON(i)); + mmio_write_32(VDOCRU_BASE + VDO_CRU_CLKGATE_CON(i), 0xffff0000); + } + + rockchip_reg_rgn_save(pd_vdo_reg_rgns, ARRAY_SIZE(pd_vdo_reg_rgns)); +} + +void pd_vdo_restore(void) +{ + int i; + + rockchip_reg_rgn_restore(pd_vdo_reg_rgns, ARRAY_SIZE(pd_vdo_reg_rgns)); + + for (i = 0; i < VDO_CRU_CLKGATE_CON_CNT; i++) + mmio_write_32(VDOCRU_BASE + VDO_CRU_CLKGATE_CON(i), + WITH_16BITS_WMSK(vdo_clk_gt_save[i])); +} + +void vd_npu_save(void) +{ + npu_clk_gt_save = mmio_read_32(NPUCRU_BASE + NPU_CRU_CLKGATE_CON0); + + mmio_write_32(NPUCRU_BASE + NPU_CRU_CLKGATE_CON0, 0xffff0000); + + rockchip_reg_rgn_save(vd_npu_reg_rgns, ARRAY_SIZE(vd_npu_reg_rgns)); +} + +void vd_npu_restore(void) +{ + rockchip_reg_rgn_restore(vd_npu_reg_rgns, ARRAY_SIZE(vd_npu_reg_rgns)); + + mmio_write_32(NPUCRU_BASE + NPU_CRU_CLKGATE_CON0, WITH_16BITS_WMSK(npu_clk_gt_save)); +} + +void vd_core_save(void) +{ + rockchip_reg_rgn_save(vd_core_reg_rgns, ARRAY_SIZE(vd_core_reg_rgns)); +} + +void vd_core_restore(void) +{ + /* slow mode */ + mmio_write_32(TOPCRU_BASE + 0x280, 0x003f0000); + + rockchip_reg_rgn_restore(vd_core_reg_rgns, ARRAY_SIZE(vd_core_reg_rgns)); + + /* switch to pll */ + mmio_write_32(TOPCRU_BASE + 0x280, 0x003f0015); +} + +void pm_reg_rgns_init(void) +{ + rockchip_alloc_region_mem(pd_aiisp_reg_rgns, ARRAY_SIZE(pd_aiisp_reg_rgns)); + rockchip_alloc_region_mem(pd_vdo_reg_rgns, ARRAY_SIZE(pd_vdo_reg_rgns)); + rockchip_alloc_region_mem(vd_npu_reg_rgns, ARRAY_SIZE(vd_npu_reg_rgns)); + rockchip_alloc_region_mem(vd_core_reg_rgns, ARRAY_SIZE(vd_core_reg_rgns)); +} diff --git a/plat/rockchip/rv1126b/drivers/pmu/pm_pd_regs.h b/plat/rockchip/rv1126b/drivers/pmu/pm_pd_regs.h new file mode 100644 index 000000000..1e56024da --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/pmu/pm_pd_regs.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#ifndef PM_PD_REGS_H +#define PM_PD_REGS_H + +#include <stdint.h> + +void pd_aiisp_save(void); +void pd_aiisp_restore(void); +void pd_vdo_save(void); +void pd_vdo_restore(void); +void vd_npu_save(void); +void vd_npu_restore(void); +void vd_core_save(void); +void vd_core_restore(void); + +void pm_reg_rgns_init(void); + +#endif diff --git a/plat/rockchip/rv1126b/drivers/pmu/pmu.c b/plat/rockchip/rv1126b/drivers/pmu/pmu.c new file mode 100644 index 000000000..1de73cb7c --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/pmu/pmu.c @@ -0,0 +1,963 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#include <assert.h> +#include <errno.h> + +#include <arch_helpers.h> +#include <bl31/bl31.h> +#include <common/debug.h> +#include <drivers/console.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <plat/common/platform.h> + +#include <cpus_on_fixed_addr.h> +#include <dmc_rv1126b.h> +#include <plat_pm_helpers.h> +#include <plat_private.h> +#include <platform_def.h> +#include <pm_pd_regs.h> +#include <pmu.h> +#include <secure.h> +#include <soc.h> + +static struct psram_data_t *psram_sleep_cfg = + (struct psram_data_t *)&sys_sleep_flag_sram; + +struct rv1126b_sleep_ddr_data { + uint32_t cru_mode_con, secure_cru_mode; + uint32_t gpio0a_iomux_l, gpio0a_iomux_h, gpio0b_iomux_l, gpio0b_iomux_h, + gpio0c_iomux_l, gpio0c_iomux_h, gpio0d_iomux_l; + uint32_t gpio0_ddr_l, gpio0_ddr_h, gpio0_dr_l, gpio0_dr_h; + uint32_t gpio0a_pull, gpio0b_pull, gpio0c_pull, gpio0d_pull; + uint32_t gpio0_dbclk_div_con; + uint32_t pmu2_pwrgt_sft_con0; + uint32_t pmugrf_soc_con0, pmugrf_soc_con1, pmugrf_soc_con4, pmugrf_soc_con5, + pmugrf_soc_con6, pmugrf_soc_con7; + uint32_t pmu0cru_sel_con1; + uint32_t pmu_pd_st, bus_idle_st; + uint32_t sys_sgrf_con; + uint32_t sleep_clk_freq_khz, sleep_pin_en_msk, sleep_pin_act_low_msk; + uint32_t ddrgrf_con21; +}; + +static struct rv1126b_sleep_ddr_data ddr_data; + +struct rv1126b_sleep_pmusram_data { + uint32_t idle_msk[2]; +}; + +static __pmusramdata struct rv1126b_sleep_pmusram_data pmusram_data; + +void rockchip_plat_mmu_el3(void) +{ +} + +static int check_cpu_wfie(uint32_t cpu) +{ + uint32_t loop = 0; + uint32_t msk = 0x11 << cpu; + + while ((mmio_read_32(COREGRF_BASE + CPUGRF_STATUS(0)) & msk) == 0 && + loop < WFEI_CHECK_LOOP) { + udelay(1); + loop++; + } + + if (loop >= WFEI_CHECK_LOOP) { + WARN("%s: error, cpu%d (0x%x)!\n", __func__, cpu, + mmio_read_32(COREGRF_BASE + CPUGRF_STATUS(0))); + return -EINVAL; + } + + return 0; +} + +static inline uint32_t cpu_power_domain_st(uint32_t cpu) +{ + return !!(mmio_read_32(PMU_BASE + PMU2_CLUSTER_PWR_ST) & + BIT(cpu + 8)); +} + +static int cpu_power_domain_ctr(uint32_t cpu, uint32_t pd_state) +{ + uint32_t loop = 0; + int ret = 0; + + mmio_write_32(PMU_BASE + PMU2_CPU_PWR_SFTCON(cpu), + BITS_WITH_WMASK(pd_state, 0x1, 0)); + + dsb(); + while ((cpu_power_domain_st(cpu) != pd_state) && (loop < PD_CTR_LOOP)) { + udelay(1); + loop++; + } + + if (cpu_power_domain_st(cpu) != pd_state) { + WARN("%s: %d, %d, error!\n", __func__, cpu, pd_state); + ret = -EINVAL; + } + + return ret; +} + +static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) +{ + uint32_t val; + + if (mmio_read_32(PMU_BASE + PMU2_CPU_PWR_SFTCON(cpu_id)) & BIT(0)) + return core_pwr_pd; + + val = mmio_read_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id)); + if ((val & BIT(pmu_cpu_pm_en)) != 0) { + if ((val & BIT(core_pwr_wfi_int)) != 0) + return core_pwr_wfi_int; + else if ((val & BIT(pmu_cpu_pm_sft_wakeup_en)) != 0) + return core_pwr_wfi_reset; + else + return core_pwr_wfi; + } else { + return -1; + } +} + +static int cpus_power_domain_on(uint32_t cpu_id) +{ + uint32_t cfg_info; + /* + * There are two ways to powering on or off on core. + * 1) Control it power domain into on or off in PMU_PWRDN_CON reg + * 2) Enable the core power manage in PMU_CORE_PM_CON reg, + * then, if the core enter into wfi, it power domain will be + * powered off automatically. + */ + + cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id); + + if (cfg_info == core_pwr_pd) { + /* disable core_pm cfg */ + mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), + BITS_WITH_WMASK(0, 0xf, 0)); + /* if the cores have be on, power off it firstly */ + if (cpu_power_domain_st(cpu_id) == pmu_pd_on) + cpu_power_domain_ctr(cpu_id, pmu_pd_off); + + cpu_power_domain_ctr(cpu_id, pmu_pd_on); + } else { + if (cpu_power_domain_st(cpu_id) == pmu_pd_on) { + WARN("%s: cpu%d is not in off,!\n", __func__, cpu_id); + return -EINVAL; + } + + mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), + BITS_WITH_WMASK(1, 0x1, pmu_cpu_pm_sft_wakeup_en)); + dsb(); + } + + return 0; +} + +static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) +{ + uint32_t core_pm_value; + + if (cpu_power_domain_st(cpu_id) == pmu_pd_off) + return 0; + + if (pd_cfg == core_pwr_pd) { + if (check_cpu_wfie(cpu_id) != 0) + return -EINVAL; + + /* disable core_pm cfg */ + mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), + BITS_WITH_WMASK(0, 0xf, 0)); + + cpu_power_domain_ctr(cpu_id, pmu_pd_off); + } else { + core_pm_value = BIT(pmu_cpu_pm_en) | BIT(pmu_cpu_pm_dis_int); + if (pd_cfg == core_pwr_wfi_int) + core_pm_value |= BIT(pmu_cpu_pm_int_wakeup_en); + else if (pd_cfg == core_pwr_wfi_reset) + core_pm_value |= BIT(pmu_cpu_pm_sft_wakeup_en); + + mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), + BITS_WITH_WMASK(core_pm_value, 0xf, 0)); + dsb(); + } + + return 0; +} + +int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint) +{ + uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); + + assert(cpu_id < PLATFORM_CORE_COUNT); + assert(cpuson_flags[cpu_id] == 0); + cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; + cpuson_entry_point[cpu_id] = entrypoint; + dsb(); + + cpus_power_domain_on(cpu_id); + + return PSCI_E_SUCCESS; +} + +int rockchip_soc_cores_pwr_dm_off(void) +{ + uint32_t cpu_id = plat_my_core_pos(); + + cpus_power_domain_off(cpu_id, core_pwr_wfi); + + return PSCI_E_SUCCESS; +} + +int rockchip_soc_cores_pwr_dm_on_finish(void) +{ + uint32_t cpu_id = plat_my_core_pos(); + + mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), + BITS_WITH_WMASK(0, 0xf, 0)); + + return PSCI_E_SUCCESS; +} + +int rockchip_soc_cores_pwr_dm_suspend(void) +{ + uint32_t cpu_id = plat_my_core_pos(); + + assert(cpu_id < PLATFORM_CORE_COUNT); + assert(cpuson_flags[cpu_id] == 0); + cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; + cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint(); + dsb(); + + cpus_power_domain_off(cpu_id, core_pwr_wfi_int); + + return PSCI_E_SUCCESS; +} + +int rockchip_soc_cores_pwr_dm_resume(void) +{ + uint32_t cpu_id = plat_my_core_pos(); + + /* Disable core_pm */ + mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), + BITS_WITH_WMASK(0, 0xf, 0)); + + return PSCI_E_SUCCESS; +} + +void nonboot_cpus_off(void) +{ + uint32_t boot_cpu, cpu; + + boot_cpu = plat_my_core_pos(); + + /* turn off noboot cpus */ + for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { + if (cpu == boot_cpu) + continue; + + cpus_power_domain_off(cpu, core_pwr_pd); + } +} + +__pmusramfunc void pmusram_pmu_bus_idle_req_msk(uint32_t msk, uint32_t state) +{ + if (state == pmu_bus_idle) + state = msk; + else + state = 0x0; + + mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_SFTCON, + BITS_WITH_WMASK(state, msk, 0)); + + while (pmu_bus_idle_st_msk(msk) != state || + pmu_bus_idle_ack_msk(msk) != state) + ; +} + +static __pmusramfunc void ddr_resume(void) +{ + /* switch to pll */ + mmio_write_32(TOPCRU_BASE + 0x280, 0x003f0015); + + /* hptimer 32k disable */ + mmio_write_32(PMUSGRF_BASE + PMUSGRF_SOC_CON(0), + BITS_WITH_WMASK(0, 0x1, 8)); + + /* hptimer is 24M here */ + write_cntfrq_el0(24000000); + + pmusram_pmu_bus_idle_req_msk(pmusram_data.idle_msk[1], pmu_bus_active); + pmusram_pmu_bus_idle_req_msk(pmusram_data.idle_msk[0], pmu_bus_active); + + dmc_restore(); +} + +static uint32_t clk_save[CRU_CLKGATE_CON_CNT + PERI_CRU_CLKGATE_CON_CNT + + BUS_CRU_CLKGATE_CON_CNT + BUS_SCRU_CLKGATE_CON_CNT + + PMU0CRU_CLKGATE_CON_CNT + PMU1CRU_CLKGATE_CON_CNT + + CORE_CRU_CLKGATE_CON_CNT + VI_CRU_CLKGATE_CON_CNT + + VEPU_CRU_CLKGATE_CON_CNT + VCP_CRU_CLKGATE_CON_CNT + + PMUSCRU_CLKGATE_CON_CNT]; + +static const uint16_t top_clk_ungt_msk[CRU_CLKGATE_CON_CNT] = { + 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, + 0xfffc, 0xffff, 0xffff, 0xffff, /* Don't open wdt clk (cru_gt8[0:1]) */ + 0xffff, 0xffff, 0xffff, 0xff87, /* Don't open mipi clk (cru_gt15[0:1]) */ +}; + +void clk_gate_con_disable(void) +{ + int i; + + for (i = 0; i < CRU_CLKGATE_CON_CNT; i++) { + mmio_write_32(TOPCRU_BASE + CRU_CLKGATE_CON(i), + (uint32_t)top_clk_ungt_msk[i] << 16); + } + + for (i = 0; i < PERI_CRU_CLKGATE_CON_CNT; i++) + mmio_write_32(PERICRU_BASE + PERI_CRU_CLKGATE_CON(i), 0xffff0000); + + for (i = 0; i < BUS_CRU_CLKGATE_CON_CNT; i++) + mmio_write_32(BUSCRU_BASE + BUS_CRU_CLKGATE_CON(i), 0xffff0000); + + for (i = 0; i < BUS_SCRU_CLKGATE_CON_CNT; i++) + mmio_write_32(BUSCRU_BASE + BUS_SCRU_CLKGATE_CON(i), 0xffff0000); + + for (i = 0; i < PMU0CRU_CLKGATE_CON_CNT; i++) + mmio_write_32(PMU0CRU_BASE + PMU0CRU_CLKGATE_CON(i), 0xffff0000); + + for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++) + mmio_write_32(PMU1CRU_BASE + PMU1CRU_CLKGATE_CON(i), 0xffff0000); + + for (i = 0; i < CORE_CRU_CLKGATE_CON_CNT; i++) + mmio_write_32(CORECRU_BASE + CORE_CRU_CLKGATE_CON(i), 0xffff0000); + + for (i = 0; i < VI_CRU_CLKGATE_CON_CNT; i++) + mmio_write_32(VICRU_BASE + VI_CRU_CLKGATE_CON(i), 0xffff0000); + + for (i = 0; i < VEPU_CRU_CLKGATE_CON_CNT; i++) + mmio_write_32(VEPUCRU_BASE + VEPU_CRU_CLKGATE_CON(i), 0xffff0000); + + for (i = 0; i < VCP_CRU_CLKGATE_CON_CNT; i++) + mmio_write_32(VCPCRU_BASE + VCP_CRU_CLKGATE_CON(i), 0xffff0000); + + mmio_write_32(PMUSCRU_BASE + PMUSCRU_CLKGATE_CON0, 0xffff0000); +} + +void clk_gate_con_save(void) +{ + int i, j = 0; + + for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) + clk_save[j] = mmio_read_32(TOPCRU_BASE + CRU_CLKGATE_CON(i)); + + for (i = 0; i < PERI_CRU_CLKGATE_CON_CNT; i++, j++) + clk_save[j] = mmio_read_32(PERICRU_BASE + PERI_CRU_CLKGATE_CON(i)); + + for (i = 0; i < BUS_CRU_CLKGATE_CON_CNT; i++, j++) + clk_save[j] = mmio_read_32(BUSCRU_BASE + BUS_CRU_CLKGATE_CON(i)); + + for (i = 0; i < BUS_SCRU_CLKGATE_CON_CNT; i++, j++) + clk_save[j] = mmio_read_32(BUSCRU_BASE + BUS_SCRU_CLKGATE_CON(i)); + + for (i = 0; i < PMU0CRU_CLKGATE_CON_CNT; i++, j++) + clk_save[j] = mmio_read_32(PMU0CRU_BASE + PMU0CRU_CLKGATE_CON(i)); + + for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) + clk_save[j] = mmio_read_32(PMU1CRU_BASE + PMU1CRU_CLKGATE_CON(i)); + + for (i = 0; i < CORE_CRU_CLKGATE_CON_CNT; i++, j++) + clk_save[j] = mmio_read_32(CORECRU_BASE + CORE_CRU_CLKGATE_CON(i)); + + for (i = 0; i < VI_CRU_CLKGATE_CON_CNT; i++, j++) + clk_save[j] = mmio_read_32(VICRU_BASE + VI_CRU_CLKGATE_CON(i)); + + for (i = 0; i < VEPU_CRU_CLKGATE_CON_CNT; i++, j++) + clk_save[j] = mmio_read_32(VEPUCRU_BASE + VEPU_CRU_CLKGATE_CON(i)); + + for (i = 0; i < VCP_CRU_CLKGATE_CON_CNT; i++, j++) + clk_save[j] = mmio_read_32(VCPCRU_BASE + VCP_CRU_CLKGATE_CON(i)); + + clk_save[j] = mmio_read_32(PMUSCRU_BASE + PMUSCRU_CLKGATE_CON0); +} + +void clk_gate_con_restore(void) +{ + int i, j = 0; + + for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) + mmio_write_32(TOPCRU_BASE + CRU_CLKGATE_CON(i), + WITH_16BITS_WMSK(clk_save[j])); + + for (i = 0; i < PERI_CRU_CLKGATE_CON_CNT; i++, j++) + mmio_write_32(PERICRU_BASE + PERI_CRU_CLKGATE_CON(i), + WITH_16BITS_WMSK(clk_save[j])); + + for (i = 0; i < BUS_CRU_CLKGATE_CON_CNT; i++, j++) + mmio_write_32(BUSCRU_BASE + BUS_CRU_CLKGATE_CON(i), + WITH_16BITS_WMSK(clk_save[j])); + + for (i = 0; i < BUS_SCRU_CLKGATE_CON_CNT; i++, j++) + mmio_write_32(BUSCRU_BASE + BUS_SCRU_CLKGATE_CON(i), + WITH_16BITS_WMSK(clk_save[j])); + + for (i = 0; i < PMU0CRU_CLKGATE_CON_CNT; i++, j++) + mmio_write_32(PMU0CRU_BASE + PMU0CRU_CLKGATE_CON(i), + WITH_16BITS_WMSK(clk_save[j])); + + for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) + mmio_write_32(PMU1CRU_BASE + PMU1CRU_CLKGATE_CON(i), + WITH_16BITS_WMSK(clk_save[j])); + + for (i = 0; i < CORE_CRU_CLKGATE_CON_CNT; i++, j++) + mmio_write_32(CORECRU_BASE + CORE_CRU_CLKGATE_CON(i), + WITH_16BITS_WMSK(clk_save[j])); + + for (i = 0; i < VI_CRU_CLKGATE_CON_CNT; i++, j++) + mmio_write_32(VICRU_BASE + VI_CRU_CLKGATE_CON(i), + WITH_16BITS_WMSK(clk_save[j])); + + for (i = 0; i < VEPU_CRU_CLKGATE_CON_CNT; i++, j++) + mmio_write_32(VEPUCRU_BASE + VEPU_CRU_CLKGATE_CON(i), + WITH_16BITS_WMSK(clk_save[j])); + + for (i = 0; i < VCP_CRU_CLKGATE_CON_CNT; i++, j++) + mmio_write_32(VCPCRU_BASE + VCP_CRU_CLKGATE_CON(i), + WITH_16BITS_WMSK(clk_save[j])); + + mmio_write_32(PMUSCRU_BASE + PMUSCRU_CLKGATE_CON0, WITH_16BITS_WMSK(clk_save[j])); +} + +void pmu_bus_idle_req(uint32_t bus, uint32_t state) +{ + uint32_t wait_cnt = 0; + + mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_SFTCON, + BITS_WITH_WMASK(state, 0x1, bus)); + + while (pmu_bus_idle_st(bus) != state || + pmu_bus_idle_ack(bus) != state) { + if (++wait_cnt > BUS_IDLE_LOOP) + break; + udelay(1); + } + + if (wait_cnt > BUS_IDLE_LOOP) + WARN("%s: can't wait state %d for bus %d (0x%x)\n", + __func__, state, bus, + mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST)); +} + +static inline uint32_t pmu_power_domain_st(uint32_t pd) +{ + return mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST) & BIT(pd) ? + pmu_pd_off : + pmu_pd_on; +} + +int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) +{ + uint32_t loop = 0; + int ret = 0; + + mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON, + BITS_WITH_WMASK(pd_state, 0x1, pd)); + dsb(); + + while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { + udelay(1); + loop++; + } + + if (pmu_power_domain_st(pd) != pd_state) { + WARN("%s: %d, %d, (0x%x) error!\n", __func__, pd, pd_state, + mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST)); + ret = -EINVAL; + } + + return ret; +} + +static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) +{ + uint32_t state; + + if (pmu_power_domain_st(pd_id) == pd_state) + goto out; + + if (pd_state == pmu_pd_on) + pmu_power_domain_ctr(pd_id, pd_state); + + state = (pd_state == pmu_pd_off) ? pmu_bus_idle : pmu_bus_active; + + switch (pd_id) { + case pmu_pd_npu: + pmu_bus_idle_req(pmu_bus_id_npu, state); + break; + case pmu_pd_vdo: + pmu_bus_idle_req(pmu_bus_id_vdo, state); + break; + case pmu_pd_aiisp: + pmu_bus_idle_req(pmu_bus_id_aisp, state); + break; + default: + break; + } + + if (pd_state == pmu_pd_off) + pmu_power_domain_ctr(pd_id, pd_state); + +out: + return 0; +} + +static void pmu_power_domains_suspend(void) +{ + ddr_data.pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST); + ddr_data.bus_idle_st = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST); + ddr_data.pmu2_pwrgt_sft_con0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_SFTCON); + + if ((ddr_data.pmu_pd_st & BIT(pmu_pd_aiisp)) == 0) { + pd_aiisp_save(); + pmu_set_power_domain(pmu_pd_aiisp, pmu_pd_off); + } + + if ((ddr_data.pmu_pd_st & BIT(pmu_pd_vdo)) == 0) { + pd_vdo_save(); + pmu_set_power_domain(pmu_pd_vdo, pmu_pd_off); + } + + if ((ddr_data.pmu_pd_st & BIT(pmu_pd_npu)) == 0) { + vd_npu_save(); + pmu_set_power_domain(pmu_pd_npu, pmu_pd_off); + } +} + +static void pmu_power_domains_resume(void) +{ + int i; + + for (i = 0; i < pmu_pd_id_max; i++) + pmu_set_power_domain(i, !!(ddr_data.pmu_pd_st & BIT(i))); + + for (i = 0; i < pmu_bus_id_max; i++) + pmu_bus_idle_req(i, !!(ddr_data.bus_idle_st & BIT(i))); + + if ((ddr_data.pmu_pd_st & BIT(pmu_pd_aiisp)) == 0) + pd_aiisp_restore(); + + if ((ddr_data.pmu_pd_st & BIT(pmu_pd_vdo)) == 0) + pd_vdo_restore(); + + if ((ddr_data.pmu_pd_st & BIT(pmu_pd_npu)) == 0) + vd_npu_restore(); +} + +static void ddr_sleep_config(void) +{ + ddr_data.ddrgrf_con21 = mmio_read_32(DDRGRF_BASE + DDRGRF_CON(21)); + + /* [7:4]-csysreq_aclk_pmu enable */ + mmio_write_32(DDRGRF_BASE + DDRGRF_CON(21), BITS_WITH_WMASK(0xf, 0xf, 4)); + /* [12 ]-csysreq_ddrc_pmu enable */ + mmio_write_32(DDRGRF_BASE + DDRGRF_CON(21), BITS_WITH_WMASK(0x1, 0x1, 12)); + + mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(0), BITS_WITH_WMASK(0x0, 0x1, 9)); +} + +static void ddr_sleep_config_restore(void) +{ + mmio_write_32(DDRGRF_BASE + DDRGRF_CON(21), WITH_16BITS_WMSK(ddr_data.ddrgrf_con21)); +} + +static void pmu_sleep_config(void) +{ + uint32_t clk_freq_khz = 24000; + uint32_t pmu1_wkup_int_con = 0; + uint32_t pmu0_pwr_con, pmu1_pwr_con; + uint32_t pmu1_pll_con, pmu1_cru_con[2], pmu1_ddr_ch_pwr_con, pmu1_ddr_axi_pwr_con; + uint32_t pmu2_scu_con, pmu2_scu_sftcon, pmu2_cpu_auto_con; + uint32_t pmu2_bus_idle_con, pmu2_pwr_gt_con; + + pmu1_wkup_int_con = BIT(pmu_wkup_cpu0_int) | + BIT(pmu_wkup_gpio0_int) | + 0; + + if (mmio_read_32(PMU_BASE + PMU1_WAKEUP_TIMEOUT) != 0) + pmu1_wkup_int_con |= BIT(pmu_wkup_timeout); + + pmu0_pwr_con = 0; + + pmu1_pwr_con = + BIT(pmu_powermode_en) | + /* BIT(pmu_scu0_byp) | */ + /* BIT(pmu_scu1_byp) | */ + /* BIT(pmu_bus_byp) | */ + /* BIT(pmu_ddr_byp) | */ + /* BIT(pmu_pwrgt_byp) | */ + /* BIT(pmu_cru_byp) | */ + BIT(pmu_pdpmu1_byp) | + /* BIT(pmu_wfi_byp) | */ + BIT(pmu_slp_cnt_en) | + /* BIT(pmu_wkup_pmu_sft_en) | */ + 0; + + pmu1_ddr_ch_pwr_con = + /* BIT(pmu_ddr_sref_c_en) | */ + /* BIT(pmu_ddr_ioret_en) | */ + /* BIT(pmu_ddr_ioret_exit_en) | */ + /* BIT(pmu_ddr_rstiov_en) | */ + /* BIT(pmu_ddr_rstiov_exit_en) | */ + BIT(pmu_ddrctl_c_auto_gating_en) | + BIT(pmu_ddrphy_auto_gating_en) | + 0; + + pmu1_ddr_axi_pwr_con = + /* BIT(pmu_ddr_sref_a_ch0_en) | */ + /* BIT(pmu_ddr_sref_a_ch1_en) | */ + /* BIT(pmu_ddr_sref_a_ch2_en) | */ + /* BIT(pmu_ddr_sref_a_ch3_en) | */ + 0; + + pmu1_cru_con[0] = + BIT(pmu_alive_osc_mode_en) | + /* BIT(pmu_power_off_en) | */ + /* BIT(pmu_pwm_switch_en) | */ + /* BIT(pmu_pwm_gpio_ioe_en) | */ + /* BIT(pmu_pwm_switch_io) | */ + /* BIT(pmu_pwm_clkgt_en) | */ + 0; + + pmu1_cru_con[1] = + /* BIT(pmu_peri_clksrc_gt_en) | */ + BIT(pmu_vepu_clksrc_gt_en) | + BIT(pmu_vcp_clksrc_gt_en) | + BIT(pmu_vi_clksrc_gt_en) | + BIT(pmu_npu_clksrc_gt_en) | + BIT(pmu_vdo_clksrc_gt_en) | + BIT(pmu_aisp_clksrc_gt_en) | + BIT(pmu_core_clksrc_gt_en) | + BIT(pmu_ddr_clksrc_gt_en) | + /* BIT(pmu_bus_clksrc_gt_en) | */ + 0; + + pmu1_pll_con = + BIT(pmu_gpll_pd_en) | + BIT(pmu_dpll_pd_en) | + BIT(pmu_cpll_pd_en) | + BIT(pmu_ppll_pd_en) | + 0; + + pmu2_scu_con = + BIT(pmu_l2_flush_en) | + BIT(pmu_l2_ilde_en) | + BIT(pmu_scu_pd_en) | + BIT(pmu_scu_pwroff_en) | + BIT(pmu_clst_cpu_pd_en) | + BIT(pmu_clst_clksrc_gt_en) | + 0; + + pmu2_scu_sftcon = + BIT(pmu_scu_vol_gate) | + BIT(pmu_scu_dwn_ack_sel) | + 0; + + pmu2_cpu_auto_con = + BIT(pmu_cpu_pm_int_wakeup_en) | + BIT(pmu_cpu_cluster_wakeup_en) | + 0; + + pmu2_bus_idle_con = + /* BIT(pmu_bus_id_vepu) | */ + /* BIT(pmu_bus_id_vi) | */ + BIT(pmu_bus_id_vcp) | + BIT(pmu_bus_id_cru) | + /* BIT(pmu_bus_id_peri) | */ + BIT(pmu_bus_id_bus) | + /* BIT(pmu_bus_id_cfgddr) | */ + /* BIT(pmu_bus_id_subddr) | */ + /* BIT(pmu_bus_id_ddr) | */ + 0; + + pmu2_pwr_gt_con = 0; + + /* pmu count */ + mmio_write_32(PMU_BASE + PMU1_OSC_STABLE_CNT, clk_freq_khz * 4); + mmio_write_32(PMU_BASE + PMU1_PMIC_STABLE_CNT, clk_freq_khz * 6); + mmio_write_32(PMU_BASE + PMU1_SLEEP_CNT, clk_freq_khz * 15); + + /* Pmu's clk has switched to 24M back When pmu FSM counts + * the follow counters, so we should use 24M to calculate + * these counters. + */ + mmio_write_32(PMU_BASE + PMU1_WAKEUP_RST_CLR_CNT, 0); + mmio_write_32(PMU_BASE + PMU1_PLL_LOCK_CNT, 1200); + mmio_write_32(PMU_BASE + PMU1_PWM_SWITCH_CNT, 24000 * 2); + + mmio_write_32(PMU_BASE + PMU2_SCU_STABLE_CNT, 0); + mmio_write_32(PMU_BASE + PMU2_SCU_PWRUP_CNT, 0); + mmio_write_32(PMU_BASE + PMU2_SCU_PWRDN_CNT, 0); + + /* bus / pd */ + mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON, WITH_16BITS_WMSK(pmu2_bus_idle_con)); + mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON, WITH_16BITS_WMSK(pmu2_pwr_gt_con)); + + /* clust idle */ + mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, 0x000f000f); + mmio_write_32(PMU_BASE + PMU2_SCU_PWR_CON, WITH_16BITS_WMSK(pmu2_scu_con)); + mmio_write_32(PMU_BASE + PMU2_SCU_PWR_SFTCON, WITH_16BITS_WMSK(pmu2_scu_sftcon)); + mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(0), WITH_16BITS_WMSK(pmu2_cpu_auto_con)); + + /* ddr pwr con0 */ + mmio_write_32(PMU_BASE + PMU1_DDR_CH0PWR_CON, WITH_16BITS_WMSK(pmu1_ddr_ch_pwr_con)); + mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON, WITH_16BITS_WMSK(pmu1_ddr_axi_pwr_con)); + + /* cru pwr con */ + mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON(0), WITH_16BITS_WMSK(pmu1_cru_con[0])); + mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON(1), WITH_16BITS_WMSK(pmu1_cru_con[1])); + + /* pll con */ + mmio_write_32(PMU_BASE + PMU1_PLLPD_CON, WITH_16BITS_WMSK(pmu1_pll_con)); + + /* global */ + mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, BITS_WITH_WMASK(1, 0x1, 0)); + mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, pmu1_wkup_int_con); + mmio_write_32(PMU_BASE + PMU1_PWR_CON, WITH_16BITS_WMSK(pmu1_pwr_con)); + mmio_write_32(PMU_BASE + PMU0_PWR_CON, WITH_16BITS_WMSK(pmu0_pwr_con)); +} + +static void pmu_sleep_restore(void) +{ + /* bus / pd */ + mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON, 0xffff0000); + mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON, 0xffff0000); + + /* clust idle */ + mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, 0xffff0000); + mmio_write_32(PMU_BASE + PMU2_SCU_PWR_CON, 0xffff0000); + mmio_write_32(PMU_BASE + PMU2_SCU_PWR_SFTCON, 0xffff0000); + mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(0), 0xffff0000); + + /* ddr pwr con0 */ + mmio_write_32(PMU_BASE + PMU1_DDR_CH0PWR_CON, 0xffff0000); + mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON, 0xffff0000); + + /* cru pwr con */ + mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON(0), 0xffff0000); + mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON(1), 0xffff0000); + + /* pll con */ + mmio_write_32(PMU_BASE + PMU1_PLLPD_CON, 0xffff0000); + + mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 0xffff0000); + mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, 0); + mmio_write_32(PMU_BASE + PMU1_PWR_CON, 0xffff0000); + mmio_write_32(PMU_BASE + PMU0_PWR_CON, 0xffff0000); +} + +static void secure_watchdog_disable(void) +{ + ddr_data.sys_sgrf_con = + mmio_read_32(SYSSGRF_BASE + SYSSGRF_CON); + + /* pause wdt_s */ + mmio_write_32(SYSSGRF_BASE + SYSSGRF_CON, + BITS_WITH_WMASK(1, 0x1, 0)); +} + +static void secure_watchdog_restore(void) +{ + mmio_write_32(SYSSGRF_BASE + SYSSGRF_CON, + ddr_data.sys_sgrf_con | BITS_WMSK(0x1, 0)); + + if (mmio_read_32(WDT_S_BASE + WDT_CR) & WDT_EN) + mmio_write_32(WDT_S_BASE + WDT_CRR, 0x76); +} + +static void soc_sleep_config(void) +{ + ddr_data.pmugrf_soc_con0 = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(0)); + ddr_data.pmugrf_soc_con1 = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(1)); + ddr_data.pmugrf_soc_con4 = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(4)); + ddr_data.pmugrf_soc_con5 = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(5)); + ddr_data.pmugrf_soc_con6 = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(6)); + ddr_data.pmugrf_soc_con7 = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(7)); + + pmu_sleep_config(); + ddr_sleep_config(); + secure_watchdog_disable(); +} + +static void soc_sleep_restore(void) +{ + secure_watchdog_restore(); + ddr_sleep_config_restore(); + pmu_sleep_restore(); + + mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(0), WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con0)); + mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(1), WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con1)); + mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(4), WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con4)); + mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(5), WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con5)); + mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(6), WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con6)); + mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(7), WITH_16BITS_WMSK(ddr_data.pmugrf_soc_con7)); +} + +static void pm_pll_suspend(void) +{ + ddr_data.cru_mode_con = mmio_read_32(TOPCRU_BASE + 0x280); + + /* pll switch to slow mode */ + mmio_write_32(TOPCRU_BASE + 0x280, 0x003f0000); +} + +static void pm_pll_restore(void) +{ + mmio_write_32(TOPCRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con)); +} + +int rockchip_soc_sys_pwr_dm_suspend(void) +{ + psram_sleep_cfg->pm_flag &= ~PM_WARM_BOOT_BIT; + + clk_gate_con_save(); + clk_gate_con_disable(); + pmu_power_domains_suspend(); + soc_sleep_config(); + pm_pll_suspend(); + vd_core_save(); + + return 0; +} + +int rockchip_soc_sys_pwr_dm_resume(void) +{ + vd_core_restore(); + pm_pll_restore(); + soc_sleep_restore(); + pmu_power_domains_resume(); + plat_rockchip_gic_cpuif_enable(); + clk_gate_con_restore(); + + psram_sleep_cfg->pm_flag |= PM_WARM_BOOT_BIT; + + return 0; +} + +static __pmusramfunc void pmusram_wfi(void) +{ + pmusram_data.idle_msk[0] = + BIT(pmu_bus_id_peri) | + BIT(pmu_bus_id_vi) | + BIT(pmu_bus_id_vepu) | + 0; + + pmusram_data.idle_msk[1] = + BIT(pmu_bus_id_ddr) | + BIT(pmu_bus_id_subddr) | + BIT(pmu_bus_id_cfgddr) | + 0; + + pmusram_pmu_bus_idle_req_msk(pmusram_data.idle_msk[0], pmu_bus_idle); + + /* ddr enter self refresh */ + dmc_enter_lp(); + + pmusram_pmu_bus_idle_req_msk(pmusram_data.idle_msk[1], pmu_bus_idle); + + /* + * The HW enters to sleep mode trigger by wfi. + */ + while (1) { + wfi(); + } +} + +void rockchip_soc_sys_pd_pwr_dn_wfi(void) +{ + disable_mmu_icache_el3(); + dsb(); + isb(); + + rockchip_set_sp(PSRAM_SP_TOP); + pmusram_wfi(); +} + +void __dead2 rockchip_soc_soft_reset(void) +{ + /* pll slow mode */ + mmio_write_32(TOPCRU_BASE + CRU_MODE_CON, 0x003f0000); + + dsb(); + isb(); + + INFO("system reset......\n"); + mmio_write_32(TOPCRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); + + /* + * Maybe the HW needs some times to reset the system, + * so we do not hope the core to execute valid codes. + */ + while (1) { + wfi(); + } +} + +void __dead2 rockchip_soc_system_off(void) +{ + INFO("system poweroff......\n"); + dsb(); + + /* + * Maybe the HW needs some times to power off the system, + * so we do not hope the core to execute valid codes. + */ + while (1) { + wfi(); + } +} + +static void rockchip_pmu_pd_init(void) +{ + pmu_set_power_domain(pmu_pd_npu, pmu_pd_on); + + INFO("idle_st=0x%x, pd_st=0x%x\n", + mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST), + mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST)); +} + +void plat_rockchip_pmu_init(void) +{ + int cpu; + + for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) + cpuson_flags[cpu] = 0; + + psram_sleep_cfg->sp = PSRAM_SP_TOP; + psram_sleep_cfg->ddr_func = (uint64_t)ddr_resume; + psram_sleep_cfg->ddr_data = 0; + psram_sleep_cfg->ddr_flag = 0; + psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; + psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT; + + nonboot_cpus_off(); + + mmio_write_32(PMU_BASE + PMU2_NOC_AUTO_CON, 0xffffffff); + + /* pmusram remap to 0x0 */ + mmio_write_32(PMUSGRF_BASE + PMUSGRF_SOC_CON(1), BITS_WITH_WMASK(2, 0x3, 9)); + + /* PMU_WAKEUP_TIMEOUT_CNT = 0, disable TIMEOUT_WAKEUP by default */ + mmio_write_32(PMU_BASE + PMU1_WAKEUP_TIMEOUT, 0); + + rockchip_pmu_pd_init(); + + pm_reg_rgns_init(); +} diff --git a/plat/rockchip/rv1126b/drivers/pmu/pmu.h b/plat/rockchip/rv1126b/drivers/pmu/pmu.h new file mode 100644 index 000000000..c0b15a844 --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/pmu/pmu.h @@ -0,0 +1,512 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#ifndef __PMU_H__ +#define __PMU_H__ + +#include <assert.h> + +#include <lib/mmio.h> +#include <platform_def.h> + +/* pmu */ +#define PMU1_OFFSET 0x4000 +#define PMU2_OFFSET 0x8000 + +#define PMU0_PWR_CON 0x0000 +#define PMU0_PMIC_STABLE_CNT 0x0010 +#define PMU0_INFO_TX_CON 0x0030 +#define PMU0_INFO_SFT_CON 0x0034 +#define PMU0_PWR_ACK_SEL_CON 0x0040 +#define PMU0_BUS_IDLE_ACK 0x0044 +#define PMU0_BUS_IDLE_ST 0x0048 + +#define PMU1_VERSION_ID (PMU1_OFFSET + 0x000) +#define PMU1_PWR_CON (PMU1_OFFSET + 0x004) +#define PMU1_PWR_FSM (PMU1_OFFSET + 0x008) +#define PMU1_INT_MASK_CON (PMU1_OFFSET + 0x00c) +#define PMU1_WAKEUP_INT_CON (PMU1_OFFSET + 0x010) +#define PMU1_WAKEUP_INT_ST (PMU1_OFFSET + 0x014) +#define PMU1_WAKEUP_EDGE_CON (PMU1_OFFSET + 0x018) +#define PMU1_WAKEUP_EDGE_ST (PMU1_OFFSET + 0x01c) +#define PMU1_WAKEUP_TIMEOUT_CNT_ST (PMU1_OFFSET + 0x020) +#define PMU1_DDR_CH0PWR_CON (PMU1_OFFSET + 0x100) +#define PMU1_DDR_CH0PWR_SFTCON (PMU1_OFFSET + 0x110) +#define PMU1_DDR_AXIPWR_CON (PMU1_OFFSET + 0x120) +#define PMU1_DDR_AXIPWR_SFTCON(i) (PMU1_OFFSET + 0x130 + (i) * 4) +#define PMU1_DDR_PWR_FSM (PMU1_OFFSET + 0x140) +#define PMU1_DDR_ST (PMU1_OFFSET + 0x144) +#define PMU1_DDR_AXI_ST (PMU1_OFFSET + 0x148) +#define PMU1_CRU_PWR_CON(i) (PMU1_OFFSET + 0x200 + (i) * 4) +#define PMU1_CRU_PWR_SFTCON(i) (PMU1_OFFSET + 0x208 + (i) * 4) +#define PMU1_CRU_PWR_FSM (PMU1_OFFSET + 0x210) +#define PMU1_PLLPD_CON (PMU1_OFFSET + 0x220) +#define PMU1_PLLPD_SFTCON (PMU1_OFFSET + 0x228) +#define PMU1_PMIC_STABLE_CNT (PMU1_OFFSET + 0x300) +#define PMU1_OSC_STABLE_CNT (PMU1_OFFSET + 0x304) +#define PMU1_WAKEUP_RST_CLR_CNT (PMU1_OFFSET + 0x308) +#define PMU1_PLL_LOCK_CNT (PMU1_OFFSET + 0x30c) +#define PMU1_WAKEUP_TIMEOUT (PMU1_OFFSET + 0x310) +#define PMU1_PWM_SWITCH_CNT (PMU1_OFFSET + 0x314) +#define PMU1_SLEEP_CNT (PMU1_OFFSET + 0x318) + +#define PMU2_SCU_PWR_CON (PMU2_OFFSET + 0x000) +#define PMU2_SCU_PWR_SFTCON (PMU2_OFFSET + 0x004) +#define PMU2_SCU_AUTO_PWR_CON (PMU2_OFFSET + 0x008) +#define PMU2_SCU_PWR_FSM_STATUS (PMU2_OFFSET + 0x00c) +#define PMU2_DBG_PWR_CON (PMU2_OFFSET + 0x018) +#define PMU2_CLUSTER_PWR_ST (PMU2_OFFSET + 0x01c) +#define PMU2_CLUSTER_IDLE_CON (PMU2_OFFSET + 0x020) +#define PMU2_CLUSTER_IDLE_SFTCON (PMU2_OFFSET + 0x024) +#define PMU2_SCU_PWRUP_CNT (PMU2_OFFSET + 0x040) +#define PMU2_SCU_PWRDN_CNT (PMU2_OFFSET + 0x044) +#define PMU2_SCU_STABLE_CNT (PMU2_OFFSET + 0x048) +#define PMU2_CPU_AUTO_PWR_CON(i) (PMU2_OFFSET + 0x080 + (i) * 4) +#define PMU2_CPU_PWR_SFTCON(i) (PMU2_OFFSET + 0x0a0 + (i) * 4) +#define PMU2_BUS_IDLE_CON (PMU2_OFFSET + 0x100) +#define PMU2_BUS_IDLE_SFTCON (PMU2_OFFSET + 0x110) +#define PMU2_BUS_IDLE_ACK (PMU2_OFFSET + 0x120) +#define PMU2_BUS_IDLE_ST (PMU2_OFFSET + 0x128) +#define PMU2_NOC_AUTO_CON (PMU2_OFFSET + 0x130) +#define PMU2_NOC_AUTO_SFTCON (PMU2_OFFSET + 0x140) +#define PMU2_PWR_GATE_CON (PMU2_OFFSET + 0x200) +#define PMU2_PWR_GATE_SFTCON (PMU2_OFFSET + 0x210) +#define PMU2_VOL_GATE_CON (PMU2_OFFSET + 0x220) +#define PMU2_PWR_GATE_ST (PMU2_OFFSET + 0x230) +#define PMU2_PWR_GATE_FSM (PMU2_OFFSET + 0x238) +#define PMU2_PWRDN_ACK_ST (PMU2_OFFSET + 0x240) +#define PMU2_PWR_C0_ACK_SEL_CON (PMU2_OFFSET + 0x280) + +/* PMU0CRU */ +#define PMU0CRU_CLKSEL_CON(i) (0x300 + (i) * 0x4) +#define PMU0CRU_CLKSEL_CON_CNT 9 +#define PMU0CRU_CLKGATE_CON(i) (0x800 + (i) * 0x4) +#define PMU0CRU_CLKGATE_CON_CNT 4 +#define PMU0CRU_SOFTRST_CON(i) (0xa00 + (i) * 0x4) +#define PMU0CRU_SOFTRST_CON_CNT 4 +#define PMU0CRU_AUTOCS_BUSCLK_MUX_CON(i) (0xd00 + (i) * 0x4) + +/* PMU1CRU */ +#define PMU1CRU_CLKSEL_CON(i) (0x300 + (i) * 0x4) +#define PMU1CRU_CLKSEL_CON_CNT 2 +#define PMU1CRU_CLKGATE_CON(i) (0x800 + (i) * 0x4) +#define PMU1CRU_CLKGATE_CON_CNT 2 +#define PMU1CRU_SOFTRST_CON(i) (0xa00 + (i) * 0x4) +#define PMU1CRU_SOFTRST_CON_CNT 2 + +/* PMUSCRU */ +#define PMUSCRU_CLKGATE_CON0 0x800 +#define PMUSCRU_CLKGATE_CON_CNT 1 +#define PMUSCRU_SOFTRST_CON0 0xa00 + +/* PMUGRF */ +#define PMUGRF_SOC_CON(i) ((i) * 4) +#define PMUGRF_AAD_CON0 0x80 +#define PMUGRF_MEM_CON(i) (0x140 + (i) * 4) +#define PMUGRF_SOC_STATUS(i) (0x170 + (i) * 4) +#define PMUGRF_OS_REG(i) (0x200 + (i) * 4) + +#define PMU_MCU_RST BIT(8) +#define PMU_MCU_HALT BIT(9) + +#define PMU_MCU_STOP_MSK \ + (PMU_MCU_HALT | PMU_MCU_RST) + +#define CORES_PM_DISABLE 0x0 + +/* pmuioc */ +#define PMUIO0_IOC_GPIO0A_IOMUX_SEL_L 0x000 +#define PMUIO0_IOC_GPIO0A_IOMUX_SEL_H 0x004 +#define PMUIO0_IOC_GPIO0B_IOMUX_SEL_L 0x008 +#define PMUIO0_IOC_GPIO0B_IOMUX_SEL_H 0x00c + +#define PMUIO1_IOC_GPIO0C_IOMUX_SEL_L 0x010 +#define PMUIO1_IOC_GPIO0C_IOMUX_SEL_H 0x014 +#define PMUIO1_IOC_GPIO0D_IOMUX_SEL_L 0x018 + +/* PMU_PWR_CON */ +enum pmu0_pwr_con { + pmu_powermode0_en = 0, + pmu_pmu1_pd_byp = 1, + pmu_pmu1_bus_byp = 2, + pmu_pmu0_pmic_stable_byp = 4, + pmu_pmu1_pwrgt = 8, + pmu_pmu1_pwrgt_sft = 9, + pmu_pmu1_mempwr_sft_gt = 10, + pmu_pmu1_idle_en = 11, + pmu_pmu1_idle_sft_en = 12, + pmu_pmu1_noc_auto_en = 13 +}; + +enum pmu1_pwr_con { + pmu_powermode_en = 0, + pmu_scu0_byp = 1, + pmu_scu1_byp = 2, + pmu_bus_byp = 4, + pmu_ddr_byp = 5, + pmu_pwrgt_byp = 6, + pmu_cru_byp = 7, + pmu_pdpmu1_byp = 9, + pmu_wfi_byp = 12, + pmu_slp_cnt_en = 13, + pmu_wkup_pmu_sft_en = 14, +}; + +enum pmu_wakeup_int { + pmu_wkup_cpu0_int = 0, + pmu_wkup_cpu1_int = 1, + pmu_wkup_cpu2_int = 2, + pmu_wkup_cpu3_int = 3, + pmu_wkup_gpio0_int = 4, + pmu_wkup_sdmmc0_int = 5, + pmu_wkup_sdmmc1_int = 6, + pmu_wkup_sdio_int = 7, + pmu_wkup_usbdev_int = 8, + pmu_wkup_uart0_int = 9, + pmu_wkup_i2c2_int = 10, + pmu_wkup_pwm1_int = 11, + pmu_wkup_timer_int = 12, + pmu_wkup_hptimer_int = 13, + pmu_wkup_sys_int = 14, + pmu_wkup_aov_int = 15, + pmu_wkup_aad_int = 16, + pmu_wkup_timeout = 17, +}; + +/* PMU_DDR_PWR_CON */ +enum pmu_ddr_ch_pwr_con { + pmu_ddr_sref_c_en = 0, + pmu_ddr_ioret_en = 1, + pmu_ddr_ioret_exit_en = 2, + pmu_ddr_rstiov_en = 3, + pmu_ddr_rstiov_exit_en = 4, + pmu_ddrctl_c_auto_gating_en = 5, + pmu_ddrphy_auto_gating_en = 6, +}; + +enum pmu_ddr_axi_pwr_con { + pmu_ddr_sref_a_ch0_en = 0, + pmu_ddr_sref_a_ch1_en = 1, + pmu_ddr_sref_a_ch2_en = 2, + pmu_ddr_sref_a_ch3_en = 3, +}; + +/* PMU_CRU_PWR_CON0 */ +enum pmu_cru_pwr_con0 { + pmu_alive_32k_en = 0, + pmu_osc_dis_en = 1, + pmu_wakeup_rst_en = 2, + pmu_input_clamp_en = 3, + pmu_alive_osc_mode_en = 4, + pmu_power_off_en = 5, + pmu_pwm_switch_en = 6, + pmu_pwm_gpio_ioe_en = 7, + pmu_pwm_switch_io = 8, + pmu_pwm_clkgt_en = 9, +}; + +/* PMU_CRU_PWR_CON1 */ +enum pmu_cru_pwr_con1 { + pmu_peri_clksrc_gt_en = 0, + pmu_vepu_clksrc_gt_en = 1, + pmu_vcp_clksrc_gt_en = 2, + pmu_vi_clksrc_gt_en = 3, + pmu_npu_clksrc_gt_en = 4, + pmu_vdo_clksrc_gt_en = 5, + pmu_aisp_clksrc_gt_en = 6, + pmu_core_clksrc_gt_en = 7, + pmu_ddr_clksrc_gt_en = 8, + pmu_bus_clksrc_gt_en = 9, +}; + +/* PMU_SCU_PWR_CON */ +enum pmu_scu_pwr_con { + pmu_l2_flush_en = 0, + pmu_l2_ilde_en = 1, + pmu_scu_pd_en = 2, + pmu_scu_pwroff_en = 3, + pmu_clst_cpu_pd_en = 5, + pmu_clst_clksrc_gt_en = 6, + pmu_std_wfi_bypass = 8, + pmu_std_wfil2_bypass = 9, +}; + +enum pmu_scu_pwr_sftcon { + pmu_l2_flush_req_clst_cfg = 0, + pmu_acinactm_clst_cfg = 1, + pmu_scu_pd_sft_en = 2, + pmu_scu_pwroff_sft_en = 3, + pmu_scu_vol_gate = 5, + pmu_scu_dwn_ack_sel = 6, +}; + +/* PMU_PLLPD_CON */ +enum pmu_pllpd_con { + pmu_gpll_pd_en = 0, + pmu_dpll_pd_en = 1, + pmu_cpll_pd_en = 2, + pmu_ppll_pd_en = 3, +}; + +/* PMU_CLST_PWR_ST */ +enum pmu_clst_pwr_st { + pmu_cpu0_wfi = 0, + pmu_cpu1_wfi = 1, + pmu_cpu2_wfi = 2, + pmu_cpu3_wfi = 3, + pmu_standbywfil2 = 5, + pmu_l2flushdone = 6, + pmu_cpu0_pd_st = 8, + pmu_cpu1_pd_st = 9, + pmu_cpu2_pd_st = 10, + pmu_cpu3_pd_st = 11, + pmu_scu_pd_st = 12, +}; + +/* PMU_CLST_IDLE_CON */ +enum pmu_clst_idle_con { + pmu_idle_req_cpu = 2, + pmu_core_clk_gt_msk = 3, +}; + +enum cores_pm_ctr_mode { + core_pwr_pd = 0, + core_pwr_wfi = 1, + core_pwr_wfi_int = 2, + core_pwr_wfi_reset = 3, +}; + +/* PMU_CPUX_AUTO_PWR_CON */ +enum pmu_cpu_auto_pwr_con { + pmu_cpu_pm_en = 0, + pmu_cpu_pm_int_wakeup_en = 1, + pmu_cpu_pm_dis_int = 2, + pmu_cpu_pm_sft_wakeup_en = 3, + pmu_cpu_auto_pwrdn_mode = 4, + pmu_cpu_cluster_wakeup_en = 5, +}; + +enum qos_id { + qos_cpu = 0, + qos_npu = 1, + qos_aiisp = 2, + qos_dma2ddr = 3, + qos_emmc = 4, + qos_fspi = 5, + qos_u2host = 6, + qos_u3otg = 7, + qos_rkvenc = 8, + qos_saradc0 = 9, + qos_sdmmc1 = 10, + qos_lpmcu = 11, + qos_dcf = 12, + qos_mcu = 13, + qos_rga = 14, + qos_rkce = 15, + qos_rkdma = 16, + qos_decom = 17, + qos_ooc = 18, + qos_rkjpeg = 19, + qos_rkvdec = 20, + qos_vop = 21, + qos_avsp_ro = 22, + qos_avsp_wo = 23, + qos_fec_ro = 24, + qos_fec_wo = 25, + qos_aad = 26, + qos_afe = 27, + qos_atdd = 28, + qos_fspi1 = 29, + qos_lpdma = 30, + qos_spi2apb = 31, + qos_gmac = 32, + qos_isp = 33, + qos_rkcan0 = 34, + qos_rkcan1 = 35, + qos_sdmmc0 = 36, + qos_vicap = 37, + qos_vpsi = 38, + qos_vpss = 39, + qos_saradc1 = 40, + qos_saradc2 = 41, +}; + +enum pmu_bus_id { + pmu_bus_id_ddr = 0, + pmu_bus_id_subddr = 1, + pmu_bus_id_cfgddr = 2, + pmu_bus_id_peri = 3, + pmu_bus_id_vepu = 4, + pmu_bus_id_vcp = 5, + pmu_bus_id_vi = 6, + pmu_bus_id_cru = 7, + pmu_bus_id_npu = 8, + pmu_bus_id_vdo = 9, + pmu_bus_id_aisp = 10, + pmu_bus_id_bus = 11, + pmu_bus_id_max, +}; + +enum pmu_pd_id { + pmu_pd_npu = 0, + pmu_pd_vdo = 1, + pmu_pd_aiisp = 2, + pmu_pd_id_max, +}; + +enum pmu_vd_id { + pmu_vd_npu = 0, + pmu_vd_id_max, +}; + +enum pmu_bus_state { + pmu_bus_active = 0, + pmu_bus_idle = 1, +}; + +enum pmu_pd_state { + pmu_pd_on = 0, + pmu_pd_off = 1 +}; + +#define PD_CTR_LOOP 5000 +#define WFEI_CHECK_LOOP 5000 +#define BUS_IDLE_LOOP 1000 +#define NONBOOT_CPUS_OFF_LOOP 500000 + +#define REBOOT_FLAG 0x5242C300 +#define BOOT_BROM_DOWNLOAD 0xef08a53c + +#define BOOTROM_SUSPEND_MAGIC 0x02468ace +#define BOOTROM_RESUME_MAGIC 0x13579bdf +#define WARM_BOOT_MAGIC 0x76543210 +#define VALID_GLB_RST_MSK 0xffff + +#define DEFAULT_BOOT_CPU 0 + +/******************************************************* + * sleep mode define + *******************************************************/ +#define SLP_ARMPD BIT(0) +#define SLP_ARMOFF BIT(1) +#define SLP_ARMOFF_DDRPD BIT(2) +#define SLP_ARMOFF_LOGOFF BIT(3) +#define SLP_ARMOFF_PMUOFF BIT(4) +#define SLP_FROM_UBOOT BIT(5) + +/* all plls except ddr's pll*/ +#define SLP_PMU_HW_PLLS_PD BIT(8) +#define SLP_PMU_PMUALIVE_32K BIT(9) +#define SLP_PMU_DIS_OSC BIT(10) + +#define SLP_CLK_GT BIT(16) +#define SLP_PMIC_LP BIT(17) + +#define SLP_32K_IO BIT(23) +#define SLP_32K_EXT BIT(24) +#define SLP_TIME_OUT_WKUP BIT(25) +#define SLP_PMU_DBG BIT(26) +#define SLP_LP_PR BIT(27) +#define SLP_ARCH_TIMER_RESET BIT(28) +#define SLP_LP_AOA BIT(29) + +#define PM_INVALID_GPIO 0xffff +#define MAX_GPIO0_IO_CNT 26 +#define MAX_SLEEP_IO_CFG_CNT MAX_GPIO0_IO_CNT +#define MAX_VIRTUAL_PWROFF_IRQ_CNT 20 + +enum { + RK_PM_VIRT_PWROFF_EN = 0, + RK_PM_VIRT_PWROFF_IRQ_CFG = 1, + RK_PM_VIRT_PWROFF_MAX, +}; + +/* sleep pin */ +#define RKPM_SLEEP_PIN0_EN BIT(0) /* GPIO0_A3 */ +#define RKPM_SLEEP_PIN1_EN BIT(1) /* GPIO0_A4 */ +#define RKPM_SLEEP_PIN2_EN BIT(2) /* GPIO0_A5 */ + +#define RKPM_SLEEP_PIN0_ACT_LOW BIT(0) /* GPIO0_A3 */ +#define RKPM_SLEEP_PIN1_ACT_LOW BIT(1) /* GPIO0_A4 */ +#define RKPM_SLEEP_PIN2_ACT_LOW BIT(2) /* GPIO0_A5 */ + +/* io config */ +#define RKPM_IO_CFG_IOMUX_SFT 0 +#define RKPM_IO_CFG_GPIO_DIR_SFT 8 +#define RKPM_IO_CFG_GPIO_LVL_SFT 9 +#define RKPM_IO_CFG_PULL_SFT 10 +#define RKPM_IO_CFG_ID_SFT 16 + +#define RKPM_IO_CFG_IOMUX_MSK 0x3f +#define RKPM_IO_CFG_GPIO_DIR_MSK 0x1 +#define RKPM_IO_CFG_GPIO_LVL_MSK 0x1 +#define RKPM_IO_CFG_PULL_MSK 0x3 +#define RKPM_IO_CFG_ID_MSK 0xffff + +#define RKPM_IO_CFG_IOMUX_GPIO_VAL 0 +#define RKPM_IO_CFG_GPIO_DIR_INPUT_VAL 0 +#define RKPM_IO_CFG_GPIO_DIR_OUTPUT_VAL 1 +#define RKPM_IO_CFG_GPIO_LVL_LOW_VAL 0 +#define RKPM_IO_CFG_GPIO_LVL_HIGH_VAL 1 +#define RKPM_IO_CFG_PULL_NONE_VAL 0 +#define RKPM_IO_CFG_PULL_UP_VAL 1 +#define RKPM_IO_CFG_PULL_DOWN_VAL 2 + +#define RKPM_IO_CFG_IOMUX(func) ((func) << RKPM_IO_CFG_IOMUX_SFT) +#define RKPM_IO_CFG_GPIO_DIR_INPUT \ + (RKPM_IO_CFG_GPIO_DIR_INPUT_VAL << RKPM_IO_CFG_GPIO_DIR_SFT) +#define RKPM_IO_CFG_GPIO_DIR_OUTPUT \ + (RKPM_IO_CFG_GPIO_DIR_OUTPUT_VAL << RKPM_IO_CFG_GPIO_DIR_SFT) +#define RKPM_IO_CFG_GPIO_LVL_LOW \ + (RKPM_IO_CFG_GPIO_LVL_LOW_VAL << RKPM_IO_CFG_GPIO_LVL_SFT) +#define RKPM_IO_CFG_GPIO_LVL_HIGH \ + (RKPM_IO_CFG_GPIO_LVL_HIGH_VAL << RKPM_IO_CFG_GPIO_LVL_SFT) +#define RKPM_IO_CFG_PULL_NONE \ + (RKPM_IO_CFG_PULL_NONE_VAL << RKPM_IO_CFG_PULL_SFT) +#define RKPM_IO_CFG_PULL_UP \ + (RKPM_IO_CFG_PULL_UP_VAL << RKPM_IO_CFG_PULL_SFT) +#define RKPM_IO_CFG_PULL_DOWN \ + (RKPM_IO_CFG_PULL_DOWN_VAL << RKPM_IO_CFG_PULL_SFT) +#define RKPM_IO_CFG_ID(id) ((id) << RKPM_IO_CFG_ID_SFT) +#define RKPM_IO_CFG_IOMUX_GPIO \ + RKPM_IO_CFG_IOMUX(RKPM_IO_CFG_IOMUX_GPIO_VAL) + +#define RKPM_IO_CFG_GET_IOMUX(cfg) \ + (((cfg) >> RKPM_IO_CFG_IOMUX_SFT) & RKPM_IO_CFG_IOMUX_MSK) +#define RKPM_IO_CFG_GET_GPIO_DIR(cfg) \ + (((cfg) >> RKPM_IO_CFG_GPIO_DIR_SFT) & RKPM_IO_CFG_GPIO_DIR_MSK) +#define RKPM_IO_CFG_GET_GPIO_LVL(cfg) \ + (((cfg) >> RKPM_IO_CFG_GPIO_LVL_SFT) & RKPM_IO_CFG_GPIO_LVL_MSK) +#define RKPM_IO_CFG_GET_PULL(cfg) \ + (((cfg) >> RKPM_IO_CFG_PULL_SFT) & RKPM_IO_CFG_PULL_MSK) +#define RKPM_IO_CFG_GET_ID(cfg) \ + (((cfg) >> RKPM_IO_CFG_ID_SFT) & RKPM_IO_CFG_ID_MSK) + +#define pmu_bus_idle_st(id) \ + (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST) & BIT(id))) + +#define pmu_bus_idle_ack(id) \ + (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ACK) & BIT(id))) + +#define pmu_bus_idle_st_msk(msk) \ + (mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST) & (msk)) + +#define pmu_bus_idle_ack_msk(msk) \ + (mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ACK) & (msk)) + +static inline uint32_t read_mem_os_reg(uint32_t id) +{ + assert((id) < MAX_MEM_OS_REG_NUM); + + return mmio_read_32(MEM_OS_REG_BASE + 4 * (id)); +} + +static inline void write_mem_os_reg(uint32_t id, uint32_t val) +{ + assert((id) < MAX_MEM_OS_REG_NUM); + + mmio_write_32(MEM_OS_REG_BASE + 4 * (id), val); +} +#endif /* __PMU_H__ */ diff --git a/plat/rockchip/rv1126b/drivers/secure/secure.c b/plat/rockchip/rv1126b/drivers/secure/secure.c new file mode 100644 index 000000000..dbdb9120b --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/secure/secure.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#include <assert.h> + +#include <lib/mmio.h> + +#include <plat_private.h> +#include <platform_def.h> +#include <secure.h> +#include <soc.h> + +/* unit: Mb */ +static void ddr_fw_rgn_config(uint64_t base_mb, uint64_t top_mb, int rgn_id) +{ + mmio_write_32(FW_DDR_BASE + FIREWALL_DDR_RGN(rgn_id), + RG_MAP_SECURE(top_mb << MB_TO_128KB_SHFT, base_mb << MB_TO_128KB_SHFT)); + + /* enable region */ + mmio_setbits_32(FW_DDR_BASE + FIREWALL_DDR_CON, BIT(rgn_id)); +} + +/* Unit: Kb */ +static void sram_fw_rgn_config(uint64_t base_kb, uint64_t top_kb, int rgn_id) +{ + uint32_t sft = rgn_id * 8; + uint32_t val = RG_MAP_SRAM_SECURE(top_kb, base_kb); + + mmio_write_32(SYSSGRF_BASE + SYSSGRF_FIREWALL_CON(10), BITS_WITH_WMASK(val, 0xff, sft)); + + /* enable region */ + mmio_write_32(SYSSGRF_BASE + SYSSGRF_FIREWALL_CON(11), BITS_WITH_WMASK(1, 0x1, rgn_id)); +} + +static void secure_region_init(void) +{ + uint32_t i; + + /* disable all region first */ + mmio_write_32(FW_DDR_BASE + FIREWALL_DDR_CON, 0x0); + mmio_write_32(SYSSGRF_BASE + SYSSGRF_FIREWALL_CON(11), BITS_WITH_WMASK(0, 0x3, 0)); + + /* all other ns-master can't access all ddr-regions */ + for (i = 0; i < FIREWALL_DDR_MST_CNT; i++) + mmio_write_32(FW_DDR_BASE + FIREWALL_DDR_MST(i), 0xffffffff); + + /* Use FW_DDR_RGN0_REG to config 0~1M of ddr space to secure */ + ddr_fw_rgn_config(TZRAM_BASE >> 20, (TZRAM_BASE + TZRAM_SIZE) >> 20, 0); + + /* Use FIREWALL_SYSMEM_RGN0 to config 48~64k of sram as secure */ + sram_fw_rgn_config(44, 64, 0); +} + +void secure_timer_init(void) +{ + /* rktimer switch to 24M */ + mmio_write_32(TOPCRU_BASE + CRU_CLKSEL_CON(46), BITS_WITH_WMASK(1, 0x1, 11)); + + /* clear hptimer int_st */ + mmio_write_32(HPTIMER_BASE + TIMER_HP_INTR_STATUS, BIT(2)); +} + +void fw_init(void) +{ + int i; + + for (i = 0; i < 10; i++) + mmio_write_32(SYSSGRF_BASE + SYSSGRF_FIREWALL_CON(i), 0xffff0000); + + /* slave as NS, except dcf, otpmask */ + mmio_write_32(SYSSGRF_BASE + SYSSGRF_FIREWALL_CON(4), 0x24002400); + /* slave as NS, except umctl2, dfi */ + mmio_write_32(SYSSGRF_BASE + SYSSGRF_FIREWALL_CON(6), 0xa000a000); + /* slave as NS, except pmusram */ + mmio_write_32(SYSSGRF_BASE + SYSSGRF_FIREWALL_CON(11), BITS_WITH_WMASK(0x1, 0x7f, 4)); + + secure_region_init(); + + /* master as NS */ + mmio_write_32(SYSSGRF_BASE + SYSSGRF_APB_SECURE_CON, 0xffff0000); + /* master as NS */ + mmio_write_32(SYSSGRF_BASE + SYSSGRF_AHB_SECURE_CON, 0xffffffff); + /* master as NS, except dcf */ + mmio_write_32(SYSSGRF_BASE + SYSSGRF_AXI_SECURE_CON, 0xfffffff3); +} + +void secure_init(void) +{ + secure_timer_init(); + fw_init(); +} diff --git a/plat/rockchip/rv1126b/drivers/secure/secure.h b/plat/rockchip/rv1126b/drivers/secure/secure.h new file mode 100644 index 000000000..75361269b --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/secure/secure.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#ifndef SECURE_H +#define SECURE_H + +/* PMUSGRF */ +#define PMUSGRF_SOC_CON(i) ((i) * 4) +#define PMUSGRF_PMUMCU_BOOT_ADDR 0x20 + +/* SYSSGRF */ +#define SYSSGRF_CON 0x0 +#define SYSSGRF_HPMCU_BOOT_ADDR 0xc +#define SYSSGRF_APB_SECURE_CON 0x10 +#define SYSSGRF_AHB_SECURE_CON 0x14 +#define SYSSGRF_AXI_SECURE_CON 0x18 + +#define SYSSGRF_FIREWALL_CON(i) (0x20 + (i) * 4) +#define SYSSGRF_FIREWALL_CON_CNT 12 +#define SYSSGRF_FUSE_CON 0x50 + +/* FW_DDR */ +#define FIREWALL_DDR_RGN(i) ((i) * 0x4) +#define FIREWALL_DDR_RGN_CNT 8 +#define FIREWALL_DDR_MST(i) (0x40 + (i) * 0x4) +#define FIREWALL_DDR_MST_CNT 16 +#define FIREWALL_DDR_CON 0xf0 + +#define PLAT_MAX_DDR_CAPACITY_MB 4096 +#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | ((base) & 0xffff)) +#define MB_TO_128KB_SHFT 3 + +#define FIREWALL_SYSMEM_RGN_CNT 2 + +#define RG_MAP_SRAM_SECURE(top_kb, base_kb) \ + (((((top_kb) / 4 - 1) & 0xf) << 4) | ((base_kb) / 4 & 0xf)) + +void secure_timer_init(void); +void secure_init(void); + +#endif /* SECURE_H */ diff --git a/plat/rockchip/rv1126b/drivers/soc/soc.c b/plat/rockchip/rv1126b/drivers/soc/soc.c new file mode 100644 index 000000000..1616d1e28 --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/soc/soc.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#include <assert.h> +#include <errno.h> + +#include <arch_helpers.h> +#include <bl31/bl31.h> +#include <common/debug.h> +#include <drivers/console.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_compat.h> +#include <platform.h> + +#include <plat_private.h> +#include <platform_def.h> +#include <pmu.h> +#include <rv1126b_clk.h> +#include <secure.h> +#include <soc.h> + +const mmap_region_t plat_rk_mmap[] = { + MAP_REGION_FLAT(RV1126B_DEV_RNG0_BASE, RV1126B_DEV_RNG0_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(DDR_SHARE_MEM, DDR_SHARE_SIZE, + MT_DEVICE | MT_RW | MT_NS), + { 0 } +}; + +/* The RockChip power domain tree descriptor */ +const unsigned char rockchip_power_domain_tree_desc[] = { + /* No of root nodes */ + PLATFORM_SYSTEM_COUNT, + /* No of children for the root node */ + PLATFORM_CLUSTER_COUNT, + /* No of children for the first cluster node */ + PLATFORM_CLUSTER0_CORE_COUNT, +}; + +static void print_glb_reset_status(void) +{ + uint32_t glb_rst_st = 0; + uint32_t warm_boot = 0; + + /* clear CRU_GLB_RST_ST_NCLR if cold boot */ + if (mmio_read_32(PMUGRF_BASE + PMUGRF_OS_REG(11)) == WARM_BOOT_MAGIC) { + glb_rst_st = mmio_read_32(TOPCRU_BASE + CRU_GLB_RST_ST_NCLR); + warm_boot = 1; + } else { + mmio_write_32(PMUGRF_BASE + PMUGRF_OS_REG(11), WARM_BOOT_MAGIC); + } + + mmio_write_32(TOPCRU_BASE + CRU_GLB_RST_ST_NCLR, 0xffff); + + /* save glb_rst_st in mem_os_reg0 */ + write_mem_os_reg(0, glb_rst_st); + + if (warm_boot != 0) + INFO("soc warm boot, reset status: 0x%x\n", glb_rst_st); + else + INFO("soc cold boot\n"); +} + +static void system_reset_init(void) +{ + print_glb_reset_status(); + + /* + * enable tsadc trigger global reset and select first reset. + * enable global reset and wdt trigger pmu reset. + * select first reset trigger pmu reset. + */ + mmio_write_32(TOPCRU_BASE + CRU_GLB_RST_CON(0), 0x3f); + /* the CRU APB is 100M and clk of rst_con0~2 is 24M, + * so need 3 cycle of (24M + apb_cru_clk) to sync at most. + */ + udelay(1); + mmio_write_32(TOPCRU_BASE + CRU_GLB_RST_CON(1), 0x1); + udelay(1); + mmio_write_32(TOPCRU_BASE + CRU_GLB_RST_CON(2), 0x1); + udelay(1); + + /* enable wdt_s reset */ + mmio_write_32(SYSSGRF_BASE + SYSSGRF_CON, BITS_WITH_WMASK(0x1, 0x1, 8)); + + /* enable wdt_ns reset */ + mmio_write_32(SYSGRF_BASE + SYSGRF_BUSGRF_MISC, BITS_WITH_WMASK(0x1, 0x3, 12)); + + /* reset width = 0xffff */ + mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(3), 0xffffffff); + + /* enable first/tsadc/wdt reset output */ + mmio_write_32(PMUSGRF_BASE + PMUSGRF_SOC_CON(0), BITS_WITH_WMASK(0x7, 0x7, 9)); + + /* pmugrf/pmu_ioc hold */ + mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(4), 0xffff0120); + + /* pmusgrf hold */ + mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(5), 0xffff8000); + + /* select tsadc_shut_m0 iomux */ + mmio_write_32(PMU0IOC_BASE + 0x0, 0x00f00030); +} + +void plat_rockchip_soc_init(void) +{ + rockchip_clock_init(); + system_reset_init(); + secure_init(); + rockchip_init_scmi_server(); +} diff --git a/plat/rockchip/rv1126b/drivers/soc/soc.h b/plat/rockchip/rv1126b/drivers/soc/soc.h new file mode 100644 index 000000000..f0cd9c636 --- /dev/null +++ b/plat/rockchip/rv1126b/drivers/soc/soc.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#ifndef __SOC_H__ +#define __SOC_H__ + +#define KHz 1000 +#define MHz (1000 * KHz) +#define OSC_HZ (24 * MHz) + +#define MCU_VALID_START_ADDRESS 0x800000 + +/* CRU */ +#define GLB_SRST_FST_CFG_VAL 0xfdb9 + +#define CRU_PLLS_CON(pll_id, i) ((pll_id) * 0x20 + (i) * 0x4) +#define CRU_PLL_CON(i) ((i) * 0x4) +#define CRU_SSCGTBL_CON(i) (0x140 + (i) * 0x4) +#define CRU_MODE_CON 0x280 +#define CRU_CLKSEL_CON(i) (0x300 + (i) * 0x4) +#define CRU_CLKSEL_CON_CNT 71 +#define CRU_CLKGATE_CON(i) (0x800 + (i) * 0x4) +#define CRU_CLKGATE_CON_CNT 16 +#define CRU_SOFTRST_CON(i) (0xa00 + (i) * 0x4) + +#define CRU_GLB_CNT_TH 0xc00 +#define CRU_GLB_RST_ST 0xc04 +#define CRU_GLB_SRST_FST 0xc08 +#define CRU_GLB_SRST_SND 0xc0c +#define CRU_GLB_RST_CON(i) (0xc10 + (i) * 0x4) +#define CRU_GLB_RST_ST_NCLR 0xc20 + +#define CRU_PLLCON0_FBDIV_MASK 0xfff +#define CRU_PLLCON0_FBDIV_SHIFT 0 +#define CRU_PLLCON0_POSTDIV1_MASK 0x7 +#define CRU_PLLCON0_POSTDIV1_SHIFT 12 +#define CRU_PLLCON0_BYPASS_SHIFT 15 +#define CRU_PLLCON1_REFDIV_MASK 0x3f +#define CRU_PLLCON1_REFDIV_SHIFT 0 +#define CRU_PLLCON1_POSTDIV2_MASK 0x7 +#define CRU_PLLCON1_POSTDIV2_SHIFT 6 +#define CRU_PLLCON1_LOCK_STATUS BIT(10) +#define CRU_PLLCON1_DSMPD_MASK 0x1 +#define CRU_PLLCON1_DSMPD_SHIFT 12 +#define CRU_PLLCON1_PWRDOWN BIT(13) + +/* DDRCRU */ +#define DDRCRU_CLKSEL_CON0 00x300 +#define DDRCRU_CLKGATE_CON0 0x800 +#define DDRCRU_SOFTRST_CON0 0xa00 + +/* PERI_CRU */ +#define PERI_CRU_MODE_CON 0x280 +#define PERI_CRU_CLKSEL_CON(i) (0x300 + (i) * 0x4) +#define PERI_CRU_CLKGATE_CON(i) (0x800 + (i) * 0x4) +#define PERI_CRU_CLKGATE_CON_CNT 2 +#define PERI_CRU_SOFTRST_CON(i) (0xa00 + (i) * 0x4) + +/* BUS CRU */ +#define BUS_CRU_CLKSEL_CON(i) (0x300 + (i) * 0x4) +#define BUS_CRU_CLKGATE_CON(i) (0x800 + (i) * 0x4) +#define BUS_CRU_CLKGATE_CON_CNT 7 +#define BUS_CRU_SOFTRST_CON(i) (0xa00 + (i) * 0x4) + +/* BUS SCRU */ +#define BUS_SCRU_CLKSEL_CON(i) (0x300 + (i) * 0x4) +#define BUS_SCRU_CLKGATE_CON(i) (0x800 + (i) * 0x4) +#define BUS_SCRU_CLKGATE_CON_CNT 3 +#define BUS_SCRU_SOFTRST_CON(i) (0xa00 + (i) * 0x4) + +/* CORE CRU */ +#define CORE_CRU_CLKSEL_CON(i) (0x300 + (i) * 0x4) +#define CORE_CRU_CLKGATE_CON(i) (0x800 + (i) * 0x4) +#define CORE_CRU_CLKGATE_CON_CNT 2 + +/* VI CRU */ +#define VI_CRU_CLKSEL_CON(i) (0x300 + (i) * 0x4) +#define VI_CRU_CLKGATE_CON(i) (0x800 + (i) * 0x4) +#define VI_CRU_CLKGATE_CON_CNT 5 + +/* VEPU CRU */ +#define VEPU_CRU_CLKSEL_CON(i) (0x300 + (i) * 0x4) +#define VEPU_CRU_CLKGATE_CON(i) (0x800 + (i) * 0x4) +#define VEPU_CRU_CLKGATE_CON_CNT 2 + +/* VCP CRU */ +#define VCP_CRU_CLKSEL_CON(i) (0x300 + (i) * 0x4) +#define VCP_CRU_CLKGATE_CON(i) (0x800 + (i) * 0x4) +#define VCP_CRU_CLKGATE_CON_CNT 2 + +/* NPU CRU */ +#define NPU_CRU_CLKSEL_CON0 0x300 +#define NPU_CRU_CLKGATE_CON0 0x800 +#define NPU_CRU_CLKGATE_CON_CNT 1 + +/* VDO CRU */ +#define VDO_CRU_CLKSEL_CON0 0x300 +#define VDO_CRU_CLKGATE_CON(i) (0x800 + (i) * 0x4) +#define VDO_CRU_CLKGATE_CON_CNT 3 + +/* SYSGRF */ +#define SYSGRF_BUSGRF_MISC 0xc +#define SYSGRF_NOC_CON(i) (0x30 + (i) * 4) +#define SYSGRF_NOC_STATUS(i) (0x100 + (i) * 4) +#define SYSGRF_SYS_STATUS 0x118 + +/* CPUGRF */ +#define CPUGRF_CON(i) ((i) * 4) +#define CPUGRF_STATUS(i) (0xc + (i) * 4) + +/* DDRGRF */ +#define DDRGRF_CON(i) ((i) * 4) +#define DDRGRF_STATUS(i) (0x100 + (i) * 4) + +/* pvtm */ +#define PVTM_CON(i) (0x4 + (i) * 4) +#define PVTM_INTEN 0x70 +#define PVTM_INTSTS 0x74 +#define PVTM_STATUS(i) (0x80 + (i) * 4) +#define PVTM_CALC_CNT 0x200 + +enum pvtm_con0 { + pvtm_start = 0, + pvtm_osc_en = 1, + pvtm_osc_sel = 2, + pvtm_rnd_seed_en = 5, +}; + +/* WDT */ +#define WDT_CR 0x0 +#define WDT_TORR 0x4 +#define WDT_CCVR 0x8 +#define WDT_CRR 0xc +#define WDT_STAT 0x10 +#define WDT_EOI 0x14 + +#define WDT_EN BIT(0) +#define WDT_RSP_MODE BIT(1) + +/* timer */ +#define TIMER_LOAD_COUNT0 0x00 +#define TIMER_LOAD_COUNT1 0x04 +#define TIMER_CURRENT_VALUE0 0x08 +#define TIMER_CURRENT_VALUE1 0x0c +#define TIMER_CONTROL_REG 0x10 +#define TIMER_INTSTATUS 0x18 + +#define TIMER_DIS 0x0 +#define TIMER_EN 0x1 + + /* hp timer */ +#define TIMER_HP_REVISION 0x00 +#define TIMER_HP_CTRL 0x04 +#define TIMER_HP_INTR_EN 0x08 +#define TIMER_HP_T24_GCD 0x0c +#define TIMER_HP_T32_GCD 0x10 +#define TIMER_HP_LOAD_COUNT0 0x14 +#define TIMER_HP_LOAD_COUNT1 0x18 +#define TIMER_HP_T24_DELAT_COUNT0 0x1c +#define TIMER_HP_T24_DELAT_COUNT1 0x20 +#define TIMER_HP_CURR_32K_VALUE0 0x24 +#define TIMER_HP_CURR_32K_VALUE1 0x28 +#define TIMER_HP_CURR_TIMER_VALUE0 0x2c +#define TIMER_HP_CURR_TIMER_VALUE1 0x30 +#define TIMER_HP_T24_32BEGIN0 0x34 +#define TIMER_HP_T24_32BEGIN1 0x38 +#define TIMER_HP_T32_24END0 0x3c +#define TIMER_HP_T32_24END1 0x40 +#define TIMER_HP_BEGIN_END_VALID 0x44 +#define TIMER_HP_SYNC_REQ 0x48 +#define TIMER_HP_INTR_STATUS 0x4c +#define TIMER_HP_UPD_EN 0x50 + + /* GPIO */ +#define GPIO_SWPORT_DR_L 0x0000 +#define GPIO_SWPORT_DR_H 0x0004 +#define GPIO_SWPORT_DDR_L 0x0008 +#define GPIO_SWPORT_DDR_H 0x000c +#define GPIO_INT_EN_L 0x0010 +#define GPIO_INT_EN_H 0x0014 +#define GPIO_INT_MASK_L 0x0018 +#define GPIO_INT_MASK_H 0x001c +#define GPIO_INT_TYPE_L 0x0020 +#define GPIO_INT_TYPE_H 0x0024 +#define GPIO_INT_POLARITY_L 0x0028 +#define GPIO_INT_POLARITY_H 0x002c +#define GPIO_INT_BOTHEDGE_L 0x0030 +#define GPIO_INT_BOTHEDGE_H 0x0034 +#define GPIO_DEBOUNCE_L 0x0038 +#define GPIO_DEBOUNCE_H 0x003c +#define GPIO_DBCLK_DIV_EN_L 0x0040 +#define GPIO_DBCLK_DIV_EN_H 0x0044 +#define GPIO_DBCLK_DIV_CON 0x0048 +#define GPIO_INT_STATUS 0x0050 +#define GPIO_INT_RAWSTATUS 0x0058 +#define GPIO_PORT_EOI_L 0x0060 +#define GPIO_PORT_EOI_H 0x0064 +#define GPIO_EXT_PORT 0x0070 +#define GPIO_VER_ID 0x0078 +#define GPIO_STORE_ST_L 0x0080 +#define GPIO_STORE_ST_H 0x0084 +#define GPIO_REG_GROUP_L 0x0100 +#define GPIO_REG_GROUP_H 0x0104 +#define GPIO_VIRTUAL_EN 0x0108 +#define GPIO_REG_GROUP1_L 0x0110 +#define GPIO_REG_GROUP1_H 0x0114 +#define GPIO_REG_GROUP2_L 0x0118 +#define GPIO_REG_GROUP2_H 0x011c +#define GPIO_REG_GROUP3_L 0x0120 +#define GPIO_REG_GROUP3_H 0x0124 + +/* PWM */ +#define PMW_PWRCAPTURE_VAL 0x15c + +#define OTP_CHIP_ID_OFF 0 +#define OTP_FEA_ID_OFF 10 +#define OTP_CHIP_ID_RM_OFF 14 +#define OTP_FEA_ID_RM_OFF 22 + +#define SOC_RV1126B 0x52561126 +#define SOC_UNKNOWN 0xeeee +#define SOC_ROOT 0x0 +#endif /* __SOC_H__ */ diff --git a/plat/rockchip/rv1126b/include/plat.ld.S b/plat/rockchip/rv1126b/include/plat.ld.S new file mode 100644 index 000000000..dc8b6a36b --- /dev/null +++ b/plat/rockchip/rv1126b/include/plat.ld.S @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#ifndef ROCKCHIP_PLAT_LD_S +#define ROCKCHIP_PLAT_LD_S + +MEMORY { + PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE +} + +SECTIONS +{ + . = PMUSRAM_BASE; + + /* + * pmu_cpuson_entrypoint request address + * align 64K when resume, so put it in the + * start of pmusram + */ + .text_pmusram : { + ASSERT(. == ALIGN(4 * 1024), + ".pmusram.entry request 64K aligned."); + KEEP(*(.pmusram.entry)) + __bl31_pmusram_text_start = .; + *(.pmusram.text) + *(.pmusram.rodata) + __bl31_pmusram_text_real_end = .; + __bl31_pmusram_text_end = .; + __bl31_pmusram_data_start = .; + *(.pmusram.data) + __bl31_pmusram_data_real_end = .; + __bl31_pmusram_data_end = .; + + ASSERT(__bl31_pmusram_data_end <= PMUSRAM_BASE + PMUSRAM_RSIZE, + ".pmusram has exceeded its limit."); + } >PMUSRAM +} +#endif /* ROCKCHIP_PLAT_LD_S */ diff --git a/plat/rockchip/rv1126b/include/plat_sip_calls.h b/plat/rockchip/rv1126b/include/plat_sip_calls.h new file mode 100644 index 000000000..a00b0593e --- /dev/null +++ b/plat/rockchip/rv1126b/include/plat_sip_calls.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#ifndef __PLAT_SIP_CALLS_H__ +#define __PLAT_SIP_CALLS_H__ + +#define RK_PLAT_SIP_NUM_CALLS 0 + +#endif /* __PLAT_SIP_CALLS_H__ */ diff --git a/plat/rockchip/rv1126b/include/platform_def.h b/plat/rockchip/rv1126b/include/platform_def.h new file mode 100644 index 000000000..e712a57be --- /dev/null +++ b/plat/rockchip/rv1126b/include/platform_def.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include <arch.h> +#include <common_def.h> + +#include <rv1126b_def.h> + +#define DEBUG_XLAT_TABLE 0 + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#if DEBUG_XLAT_TABLE +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL1 +#define PLATFORM_STACK_SIZE 0x440 +#elif IMAGE_BL2 +#define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL32 +#define PLATFORM_STACK_SIZE 0x440 +#endif + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 0 + +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) + +#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 + +#define PLAT_RK_CLST_TO_CPUID_SHIFT 6 + +/* + * This macro defines the deepest retention state possible. A higher state + * id will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE 1 + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE 2 +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +/* TF txet, ro, rw, Size: 512KB */ +#define TZRAM_BASE RK_DRAM_BASE +#define TZRAM_SIZE 0x100000 + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted RAM + */ +#define BL31_BASE (TZRAM_BASE + 0x0) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +#define ADDR_SPACE_SIZE (1ULL << 32) +#define MAX_XLAT_TABLES 18 +#define MAX_MMAP_REGIONS 27 + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/* + * Define GICD and GICC and GICR base + */ +#define PLAT_RK_GICD_BASE PLAT_GICD_BASE +#define PLAT_RK_GICC_BASE PLAT_GICC_BASE +#define PLAT_RK_GICR_BASE PLAT_GICR_BASE + +#define PLAT_RK_UART_BASE RK_DBG_UART_BASE +#define PLAT_RK_UART_CLOCK RK_DBG_UART_CLOCK +#define PLAT_RK_UART_BAUDRATE RK_DBG_UART_BAUDRATE + +#define PLAT_RK_PRIMARY_CPU 0x0 +#endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/rockchip/rv1126b/plat_sip_calls.c b/plat/rockchip/rv1126b/plat_sip_calls.c new file mode 100644 index 000000000..3a147b5d8 --- /dev/null +++ b/plat/rockchip/rv1126b/plat_sip_calls.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <drivers/scmi-msg.h> + +#include <plat_sip_calls.h> +#include <rockchip_sip_svc.h> + +uintptr_t rockchip_plat_sip_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + switch (smc_fid) { + case RK_SIP_SCMI_AGENT0: + scmi_smt_fastcall_smc_entry(0); + SMC_RET1(handle, 0); + + default: + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} diff --git a/plat/rockchip/rv1126b/platform.mk b/plat/rockchip/rv1126b/platform.mk new file mode 100644 index 000000000..46bb5e6b2 --- /dev/null +++ b/plat/rockchip/rv1126b/platform.mk @@ -0,0 +1,114 @@ +# +# Copyright (c) 2026, Rockchip Electronics Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +RK_PLAT := plat/rockchip +RK_PLAT_SOC := ${RK_PLAT}/${PLAT} +RK_PLAT_COMMON := ${RK_PLAT}/common + +DISABLE_BIN_GENERATION := 1 + +include drivers/arm/gic/v2/gicv2.mk +include lib/libfdt/libfdt.mk +include lib/xlat_tables_v2/xlat_tables.mk + +PLAT_INCLUDES := -Idrivers/arm/gic/common/ \ + -Idrivers/arm/gic/v2/ \ + -Iinclude/bl31 \ + -Iinclude/common \ + -Iinclude/drivers \ + -Iinclude/drivers/arm \ + -Iinclude/drivers/auth \ + -Iinclude/drivers/io \ + -Iinclude/drivers/ti/uart \ + -Iinclude/lib \ + -Iinclude/lib/cpus/${ARCH} \ + -Iinclude/lib/el3_runtime \ + -Iinclude/lib/psci \ + -Iinclude/plat/common \ + -Iinclude/services \ + -Iinclude/plat/common/ \ + -Idrivers/scmi-msg/ \ + -I${RK_PLAT_COMMON}/ \ + -I${RK_PLAT_COMMON}/pmusram/ \ + -I${RK_PLAT_COMMON}/include/ \ + -I${RK_PLAT_COMMON}/drivers/pmu/ \ + -I${RK_PLAT_COMMON}/drivers/parameter/ \ + -I${RK_PLAT_COMMON}/scmi/ \ + -I${RK_PLAT_SOC}/ \ + -I${RK_PLAT_SOC}/drivers/dmc/ \ + -I${RK_PLAT_SOC}/scmi/ \ + -I${RK_PLAT_SOC}/drivers/pmu/ \ + -I${RK_PLAT_SOC}/drivers/secure/ \ + -I${RK_PLAT_SOC}/drivers/soc/ \ + -I${RK_PLAT_SOC}/include/ \ + +RK_GIC_SOURCES := ${GICV2_SOURCES} \ + plat/common/plat_gicv2.c \ + ${RK_PLAT}/common/rockchip_gicv2.c + +PLAT_BL_COMMON_SOURCES := ${XLAT_TABLES_LIB_SRCS} \ + common/desc_image_load.c \ + lib/bl_aux_params/bl_aux_params.c \ + plat/common/aarch64/crash_console_helpers.S \ + plat/common/plat_psci_common.c + +ifneq (${ENABLE_STACK_PROTECTOR},0) +PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c +endif + +BL31_SOURCES += ${RK_GIC_SOURCES} \ + drivers/ti/uart/aarch64/16550_console.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/scmi-msg/base.c \ + drivers/scmi-msg/clock.c \ + drivers/scmi-msg/entry.c \ + drivers/scmi-msg/reset_domain.c \ + drivers/scmi-msg/smt.c \ + lib/cpus/aarch64/cortex_a53.S \ + $(LIBFDT_SRCS) \ + $(ZLIB_SOURCES) \ + ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ + ${RK_PLAT_COMMON}/aarch64/platform_common.c \ + ${RK_PLAT_COMMON}/bl31_plat_setup.c \ + ${RK_PLAT_COMMON}/plat_pm.c \ + ${RK_PLAT_COMMON}/params_setup.c \ + ${RK_PLAT_COMMON}/plat_pm_helpers.c \ + ${RK_PLAT_COMMON}/plat_topology.c \ + ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ + ${RK_PLAT_COMMON}/pmusram/cpus_on_fixed_addr.S \ + ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \ + ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ + ${RK_PLAT_COMMON}/scmi/scmi.c \ + ${RK_PLAT_COMMON}/scmi/scmi_clock.c \ + ${RK_PLAT_COMMON}/scmi/scmi_rstd.c \ + ${RK_PLAT_COMMON}/scmi/rockchip_common_clock.c \ + ${RK_PLAT_SOC}/drivers/dmc/suspend.c \ + ${RK_PLAT_SOC}/plat_sip_calls.c \ + ${RK_PLAT_SOC}/scmi/rv1126b_clk.c \ + ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ + ${RK_PLAT_SOC}/drivers/pmu/pm_pd_regs.c \ + ${RK_PLAT_SOC}/drivers/secure/secure.c \ + ${RK_PLAT_SOC}/drivers/soc/soc.c + +# Enable workarounds for selected Cortex-A53 errata +ERRATA_A53_835769 := 1 +ERRATA_A53_843419 := 1 +ERRATA_A53_855873 := 1 +ERRATA_A53_1530924 := 1 + +ENABLE_PLAT_COMPAT := 0 +MULTI_CONSOLE_API := 1 +CTX_INCLUDE_EL2_REGS := 0 +CTX_INCLUDE_AARCH32_REGS := 0 +INIT_UNUSED_NS_EL2 := 1 + +# Do not enable SVE +ENABLE_SVE_FOR_NS := 0 + +WORKAROUND_CVE_2017_5715 := 0 + +PLAT_EXTRA_LD_SCRIPT := 1 diff --git a/plat/rockchip/rv1126b/rv1126b_def.h b/plat/rockchip/rv1126b/rv1126b_def.h new file mode 100644 index 000000000..1b7df0ece --- /dev/null +++ b/plat/rockchip/rv1126b/rv1126b_def.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#ifndef __PLAT_DEF_H__ +#define __PLAT_DEF_H__ + +#define SIZE_K(n) ((n) * 1024) +#define SIZE_M(n) ((n) * 1024 * 1024) + +#define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) +#define BITS_WMSK(msk, shift) ((msk) << ((shift) + REG_MSK_SHIFT)) + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define RK_DRAM_BASE 0x40000000 +#define RK_DRAM_RGN_BASE 0x0 + +#define RV1126B_DEV_RNG0_BASE 0x00000000 +#define RV1126B_DEV_RNG0_SIZE 0x40000000 + +/* All slave base address declare below */ +#define TOPCRU_BASE 0x20000000 +#define BUSCRU_BASE 0x20010000 +#define PERICRU_BASE 0x20020000 +#define CORECRU_BASE 0x20030000 +#define PMU0CRU_BASE 0x20040000 +#define PMU1CRU_BASE 0x20050000 +#define DDRCRU_BASE 0x20060000 +#define SUBDDRCRU_BASE 0x20068000 +#define VICRU_BASE 0x20070000 +#define VEPUCRU_BASE 0x20080000 +#define NPUCRU_BASE 0x20090000 +#define VDOCRU_BASE 0x200a0000 +#define VCPCRU_BASE 0x200b0000 + +#define SYSGRF_BASE 0x20100000 +#define PERIGRF_BASE 0x20110000 +#define U3PHYGRF_BASE 0x20118000 +#define COREGRF_BASE 0x20120000 +#define PMUGRF_BASE 0x20130000 +#define DDRGRF_BASE 0x20140000 +#define VIGRF_BASE 0x20150000 +#define VEPUGRF_BASE 0x20160000 +#define NPUGRF_BASE 0x20170000 +#define VDOGRF_BASE 0x20180000 +#define VCPGRF_BASE 0x20190000 +#define PMU0IOC_BASE 0x201a0000 +#define PMU1IOC_BASE 0x201a8000 +#define IOC1_BASE 0x201b0000 +#define IOC2_BASE 0x201b8000 +#define IOC3_BASE 0x201c0000 +#define IOC4_BASE 0x201c8000 +#define IOC5_BASE 0x201d0000 +#define IOC6_BASE 0x201d8000 +#define IOC7_BASE 0x201e0000 + +#define BUSSCRU_BASE 0x20200000 +#define PMUSCRU_BASE 0x20210000 + +#define SYSSGRF_BASE 0x20220000 +#define PMUSGRF_BASE 0x20230000 +#define PVTPLL_CORE_BASE 0x20480000 +#define PVTPLL_VI_BASE 0x21C60000 +#define PVTPLL_VEPU_BASE 0x21F00000 +#define PVTPLL_VCP_BASE 0x21FC0000 +#define PVTPLL_NPU_BASE 0x22080000 + +#define GPIO0_BASE 0x20600000 +#define PWM1_BASE 0x20700000 +#define I2C2_BASE 0x20810000 +#define UART0_BASE 0x20810000 +#define HPTIMER_BASE 0x20820000 +#define PMU_BASE 0x20830000 +#define PMU0_BASE 0x20830000 +#define PMU1_BASE 0x20834000 +#define PMU2_BASE 0x20838000 +#define PMU_WDT_BASE 0x20850000 +#define RC_OSC_CTRL_BASE 0x20860000 +#define STIMER_BASE 0x20a00000 +#define WDT_S_BASE 0x20b00000 +#define OTP_S_BASE 0x20b10000 +#define WDT_NS_BASE 0x20b60000 +#define DCF_BASE 0x20b70000 +#define OTP_NS_BASE 0x20b90000 +#define OTP_MASK_BASE 0x20ba0000 +#define TSADC_BASE 0x20bb0000 +#define NSTIMER_BASE 0x20c00000 + +#define UART1_BASE 0x21160000 +#define UART2_BASE 0x21170000 +#define UART3_BASE 0x21180000 +#define UART4_BASE 0x21190000 +#define UART5_BASE 0x211a0000 +#define UART6_BASE 0x211b0000 +#define UART7_BASE 0x211c0000 +#define GIC400_BASE 0x21200000 + +#define GPIO1_BASE 0x21300000 +#define DDRCTL_BASE 0x21600000 +#define DDRPHY_BASE 0x21650000 +#define FW_DDR_BASE 0x21660000 +#define GPIO2_BASE 0x21700000 +#define GPIO4_BASE 0x21800000 +#define GPIO5_BASE 0x21900000 +#define GPIO6_BASE 0x21a00000 +#define GPIO7_BASE 0x21b00000 +#define GPIO3_BASE 0x21e00000 +#define VOP_BASE 0x22150000 + +#define PMUSRAM_RSIZE SIZE_K(8) +#define PMUSRAM_BASE 0x3ff1e000 +#define AOASRAM_BASE 0x3ff20000 +#define SRAM_BASE 0x3ffb0000 + +#define MAX_MEM_OS_REG_NUM 4 +#define MEM_OS_REG_BASE \ + (PMUSRAM_BASE + PMUSRAM_RSIZE - MAX_MEM_OS_REG_NUM * 4) + +#define PSRAM_SP_TOP MEM_OS_REG_BASE + +#define STIMER_CHN_BASE(i) (STIMER_BASE + 0x10000 * (i)) +#define NSTIMER_CHN_BASE(i) (NSTIMER_BASE + 0x10000 * (i)) + +/************************************************************************** + * share mem region allocation: 1M~2M + **************************************************************************/ +#define DDR_SHARE_MEM (RK_DRAM_BASE + SIZE_K(1024)) +#define DDR_SHARE_SIZE SIZE_K(64) + +#define SHARE_MEM_BASE DDR_SHARE_MEM +#define SHARE_MEM_PAGE_NUM 15 +#define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4) + +#define SCMI_SHARE_MEM_BASE (SHARE_MEM_BASE + SHARE_MEM_SIZE) +#define SCMI_SHARE_MEM_SIZE SIZE_K(4) + +#define SMT_BUFFER_BASE SCMI_SHARE_MEM_BASE +#define SMT_BUFFER0_BASE SMT_BUFFER_BASE + +#define ROCKCHIP_PM_REG_REGION_MEM_SIZE SIZE_K(8) + +/************************************************************************** + * UART related constants + **************************************************************************/ +#define RK_DBG_UART_BASE UART0_BASE +#define RK_DBG_UART_BAUDRATE 1500000 +#define RK_DBG_UART_CLOCK 24000000 + +/****************************************************************************** + * GIC-400 & interrupt handling related constants + ******************************************************************************/ + +/* Base rk_platform compatible GIC memory map */ +#define PLAT_GICD_BASE (GIC400_BASE + 0x1000) +#define PLAT_GICC_BASE (GIC400_BASE + 0x2000) +#define PLAT_GICR_BASE 0 + +/****************************************************************************** + * sgi, ppi + ******************************************************************************/ +#define RK_IRQ_SEC_SGI_0 8 +#define RK_IRQ_SEC_SGI_1 9 +#define RK_IRQ_SEC_SGI_2 10 +#define RK_IRQ_SEC_SGI_3 11 +#define RK_IRQ_SEC_SGI_4 12 +#define RK_IRQ_SEC_SGI_5 13 +#define RK_IRQ_SEC_SGI_6 14 +#define RK_IRQ_SEC_SGI_7 15 +#define RK_IRQ_SEC_PHY_TIMER 29 + +/* + * Define a list of Group 0 interrupts. + */ +#define PLAT_RK_GICV2_G0_IRQS \ + INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL) +#endif /* __PLAT_DEF_H__ */ diff --git a/plat/rockchip/rv1126b/scmi/rv1126b_clk.c b/plat/rockchip/rv1126b/scmi/rv1126b_clk.c new file mode 100644 index 000000000..bfae4f540 --- /dev/null +++ b/plat/rockchip/rv1126b/scmi/rv1126b_clk.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#include <assert.h> +#include <errno.h> + +#include <drivers/delay_timer.h> +#include <drivers/scmi.h> +#include <lib/mmio.h> +#include <lib/spinlock.h> + +#include <plat_private.h> +#include <platform_def.h> +#include <rockchip_sip_svc.h> +#include <rv1126b_clk.h> +#include <scmi_clock.h> +#include <soc.h> + +enum pll_type_sel { + PLL_SEL_AUTO, /* all plls (normal pll or pvtpll) */ + PLL_SEL_PVT, + PLL_SEL_NOR, + PLL_SEL_AUTO_NOR /* all normal plls (apll/gpll/npll) */ +}; + +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + +#define GPLL_RATE 1188000000 +#define CPLL_RATE 1000000000 +#define AUPLL_RATE 786431952 + +#define MAX_RATE_TABLE 16 + +#define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift) +#define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift) +#define CLKDIV_4BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0xfU, shift) +#define CLKDIV_3BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x7U, shift) +#define CLKDIV_2BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3U, shift) +#define CLKDIV_1BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1U, shift) + +#define CPU_PLL_PATH_SLOWMODE BITS_WITH_WMASK(0U, 0x3U, 0) +#define CPU_PLL_PATH_NORMAL BITS_WITH_WMASK(1U, 0x3U, 0) +#define CPU_PLL_PATH_DEEP_SLOW BITS_WITH_WMASK(2U, 0x3U, 0) + +#define CRU_PLL_POWER_DOWN BIT_WITH_WMSK(13) +#define CRU_PLL_POWER_UP WMSK_BIT(13) + +#define PRATE(x) static const unsigned long const x[] +#define PINFO(x) static const uint32_t const x[] + +PRATE(p_24m) = { OSC_HZ }; +PRATE(p_100m) = { 100 * MHz}; +PRATE(p_200m) = { 198 * MHz}; +PRATE(p_300m) = { 297 * MHz}; + +PINFO(clk_user_otpc_s_info) = { 0, 0, 0, 0x20200308, 12, 3, 0x20200800, 12 }; +PINFO(clk_sbpi_otpc_s_info) = { 0, 0, 0, 0, 0, 0, 0x20200800, 11 }; +PINFO(pclk_otpc_s_info) = { 0, 0, 0, 0, 0, 0, 0x20200800, 10 }; +PINFO(pclk_key_r_s_info) = { 0, 0, 0, 0, 0, 0, 0x20200800, 13 }; +PINFO(hclk_kl_rkce_s_info) = { 0, 0, 0, 0, 0, 0, 0x20200800, 9 }; +PINFO(hclk_rkce_s_info) = { 0, 0, 0, 0, 0, 0, 0x20200800, 8 }; +PINFO(pclk_wdt_s_info) = { 0, 0, 0, 0, 0, 0, 0x20200800, 6 }; +PINFO(tclk_wdt_s_info) = { 0, 0, 0, 0, 0, 0, 0x20200800, 7 }; +PINFO(clk_stimer0_info) = { 0, 0, 0, 0, 0, 0, 0x20200800, 4 }; +PINFO(clk_stimer1_info) = { 0, 0, 0, 0, 0, 0, 0x20200800, 5 }; +PINFO(pclk_stimer_info) = { 0, 0, 0, 0, 0, 0, 0x20200800, 3 }; +PINFO(hclk_rkrng_s_info) = { 0, 0, 0, 0, 0, 0, 0x20200808, 14 }; +PINFO(clk_pka_rkce_s_info) = { 0, 0, 0, 0, 0, 0, 0x20200808, 13 }; +PINFO(aclk_rkce_s_info) = { 0, 0, 0, 0, 0, 0, 0x20200808, 12 }; + +#define RV1126B_SCMI_CLOCK(_id, _name, _data, _table, _cnt, _is_s) \ +rk_scmi_clock_t _name = { \ + .id = _id, \ + .name = #_name, \ + .clk_ops = _data, \ + .rate_table = _table, \ + .rate_cnt = _cnt, \ + .is_security = _is_s, \ +} + +#define RV1126B_SCMI_CLOCK_COM(_id, _name, _parent_table, _info, _data, \ + _table, is_d, _is_s) \ +rk_scmi_clock_t _name = { \ + .id = _id, \ + .name = #_name, \ + .parent_table = _parent_table, \ + .info = _info, \ + .clk_ops = _data, \ + .rate_table = _table, \ + .rate_cnt = ARRAY_SIZE(_table), \ + .is_dynamic_prate = is_d, \ + .is_security = _is_s, \ +} + +static unsigned long rv1126b_common_rates[] = { + 400000, 24000000, 50000000, 100000000, 198000000, 297000000, 396000000, +}; + +static const struct rk_clk_ops clk_scmi_ops_com = { + .get_rate = clk_scmi_common_get_rate, + .set_rate = clk_scmi_common_set_rate, + .set_status = clk_scmi_common_set_status, +}; + +static const struct rk_clk_ops clk_scmi_ops_gate = { + .get_rate = clk_scmi_common_get_rate, + .set_status = clk_scmi_common_set_status, +}; + +RV1126B_SCMI_CLOCK_COM(CLK_USER_OTPC_S, clk_user_otpc_s, p_24m, clk_user_otpc_s_info, + &clk_scmi_ops_com, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(CLK_SBPI_OTPC_S, clk_sbpi_otpc_s, p_24m, clk_sbpi_otpc_s_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(PCLK_OTPC_S, pclk_otpc_s, p_100m, pclk_otpc_s_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(PCLK_KEY_READER_S, pclk_key_r_s, p_100m, pclk_key_r_s_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(HCLK_KL_RKCE_S, hclk_kl_rkce_s, p_200m, hclk_kl_rkce_s_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(HCLK_RKCE_S, hclk_rkce_s, p_200m, hclk_rkce_s_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(PCLK_WDT_S, pclk_wdt_s, p_100m, pclk_wdt_s_info, + &clk_scmi_ops_gate, rv1126b_common_rates, true, true); +RV1126B_SCMI_CLOCK_COM(TCLK_WDT_S, tclk_wdt_s, p_24m, tclk_wdt_s_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(CLK_STIMER0, clk_stimer0, p_100m, clk_stimer0_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(CLK_STIMER1, clk_stimer1, p_100m, clk_stimer1_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(PLK_STIMER, pclk_stimer, p_100m, pclk_stimer_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(HCLK_RKRNG_S, hclk_rkrng_s, p_200m, hclk_rkrng_s_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(CLK_PKA_RKCE_S, clk_pka_rkce_s, p_200m, clk_pka_rkce_s_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); +RV1126B_SCMI_CLOCK_COM(ACLK_RKCE_S, aclk_rkce_s, p_300m, aclk_rkce_s_info, + &clk_scmi_ops_gate, rv1126b_common_rates, false, true); + +static rk_scmi_clock_t *clock_table[] = { + [CLK_USER_OTPC_S] = &clk_user_otpc_s, + [CLK_SBPI_OTPC_S] = &clk_sbpi_otpc_s, + [PCLK_OTPC_S] = &pclk_otpc_s, + [PCLK_KEY_READER_S] = &pclk_key_r_s, + [HCLK_KL_RKCE_S] = &hclk_kl_rkce_s, + [HCLK_RKCE_S] = &hclk_rkce_s, + [PCLK_WDT_S] = &pclk_wdt_s, + [TCLK_WDT_S] = &tclk_wdt_s, + [CLK_STIMER0] = &clk_stimer0, + [CLK_STIMER1] = &clk_stimer1, + [PLK_STIMER] = &pclk_stimer, + [HCLK_RKRNG_S] = &hclk_rkrng_s, + [CLK_PKA_RKCE_S] = &clk_pka_rkce_s, + [ACLK_RKCE_S] = &aclk_rkce_s, +}; + +size_t rockchip_scmi_clock_count(unsigned int agent_id __unused) +{ + return CLK_NR_CLKS; +} + +rk_scmi_clock_t *rockchip_scmi_get_clock(uint32_t agent_id __unused, + uint32_t clock_id) +{ + rk_scmi_clock_t *table = NULL; + + if (clock_id < ARRAY_SIZE(clock_table)) { + table = clock_table[clock_id]; + if (table == NULL) + return NULL; + } + + if ((table != NULL) && (table->is_security == 0)) + return table; + else + return NULL; + + return NULL; +} + +void rockchip_clock_init(void) +{ + /* disable aclk_rkce_s_en and clk_pka_rkce_s_en */ + mmio_write_32(0x20200808, 0x30003000); +} diff --git a/plat/rockchip/rv1126b/scmi/rv1126b_clk.h b/plat/rockchip/rv1126b/scmi/rv1126b_clk.h new file mode 100644 index 000000000..de99bd8eb --- /dev/null +++ b/plat/rockchip/rv1126b/scmi/rv1126b_clk.h @@ -0,0 +1,794 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2026, Rockchip Electronics Co., Ltd. + */ + +#ifndef _CLOCK_H +#define _CLOCK_H + +/* pll clocks */ +#define PLL_GPLL 1 +#define PLL_CPLL 2 +#define PLL_AUPLL 3 +#define ARMCLK 4 +#define SCLK_DDR 5 + +/* clk (clocks) */ +#define CLK_CPLL_DIV20 8 +#define CLK_CPLL_DIV10 9 +#define CLK_CPLL_DIV8 10 +#define CLK_GPLL_DIV8 11 +#define CLK_GPLL_DIV6 12 +#define CLK_GPLL_DIV4 13 +#define CLK_CPLL_DIV3 14 +#define CLK_GPLL_DIV3 15 +#define CLK_CPLL_DIV2 16 +#define CLK_GPLL_DIV2 17 +#define CLK_CM_FRAC0 18 +#define CLK_CM_FRAC1 19 +#define CLK_CM_FRAC2 20 +#define CLK_UART_FRAC0 21 +#define CLK_UART_FRAC1 22 +#define CLK_AUDIO_FRAC0 23 +#define CLK_AUDIO_FRAC1 24 +#define CLK_AUDIO_INT0 25 +#define CLK_AUDIO_INT1 26 +#define SCLK_UART0_SRC 27 +#define SCLK_UART1 28 +#define SCLK_UART2 29 +#define SCLK_UART3 30 +#define SCLK_UART4 31 +#define SCLK_UART5 32 +#define SCLK_UART6 33 +#define SCLK_UART7 34 +#define MCLK_SAI0 35 +#define MCLK_SAI1 36 +#define MCLK_SAI2 37 +#define MCLK_PDM 38 +#define CLKOUT_PDM 39 +#define MCLK_ASRC0 40 +#define MCLK_ASRC1 41 +#define MCLK_ASRC2 42 +#define MCLK_ASRC3 43 +#define CLK_ASRC0 44 +#define CLK_ASRC1 45 +#define CLK_CORE_PLL 46 +#define CLK_NPU_PLL 47 +#define CLK_VEPU_PLL 48 +#define CLK_ISP_PLL 49 +#define CLK_AISP_PLL 50 +#define CLK_SARADC0_SRC 51 +#define CLK_SARADC1_SRC 52 +#define CLK_SARADC2_SRC 53 +#define HCLK_NPU_ROOT 54 +#define PCLK_NPU_ROOT 55 +#define ACLK_VEPU_ROOT 56 +#define HCLK_VEPU_ROOT 57 +#define PCLK_VEPU_ROOT 58 +#define CLK_CORE_RGA_SRC 59 +#define ACLK_GMAC_ROOT 60 +#define ACLK_VI_ROOT 61 +#define HCLK_VI_ROOT 62 +#define PCLK_VI_ROOT 63 +#define DCLK_VICAP_ROOT 64 +#define CLK_SYS_DSMC_ROOT 65 +#define ACLK_VDO_ROOT 66 +#define ACLK_RKVDEC_ROOT 67 +#define HCLK_VDO_ROOT 68 +#define PCLK_VDO_ROOT 69 +#define DCLK_OOC_SRC 70 +#define DCLK_VOP 71 +#define DCLK_DECOM_SRC 72 +#define PCLK_DDR_ROOT 73 +#define ACLK_SYSMEM_SRC 74 +#define ACLK_TOP_ROOT 75 +#define ACLK_BUS_ROOT 76 +#define HCLK_BUS_ROOT 77 +#define PCLK_BUS_ROOT 78 +#define CCLK_SDMMC0 79 +#define CCLK_SDMMC1 80 +#define CCLK_EMMC 81 +#define SCLK_2X_FSPI0 82 +#define CLK_GMAC_PTP_REF_SRC 83 +#define CLK_GMAC_125M 84 +#define CLK_TIMER_ROOT 85 +#define TCLK_WDT_NS_SRC 86 +#define TCLK_WDT_S_SRC 87 +#define TCLK_WDT_HPMCU 88 +#define CLK_CAN0 89 +#define CLK_CAN1 90 +#define PCLK_PERI_ROOT 91 +#define ACLK_PERI_ROOT 92 +#define CLK_I2C_BUS_SRC 93 +#define CLK_SPI0 94 +#define CLK_SPI1 95 +#define BUSCLK_PMU_SRC 96 +#define CLK_PWM0 97 +#define CLK_PWM2 98 +#define CLK_PWM3 99 +#define CLK_PKA_RKCE_SRC 100 +#define ACLK_RKCE_SRC 101 +#define ACLK_VCP_ROOT 102 +#define HCLK_VCP_ROOT 103 +#define PCLK_VCP_ROOT 104 +#define CLK_CORE_FEC_SRC 105 +#define CLK_CORE_AVSP_SRC 106 +#define CLK_50M_GMAC_IOBUF_VI 107 +#define PCLK_TOP_ROOT 108 +#define CLK_MIPI0_OUT2IO 109 +#define CLK_MIPI1_OUT2IO 110 +#define CLK_MIPI2_OUT2IO 111 +#define CLK_MIPI3_OUT2IO 112 +#define CLK_CIF_OUT2IO 113 +#define CLK_MAC_OUT2IO 114 +#define MCLK_SAI0_OUT2IO 115 +#define MCLK_SAI1_OUT2IO 116 +#define MCLK_SAI2_OUT2IO 117 +#define CLK_CM_FRAC0_SRC 118 +#define CLK_CM_FRAC1_SRC 119 +#define CLK_CM_FRAC2_SRC 120 +#define CLK_UART_FRAC0_SRC 121 +#define CLK_UART_FRAC1_SRC 122 +#define CLK_AUDIO_FRAC0_SRC 123 +#define CLK_AUDIO_FRAC1_SRC 124 +#define ACLK_NPU_ROOT 125 +#define HCLK_RKNN 126 +#define ACLK_RKNN 127 +#define PCLK_GPIO3 128 +#define DBCLK_GPIO3 129 +#define PCLK_IOC_VCCIO3 130 +#define PCLK_SARADC0 131 +#define CLK_SARADC0 132 +#define HCLK_SDMMC1 133 +#define HCLK_VEPU 134 +#define ACLK_VEPU 135 +#define CLK_CORE_VEPU 136 +#define HCLK_FEC 137 +#define ACLK_FEC 138 +#define CLK_CORE_FEC 139 +#define HCLK_AVSP 140 +#define ACLK_AVSP 141 +#define BUSCLK_PMU1_ROOT 142 +#define HCLK_AISP 143 +#define ACLK_AISP 144 +#define CLK_CORE_AISP 145 +#define CLK_CORE_ISP_ROOT 146 +#define PCLK_DSMC 147 +#define ACLK_DSMC 148 +#define HCLK_CAN0 149 +#define HCLK_CAN1 150 +#define PCLK_GPIO2 151 +#define DBCLK_GPIO2 152 +#define PCLK_GPIO4 153 +#define DBCLK_GPIO4 154 +#define PCLK_GPIO5 155 +#define DBCLK_GPIO5 156 +#define PCLK_GPIO6 157 +#define DBCLK_GPIO6 158 +#define PCLK_GPIO7 159 +#define DBCLK_GPIO7 160 +#define PCLK_IOC_VCCIO2 161 +#define PCLK_IOC_VCCIO4 162 +#define PCLK_IOC_VCCIO5 163 +#define PCLK_IOC_VCCIO6 164 +#define PCLK_IOC_VCCIO7 165 +#define HCLK_ISP 166 +#define ACLK_ISP 167 +#define CLK_CORE_ISP 168 +#define HCLK_VICAP 169 +#define ACLK_VICAP 170 +#define DCLK_VICAP 171 +#define ISP0CLK_VICAP 172 +#define HCLK_VPSS 173 +#define ACLK_VPSS 174 +#define CLK_CORE_VPSS 175 +#define PCLK_CSI2HOST0 176 +#define DCLK_CSI2HOST0 177 +#define PCLK_CSI2HOST1 178 +#define DCLK_CSI2HOST1 179 +#define PCLK_CSI2HOST2 180 +#define DCLK_CSI2HOST2 181 +#define PCLK_CSI2HOST3 182 +#define DCLK_CSI2HOST3 183 +#define HCLK_SDMMC0 184 +#define ACLK_GMAC 185 +#define PCLK_GMAC 186 +#define CLK_GMAC_PTP_REF 187 +#define PCLK_CSIPHY0 188 +#define PCLK_CSIPHY1 189 +#define PCLK_MACPHY 190 +#define PCLK_SARADC1 191 +#define CLK_SARADC1 192 +#define PCLK_SARADC2 193 +#define CLK_SARADC2 194 +#define ACLK_RKVDEC 195 +#define HCLK_RKVDEC 196 +#define CLK_HEVC_CA_RKVDEC 197 +#define ACLK_VOP 198 +#define HCLK_VOP 199 +#define HCLK_RKJPEG 200 +#define ACLK_RKJPEG 201 +#define ACLK_RKMMU_DECOM 202 +#define HCLK_RKMMU_DECOM 203 +#define DCLK_DECOM 204 +#define ACLK_DECOM 205 +#define PCLK_DECOM 206 +#define PCLK_MIPI_DSI 207 +#define PCLK_DSIPHY 208 +#define ACLK_OOC 209 +#define ACLK_SYSMEM 210 +#define PCLK_DDRC 211 +#define PCLK_DDRMON 212 +#define CLK_TIMER_DDRMON 213 +#define PCLK_DFICTRL 214 +#define PCLK_DDRPHY 215 +#define PCLK_DMA2DDR 216 +#define CLK_RCOSC_SRC 217 +#define BUSCLK_PMU_MUX 218 +#define BUSCLK_PMU_ROOT 219 +#define PCLK_PMU 220 +#define CLK_XIN_RC_DIV 221 +#define CLK_32K 222 +#define PCLK_PMU_GPIO0 223 +#define DBCLK_PMU_GPIO0 224 +#define PCLK_PMU_HP_TIMER 225 +#define CLK_PMU_HP_TIMER 226 +#define CLK_PMU_32K_HP_TIMER 227 +#define PCLK_PWM1 228 +#define CLK_PWM1 229 +#define CLK_OSC_PWM1 230 +#define CLK_RC_PWM1 231 +#define CLK_FREQ_PWM1 232 +#define CLK_COUNTER_PWM1 233 +#define PCLK_I2C2 234 +#define CLK_I2C2 235 +#define PCLK_UART0 236 +#define SCLK_UART0 237 +#define PCLK_RCOSC_CTRL 238 +#define CLK_OSC_RCOSC_CTRL 239 +#define CLK_REF_RCOSC_CTRL 240 +#define PCLK_IOC_PMUIO0 241 +#define CLK_REFOUT 242 +#define CLK_PREROLL 243 +#define CLK_PREROLL_32K 244 +#define HCLK_PMU_SRAM 245 +#define PCLK_WDT_LPMCU 246 +#define TCLK_WDT_LPMCU 247 +#define CLK_LPMCU 248 +#define CLK_LPMCU_RTC 249 +#define PCLK_LPMCU_MAILBOX 250 +#define HCLK_OOC 251 +#define PCLK_SPI2AHB 252 +#define HCLK_SPI2AHB 253 +#define HCLK_FSPI1 254 +#define HCLK_XIP_FSPI1 255 +#define SCLK_1X_FSPI1 256 +#define PCLK_IOC_PMUIO1 257 +#define PCLK_AUDIO_ADC_PMU 258 +#define MCLK_AUDIO_ADC_PMU 259 +#define MCLK_AUDIO_ADC_DIV4_PMU 260 +#define MCLK_LPSAI 261 +#define ACLK_GIC400 262 +#define PCLK_WDT_NS 263 +#define TCLK_WDT_NS 264 +#define PCLK_WDT_HPMCU 265 +#define HCLK_CACHE 266 +#define PCLK_HPMCU_MAILBOX 267 +#define PCLK_HPMCU_INTMUX 268 +#define CLK_HPMCU 269 +#define CLK_HPMCU_RTC 270 +#define PCLK_RKDMA 271 +#define ACLK_RKDMA 272 +#define PCLK_DCF 273 +#define ACLK_DCF 274 +#define HCLK_RGA 275 +#define ACLK_RGA 276 +#define CLK_CORE_RGA 277 +#define PCLK_TIMER 278 +#define CLK_TIMER0 279 +#define CLK_TIMER1 280 +#define CLK_TIMER2 281 +#define CLK_TIMER3 282 +#define CLK_TIMER4 283 +#define CLK_TIMER5 284 +#define PCLK_I2C0 285 +#define CLK_I2C0 286 +#define PCLK_I2C1 287 +#define CLK_I2C1 288 +#define PCLK_I2C3 289 +#define CLK_I2C3 290 +#define PCLK_I2C4 291 +#define CLK_I2C4 292 +#define PCLK_I2C5 293 +#define CLK_I2C5 294 +#define PCLK_SPI0 295 +#define PCLK_SPI1 296 +#define PCLK_PWM0 297 +#define CLK_OSC_PWM0 298 +#define CLK_RC_PWM0 299 +#define PCLK_PWM2 300 +#define CLK_OSC_PWM2 301 +#define CLK_RC_PWM2 302 +#define PCLK_PWM3 303 +#define CLK_OSC_PWM3 304 +#define CLK_RC_PWM3 305 +#define PCLK_UART1 306 +#define PCLK_UART2 307 +#define PCLK_UART3 308 +#define PCLK_UART4 309 +#define PCLK_UART5 310 +#define PCLK_UART6 311 +#define PCLK_UART7 312 +#define PCLK_TSADC 313 +#define CLK_TSADC 314 +#define HCLK_SAI0 315 +#define HCLK_SAI1 316 +#define HCLK_SAI2 317 +#define HCLK_RKDSM 318 +#define MCLK_RKDSM 319 +#define HCLK_PDM 320 +#define HCLK_ASRC0 321 +#define HCLK_ASRC1 322 +#define PCLK_AUDIO_ADC_BUS 323 +#define MCLK_AUDIO_ADC_BUS 324 +#define MCLK_AUDIO_ADC_DIV4_BUS 325 +#define PCLK_RKCE 326 +#define HCLK_NS_RKCE 327 +#define PCLK_OTPC_NS 328 +#define CLK_SBPI_OTPC_NS 329 +#define CLK_USER_OTPC_NS 330 +#define CLK_OTPC_ARB 331 +#define PCLK_OTP_MASK 332 +#define CLK_TSADC_PHYCTRL 333 +#define LRCK_SRC_ASRC0 334 +#define LRCK_DST_ASRC0 335 +#define LRCK_SRC_ASRC1 336 +#define LRCK_DST_ASRC1 337 +#define PCLK_KEY_READER 338 +#define ACLK_NSRKCE 339 +#define CLK_PKA_NSRKCE 340 +#define PCLK_RTC_ROOT 341 +#define PCLK_GPIO1 342 +#define DBCLK_GPIO1 343 +#define PCLK_IOC_VCCIO1 344 +#define ACLK_USB3OTG 345 +#define CLK_REF_USB3OTG 346 +#define CLK_SUSPEND_USB3OTG 347 +#define HCLK_USB2HOST 348 +#define HCLK_ARB_USB2HOST 349 +#define PCLK_RTC_TEST 350 +#define HCLK_EMMC 351 +#define HCLK_FSPI0 352 +#define HCLK_XIP_FSPI0 353 +#define PCLK_PIPEPHY 354 +#define PCLK_USB2PHY 355 +#define CLK_REF_PIPEPHY_CPLL_SRC 356 +#define CLK_REF_PIPEPHY 357 +#define HCLK_VPSL 358 +#define ACLK_VPSL 359 +#define CLK_CORE_VPSL 360 +#define CLK_MACPHY 361 +#define HCLK_RKRNG_NS 362 +#define HCLK_RKRNG_S_NS 362 + +/* secure clks */ +#define CLK_USER_OTPC_S 400 +#define CLK_SBPI_OTPC_S 401 +#define PCLK_OTPC_S 402 +#define PCLK_KEY_READER_S 403 +#define HCLK_KL_RKCE_S 404 +#define HCLK_RKCE_S 405 +#define PCLK_WDT_S 406 +#define TCLK_WDT_S 407 +#define CLK_STIMER0 408 +#define CLK_STIMER1 409 +#define PLK_STIMER 410 +#define HCLK_RKRNG_S 411 +#define CLK_PKA_RKCE_S 412 +#define ACLK_RKCE_S 413 + +#define CLK_NR_CLKS (ACLK_RKCE_S + 1) + +/* TOPCRU_SOFTRST_CON15(Offset:0xA3C) */ +#define SRST_PRESETN_CRU 0x000000F1 +#define SRST_PRESETN_CRU_BIU 0x000000F2 + +/* BUSCRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_ARESETN_TOP_BIU 0x00040000 +#define SRST_ARESETN_RKCE_BIU 0x00040001 +#define SRST_ARESETN_BUS_BIU 0x00040002 +#define SRST_HRESETN_BUS_BIU 0x00040003 +#define SRST_PRESETN_BUS_BIU 0x00040004 +#define SRST_PRESETN_CRU_BUS 0x00040005 +#define SRST_PRESETN_SYS_GRF 0x00040006 +#define SRST_HRESETN_BOOTROM 0x00040007 +#define SRST_ARESETN_GIC400 0x00040008 +#define SRST_ARESETN_SPINLOCK 0x00040009 +#define SRST_PRESETN_WDT_NS 0x0004000A +#define SRST_TRESETN_WDT_NS 0x0004000B + +/* BUSCRU_SOFTRST_CON01(Offset:0xA04) */ +#define SRST_PRESETN_WDT_HPMCU 0x00040010 +#define SRST_TRESETN_WDT_HPMCU 0x00040011 +#define SRST_HRESETN_CACHE 0x00040012 +#define SRST_PRESETN_HPMCU_MAILBOX 0x00040013 +#define SRST_PRESETN_HPMCU_INTMUX 0x00040014 +#define SRST_RESETN_HPMCU_FULL_CLUSTER 0x00040015 +#define SRST_RESETN_HPMCU_PWUP 0x00040016 +#define SRST_RESETN_HPMCU_ONLY_CORE 0x00040017 +#define SRST_TRESETN_HPMCU_JTAG 0x00040018 +#define SRST_PRESETN_RKDMA 0x0004001B +#define SRST_ARESETN_RKDMA 0x0004001C + +/* BUSCRU_SOFTRST_CON02(Offset:0xA08) */ +#define SRST_PRESETN_DCF 0x00040020 +#define SRST_ARESETN_DCF 0x00040021 +#define SRST_HRESETN_RGA 0x00040022 +#define SRST_ARESETN_RGA 0x00040023 +#define SRST_RESETN_CORE_RGA 0x00040024 +#define SRST_PRESETN_TIMER 0x00040025 +#define SRST_RESETN_TIMER0 0x00040026 +#define SRST_RESETN_TIMER1 0x00040027 +#define SRST_RESETN_TIMER2 0x00040028 +#define SRST_RESETN_TIMER3 0x00040029 +#define SRST_RESETN_TIMER4 0x0004002A +#define SRST_RESETN_TIMER5 0x0004002B +#define SRST_ARESETN_RKCE 0x0004002C +#define SRST_RESETN_PKA_RKCE 0x0004002D +#define SRST_HRESETN_RKRNG_S 0x0004002E +#define SRST_HRESETN_RKRNG_NS 0x0004002F + +/* BUSCRU_SOFTRST_CON03(Offset:0xA0C) */ +#define SRST_PRESETN_I2C0 0x00040030 +#define SRST_RESETN_I2C0 0x00040031 +#define SRST_PRESETN_I2C1 0x00040032 +#define SRST_RESETN_I2C1 0x00040033 +#define SRST_PRESETN_I2C3 0x00040034 +#define SRST_RESETN_I2C3 0x00040035 +#define SRST_PRESETN_I2C4 0x00040036 +#define SRST_RESETN_I2C4 0x00040037 +#define SRST_PRESETN_I2C5 0x00040038 +#define SRST_RESETN_I2C5 0x00040039 +#define SRST_PRESETN_SPI0 0x0004003A +#define SRST_RESETN_SPI0 0x0004003B +#define SRST_PRESETN_SPI1 0x0004003C +#define SRST_RESETN_SPI1 0x0004003D + +/* BUSCRU_SOFTRST_CON04(Offset:0xA10) */ +#define SRST_PRESETN_PWM0 0x00040040 +#define SRST_RESETN_PWM0 0x00040041 +#define SRST_PRESETN_PWM2 0x00040044 +#define SRST_RESETN_PWM2 0x00040045 +#define SRST_PRESETN_PWM3 0x00040048 +#define SRST_RESETN_PWM3 0x00040049 + +/* BUSCRU_SOFTRST_CON05(Offset:0xA14) */ +#define SRST_PRESETN_UART1 0x00040050 +#define SRST_SRESETN_UART1 0x00040051 +#define SRST_PRESETN_UART2 0x00040052 +#define SRST_SRESETN_UART2 0x00040053 +#define SRST_PRESETN_UART3 0x00040054 +#define SRST_SRESETN_UART3 0x00040055 +#define SRST_PRESETN_UART4 0x00040056 +#define SRST_SRESETN_UART4 0x00040057 +#define SRST_PRESETN_UART5 0x00040058 +#define SRST_SRESETN_UART5 0x00040059 +#define SRST_PRESETN_UART6 0x0004005A +#define SRST_SRESETN_UART6 0x0004005B +#define SRST_PRESETN_UART7 0x0004005C +#define SRST_SRESETN_UART7 0x0004005D + +/* BUSCRU_SOFTRST_CON06(Offset:0xA18) */ +#define SRST_PRESETN_TSADC 0x00040060 +#define SRST_RESETN_TSADC 0x00040061 +#define SRST_HRESETN_SAI0 0x00040062 +#define SRST_MRESETN_SAI0 0x00040063 +#define SRST_HRESETN_SAI1 0x00040064 +#define SRST_MRESETN_SAI1 0x00040065 +#define SRST_HRESETN_SAI2 0x00040066 +#define SRST_MRESETN_SAI2 0x00040067 +#define SRST_HRESETN_RKDSM 0x00040068 +#define SRST_MRESETN_RKDSM 0x00040069 +#define SRST_HRESETN_PDM 0x0004006A +#define SRST_MRESETN_PDM 0x0004006B +#define SRST_RESETN_PDM 0x0004006C + +/* BUSCRU_SOFTRST_CON07(Offset:0xA1C) */ +#define SRST_HRESETN_ASRC0 0x00040070 +#define SRST_RESETN_ASRC0 0x00040071 +#define SRST_HRESETN_ASRC1 0x00040072 +#define SRST_RESETN_ASRC1 0x00040073 +#define SRST_PRESETN_AUDIO_ADC_BUS 0x00040074 +#define SRST_MRESETN_AUDIO_ADC_BUS 0x00040075 +#define SRST_PRESETN_RKCE 0x00040076 +#define SRST_HRESETN_NS_RKCE 0x00040077 +#define SRST_PRESETN_OTPC_NS 0x00040078 +#define SRST_RESETN_SBPI_OTPC_NS 0x00040079 +#define SRST_RESETN_USER_OTPC_NS 0x0004007A +#define SRST_RESETN_OTPC_ARB 0x0004007B +#define SRST_PRESETN_OTP_MASK 0x0004007C +#define SRST_RESETN_TSADC_PHYCTRL 0x0004007E + +/* PERICRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_ARESETN_PERI_BIU 0x00080000 +#define SRST_PRESETN_PERI_BIU 0x00080001 +#define SRST_PRESETN_RTC_BIU 0x00080002 +#define SRST_PRESETN_CRU_PERI 0x00080003 +#define SRST_PRESETN_PERI_GRF 0x00080004 +#define SRST_PRESETN_GPIO1 0x00080005 +#define SRST_DBRESETN_GPIO1 0x00080006 +#define SRST_PRESETN_IOC_VCCIO1 0x00080007 +#define SRST_ARESETN_USB3OTG 0x00080008 +#define SRST_HRESETN_USB2HOST 0x0008000B +#define SRST_HRESETN_ARB_USB2HOST 0x0008000C +#define SRST_PRESETN_RTC_TEST 0x0008000D + +/* PERICRU_SOFTRST_CON01(Offset:0xA04) */ +#define SRST_HRESETN_EMMC 0x00080010 +#define SRST_HRESETN_FSPI0 0x00080011 +#define SRST_HRESETN_XIP_FSPI0 0x00080012 +#define SRST_SRESETN_2X_FSPI0 0x00080013 +#define SRST_RESETN_UTMI_USB2HOST 0x00080015 +#define SRST_RESETN_REF_PIPEPHY 0x00080017 +#define SRST_PRESETN_PIPEPHY 0x00080018 +#define SRST_PRESETN_PIPEPHY_GRF 0x00080019 +#define SRST_PRESETN_USB2PHY 0x0008001A +#define SRST_RESETN_POR_USB2PHY 0x0008001B +#define SRST_RESETN_OTG_USB2PHY 0x0008001C +#define SRST_RESETN_HOST_USB2PHY 0x0008001D + +/* CORECRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_RESETN_REF_PVTPLL_CORE 0x000C0000 +#define SRST_NCOREPORESET0 0x000C0001 +#define SRST_NCORESET0 0x000C0002 +#define SRST_NCOREPORESET1 0x000C0003 +#define SRST_NCORESET1 0x000C0004 +#define SRST_NCOREPORESET2 0x000c0005 +#define SRST_NCORESET2 0x000C0006 +#define SRST_NCOREPORESET3 0x000C0007 +#define SRST_NCORESET3 0x000C0008 +#define SRST_NDBGRESET 0x000C0009 +#define SRST_NL2RESET 0x000C000A + +/* CORECRU_SOFTRST_CON01(Offset:0xA04) */ +#define SRST_ARESETN_CORE_BIU 0x000C0010 +#define SRST_PRESETN_CORE_BIU 0x000C0011 +#define SRST_HRESETN_CORE_BIU 0x000C0012 +#define SRST_PRESETN_DBG 0x000C0013 +#define SRST_POTRESETN_DBG 0x000C0014 +#define SRST_NTRESETN_DBG 0x000C0015 +#define SRST_PRESETN_CORE_PVTPLL 0x000C0016 +#define SRST_PRESETN_CRU_CORE 0x000C0017 +#define SRST_PRESETN_CORE_GRF 0x000C0018 +#define SRST_PRESETN_DFT2APB 0x000C001A + +/* PMUCRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_HRESETN_PMU_BIU 0x00100000 +#define SRST_PRESETN_PMU_GPIO0 0x00100007 +#define SRST_DBRESETN_PMU_GPIO0 0x00100008 +#define SRST_PRESETN_PMU_HP_TIMER 0x0010000A +#define SRST_RESETN_PMU_HP_TIMER 0x0010000B +#define SRST_RESETN_PMU_32K_HP_TIMER 0x0010000C + +/* PMUCRU_SOFTRST_CON01(Offset:0xA04) */ +#define SRST_PRESETN_PWM1 0x00100010 +#define SRST_RESETN_PWM1 0x00100011 +#define SRST_PRESETN_I2C2 0x00100012 +#define SRST_RESETN_I2C2 0x00100013 +#define SRST_PRESETN_UART0 0x00100014 +#define SRST_SRESETN_UART0 0x00100015 + +/* PMUCRU_SOFTRST_CON02(Offset:0xA08) */ +#define SRST_PRESETN_RCOSC_CTRL 0x00100020 +#define SRST_RESETN_REF_RCOSC_CTRL 0x00100022 +#define SRST_PRESETN_IOC_PMUIO0 0x00100023 +#define SRST_PRESETN_CRU_PMU 0x00100024 +#define SRST_PRESETN_PMU_GRF 0x00100025 +#define SRST_RESETN_PREROLL 0x00100027 +#define SRST_RESETN_PREROLL_32K 0x00100028 +#define SRST_HRESETN_PMU_SRAM 0x00100029 + +/* PMUCRU_SOFTRST_CON03(Offset:0xA0C) */ +#define SRST_PRESETN_WDT_LPMCU 0x00100030 +#define SRST_TRESETN_WDT_LPMCU 0x00100031 +#define SRST_RESETN_LPMCU_FULL_CLUSTER 0x00100032 +#define SRST_RESETN_LPMCU_PWUP 0x00100033 +#define SRST_RESETN_LPMCU_ONLY_CORE 0x00100034 +#define SRST_TRESETN_LPMCU_JTAG 0x00100035 +#define SRST_PRESETN_LPMCU_MAILBOX 0x00100036 + +/* PMU1CRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_PRESETN_SPI2AHB 0x00140000 +#define SRST_HRESETN_SPI2AHB 0x00140001 +#define SRST_HRESETN_FSPI1 0x00140002 +#define SRST_HRESETN_XIP_FSPI1 0x00140003 +#define SRST_SRESETN_1X_FSPI1 0x00140004 +#define SRST_PRESETN_IOC_PMUIO1 0x00140005 +#define SRST_PRESETN_CRU_PMU1 0x00140006 +#define SRST_PRESETN_AUDIO_ADC_PMU 0x00140007 +#define SRST_MRESETN_AUDIO_ADC_PMU 0x00140008 +#define SRST_HRESETN_PMU1_BIU 0x00140009 + +/* PMU1CRU_SOFTRST_CON01(Offset:0xA04) */ +#define SRST_PRESETN_LPDMA 0x00140010 +#define SRST_ARESETN_LPDMA 0x00140011 +#define SRST_HRESETN_LPSAI 0x00140012 +#define SRST_MRESETN_LPSAI 0x00140013 +#define SRST_PRESETN_AOA_TDD 0x00140014 +#define SRST_PRESETN_AOA_FE 0x00140015 +#define SRST_PRESETN_AOA_AAD 0x00140016 +#define SRST_PRESETN_AOA_APB 0x00140017 +#define SRST_PRESETN_AOA_SRAM 0x00140018 + +/* DDRCRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_PRESETN_DDR_BIU 0x00180001 +#define SRST_PRESETN_DDRC 0x00180002 +#define SRST_PRESETN_DDRMON 0x00180003 +#define SRST_RESETN_TIMER_DDRMON 0x00180004 +#define SRST_PRESETN_DFICTRL 0x00180005 +#define SRST_PRESETN_DDR_GRF 0x00180006 +#define SRST_PRESETN_CRU_DDR 0x00180007 +#define SRST_PRESETN_DDRPHY 0x00180008 +#define SRST_PRESETN_DMA2DDR 0x00180009 + +/* SUBDDRCRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_ARESETN_SYSMEM_BIU 0x001A0000 +#define SRST_ARESETN_SYSMEM 0x001A0001 +#define SRST_ARESETN_DDR_BIU 0x001A0002 +#define SRST_ARESETN_DDRSCH0_CPU 0x001A0003 +#define SRST_ARESETN_DDRSCH1_NPU 0x001A0004 +#define SRST_ARESETN_DDRSCH2_POE 0x001A0005 +#define SRST_ARESETN_DDRSCH3_VI 0x001A0006 +#define SRST_RESETN_CORE_DDRC 0x001A0007 +#define SRST_RESETN_DDRMON 0x001A0008 +#define SRST_RESETN_DFICTRL 0x001A0009 +#define SRST_RESETN_RS 0x001A000B +#define SRST_ARESETN_DMA2DDR 0x001A000C +#define SRST_RESETN_DDRPHY 0x001A000D + +/* VICRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_RESETN_REF_PVTPLL_ISP 0x001C0000 +#define SRST_ARESETN_GMAC_BIU 0x001C0001 +#define SRST_ARESETN_VI_BIU 0x001C0002 +#define SRST_HRESETN_VI_BIU 0x001C0003 +#define SRST_PRESETN_VI_BIU 0x001C0004 +#define SRST_PRESETN_CRU_VI 0x001C0005 +#define SRST_PRESETN_VI_GRF 0x001C0006 +#define SRST_PRESETN_VI_PVTPLL 0x001C0007 +#define SRST_PRESETN_DSMC 0x001C0008 +#define SRST_ARESETN_DSMC 0x001C0009 +#define SRST_HRESETN_CAN0 0x001C000A +#define SRST_RESETN_CAN0 0x001C000B +#define SRST_HRESETN_CAN1 0x001C000C +#define SRST_RESETN_CAN1 0x001C000D + +/* VICRU_SOFTRST_CON01(Offset:0xA04) */ +#define SRST_PRESETN_GPIO2 0x001C0010 +#define SRST_DBRESETN_GPIO2 0x001C0011 +#define SRST_PRESETN_GPIO4 0x001C0012 +#define SRST_DBRESETN_GPIO4 0x001C0013 +#define SRST_PRESETN_GPIO5 0x001C0014 +#define SRST_DBRESETN_GPIO5 0x001C0015 +#define SRST_PRESETN_GPIO6 0x001C0016 +#define SRST_DBRESETN_GPIO6 0x001C0017 +#define SRST_PRESETN_GPIO7 0x001C0018 +#define SRST_DBRESETN_GPIO7 0x001C0019 +#define SRST_PRESETN_IOC_VCCIO2 0x001C001A +#define SRST_PRESETN_IOC_VCCIO4 0x001C001B +#define SRST_PRESETN_IOC_VCCIO5 0x001C001C +#define SRST_PRESETN_IOC_VCCIO6 0x001C001D +#define SRST_PRESETN_IOC_VCCIO7 0x001C001E + +/* VICRU_SOFTRST_CON02(Offset:0xA08) */ +#define SRST_RESETN_CORE_ISP 0x001C0020 +#define SRST_HRESETN_VICAP 0x001C0021 +#define SRST_ARESETN_VICAP 0x001C0022 +#define SRST_DRESETN_VICAP 0x001C0023 +#define SRST_ISP0RESETN_VICAP 0x001C0024 +#define SRST_RESETN_CORE_VPSS 0x001C0025 +#define SRST_RESETN_CORE_VPSL 0x001C0026 +#define SRST_PRESETN_CSI2HOST0 0x001C0027 +#define SRST_PRESETN_CSI2HOST1 0x001C0028 +#define SRST_PRESETN_CSI2HOST2 0x001C0029 +#define SRST_PRESETN_CSI2HOST3 0x001C002A +#define SRST_HRESETN_SDMMC0 0x001C002B +#define SRST_ARESETN_GMAC 0x001C002C +#define SRST_PRESETN_CSIPHY0 0x001C002D +#define SRST_PRESETN_CSIPHY1 0x001C002E + +/* VICRU_SOFTRST_CON03(Offset:0xA0C) */ +#define SRST_PRESETN_MACPHY 0x001C0030 +#define SRST_RESETN_MACPHY 0x001C0031 +#define SRST_PRESETN_SARADC1 0x001C0032 +#define SRST_RESETN_SARADC1 0x001C0033 +#define SRST_RESETN_SARADC1_PHY 0x001C0034 +#define SRST_PRESETN_SARADC2 0x001C0035 +#define SRST_RESETN_SARADC2 0x001C0036 +#define SRST_RESETN_SARADC2_PHY 0x001C0037 + +/* VEPUCRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_RESETN_REF_PVTPLL_VEPU 0x00200000 +#define SRST_ARESETN_VEPU_BIU 0x00200001 +#define SRST_HRESETN_VEPU_BIU 0x00200002 +#define SRST_PRESETN_VEPU_BIU 0x00200003 +#define SRST_PRESETN_CRU_VEPU 0x00200004 +#define SRST_PRESETN_VEPU_GRF 0x00200005 +#define SRST_PRESETN_GPIO3 0x00200007 +#define SRST_DBRESETN_GPIO3 0x00200008 +#define SRST_PRESETN_IOC_VCCIO3 0x00200009 +#define SRST_PRESETN_SARADC0 0x0020000A +#define SRST_RESETN_SARADC0 0x0020000B +#define SRST_RESETN_SARADC0_PHY 0x0020000C +#define SRST_HRESETN_SDMMC1 0x0020000D + +/* VEPUCRU_SOFTRST_CON01(Offset:0xA04) */ +#define SRST_PRESETN_VEPU_PVTPLL 0x00200010 +#define SRST_HRESETN_VEPU 0x00200011 +#define SRST_ARESETN_VEPU 0x00200012 +#define SRST_RESETN_CORE_VEPU 0x00200013 + +/* NPUCRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_RESETN_REF_PVTPLL_NPU 0x00240000 +#define SRST_ARESETN_NPU_BIU 0x00240002 +#define SRST_HRESETN_NPU_BIU 0x00240003 +#define SRST_PRESETN_NPU_BIU 0x00240004 +#define SRST_PRESETN_CRU_NPU 0x00240005 +#define SRST_PRESETN_NPU_GRF 0x00240006 +#define SRST_PRESETN_NPU_PVTPLL 0x00240008 +#define SRST_HRESETN_RKNN 0x00240009 +#define SRST_ARESETN_RKNN 0x0024000A + +/* VDOCRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_ARESETN_RKVDEC_BIU 0x00280000 +#define SRST_ARESETN_VDO_BIU 0x00280001 +#define SRST_HRESETN_VDO_BIU 0x00280003 +#define SRST_PRESETN_VDO_BIU 0x00280004 +#define SRST_PRESETN_CRU_VDO 0x00280005 +#define SRST_PRESETN_VDO_GRF 0x00280006 +#define SRST_ARESETN_RKVDEC 0x00280007 +#define SRST_HRESETN_RKVDEC 0x00280008 +#define SRST_RESETN_HEVC_CA_RKVDEC 0x00280009 +#define SRST_ARESETN_VOP 0x0028000A +#define SRST_HRESETN_VOP 0x0028000B +#define SRST_DRESETN_VOP 0x0028000C +#define SRST_ARESETN_OOC 0x0028000D +#define SRST_HRESETN_OOC 0x0028000E +#define SRST_DRESETN_OOC 0x0028000F + +/* VDOCRU_SOFTRST_CON01(Offset:0xA04) */ +#define SRST_HRESETN_RKJPEG 0x00280013 +#define SRST_ARESETN_RKJPEG 0x00280014 +#define SRST_ARESETN_RKMMU_DECOM 0x00280015 +#define SRST_HRESETN_RKMMU_DECOM 0x00280016 +#define SRST_DRESETN_DECOM 0x00280018 +#define SRST_ARESETN_DECOM 0x00280019 +#define SRST_PRESETN_DECOM 0x0028001A +#define SRST_PRESETN_MIPI_DSI 0x0028001C +#define SRST_PRESETN_DSIPHY 0x0028001D + +/* VCPCRU_SOFTRST_CON00(Offset:0xA00) */ +#define SRST_RESETN_REF_PVTPLL_VCP 0x002C0000 +#define SRST_ARESETN_VCP_BIU 0x002C0001 +#define SRST_HRESETN_VCP_BIU 0x002C0002 +#define SRST_PRESETN_VCP_BIU 0x002C0003 +#define SRST_PRESETN_CRU_VCP 0x002C0004 +#define SRST_PRESETN_VCP_GRF 0x002C0005 +#define SRST_PRESETN_VCP_PVTPLL 0x002C0007 +#define SRST_ARESETN_AISP_BIU 0x002C0008 +#define SRST_HRESETN_AISP_BIU 0x002C0009 +#define SRST_ARESETN_AISPMEM_BIU 0x002C000A +#define SRST_RESETN_CORE_AISP 0x002C000D +#define SRST_ARESETN_AISPMEM 0x002C000E + +/* VCPCRU_SOFTRST_CON01(Offset:0xA04) */ +#define SRST_HRESETN_FEC 0x002C0010 +#define SRST_ARESETN_FEC 0x002C0011 +#define SRST_RESETN_CORE_FEC 0x002C0012 +#define SRST_HRESETN_AVSP 0x002C0013 +#define SRST_ARESETN_AVSP 0x002C0014 + +#define CLK_NR_SRST (SRST_ARESETN_AVSP + 1) + +void rockchip_clock_init(void); + +#endif diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk index 9519087b9..3f0775c65 100644 --- a/plat/rpi/rpi4/platform.mk +++ b/plat/rpi/rpi4/platform.mk @@ -102,7 +102,6 @@ $(eval $(call add_define,RPI3_PRELOADED_DTB_BASE)) endif $(eval $(call add_define,RPI3_RUNTIME_UART)) $(eval $(call add_define,RPI3_USE_UEFI_MAP)) -$(eval $(call add_define,SMC_PCI_SUPPORT)) ifeq (${ARCH},aarch32) $(error Error: AArch32 not supported on rpi4) diff --git a/plat/rpi/rpi5/platform.mk b/plat/rpi/rpi5/platform.mk index 7346c9a44..2f6d386a0 100644 --- a/plat/rpi/rpi5/platform.mk +++ b/plat/rpi/rpi5/platform.mk @@ -101,7 +101,6 @@ $(eval $(call add_define,RPI3_PRELOADED_DTB_BASE)) endif $(eval $(call add_define,RPI3_RUNTIME_UART)) $(eval $(call add_define,RPI3_USE_UEFI_MAP)) -$(eval $(call add_define,SMC_PCI_SUPPORT)) ifeq (${ARCH},aarch32) $(error Error: AArch32 not supported on rpi5) diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c index 3c7129b70..b6f076cb3 100644 --- a/plat/st/common/stm32mp_common.c +++ b/plat/st/common/stm32mp_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -70,7 +70,14 @@ uintptr_t plat_get_ns_image_entrypoint(void) unsigned int plat_get_syscnt_freq2(void) { - return read_cntfrq_el0(); + /* + * The system counter clock will never be above 4GHz, it is usually set + * at 64MHz (HSI) at startup, and then moved to another clock with a + * lower frequency and more stable. + * It is then safe to cast the return of read_cntfrq_el0 to a 32 bit + * value to match the plat_get_syscnt_freq2 function prototype. + */ + return (unsigned int)read_cntfrq_el0(); } static uintptr_t boot_ctx_address; @@ -293,7 +300,7 @@ int stm32mp_uart_console_setup(void) reset_uart((uint32_t)dt_uart_info.reset); - clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock); + clk_rate = (uint32_t)clk_get_rate((unsigned long)dt_uart_info.clock); #endif set_console(dt_uart_info.base, clk_rate); diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index 566f48189..d20f71499 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -22,11 +22,18 @@ USE_COHERENT_MEM := 0 # Default Device tree DTB_FILE_NAME ?= stm32mp157c-ev1.dtb -TF_CFLAGS += -DSTM32MP1X - STM32MP13 ?= 0 STM32MP15 ?= 0 +STM32MP1X := 1 + +# Disable STM32MP2 flags +STM32MP21 := 0 +STM32MP23 := 0 +STM32MP25 := 0 +STM32MP2X := 0 +STM32MP_DDR_FIP_IO_STORAGE := 0 + ifeq ($(STM32MP13),1) ifeq ($(STM32MP15),1) $(error Cannot enable both flags STM32MP13 and STM32MP15) @@ -160,10 +167,16 @@ $(eval $(call assert_booleans,\ STM32MP_CRYPTO_ROM_LIB \ STM32MP_DDR_32BIT_INTERFACE \ STM32MP_DDR_DUAL_AXI_PORT \ + STM32MP_DDR_FIP_IO_STORAGE \ STM32MP_STPMIC1L \ STM32MP_USE_EXTERNAL_HEAP \ STM32MP13 \ STM32MP15 \ + STM32MP1X \ + STM32MP21 \ + STM32MP23 \ + STM32MP25 \ + STM32MP2X \ ))) $(eval $(call assert_numerics,\ @@ -191,10 +204,16 @@ $(eval $(call add_defines,\ STM32MP_CRYPTO_ROM_LIB \ STM32MP_DDR_32BIT_INTERFACE \ STM32MP_DDR_DUAL_AXI_PORT \ + STM32MP_DDR_FIP_IO_STORAGE \ STM32MP_STPMIC1L \ STM32MP_USE_EXTERNAL_HEAP \ STM32MP13 \ STM32MP15 \ + STM32MP1X \ + STM32MP21 \ + STM32MP23 \ + STM32MP25 \ + STM32MP2X \ ))) # Include paths and source files diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk index adcacb765..50e425f0e 100644 --- a/plat/st/stm32mp2/platform.mk +++ b/plat/st/stm32mp2/platform.mk @@ -35,12 +35,18 @@ ENABLE_SVE_FOR_NS := 0 # Default Device tree DTB_FILE_NAME ?= stm32mp257f-ev1.dtb -TF_CFLAGS += -DSTM32MP2X - STM32MP21 ?= 0 STM32MP23 ?= 0 STM32MP25 ?= 0 +STM32MP2X := 1 + +# Disable STM32MP1 flags +STM32MP13 := 0 +STM32MP15 := 0 +STM32MP1X := 0 +STM32MP_STPMIC1L := 0 + ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),) STM32MP21 := 1 endif @@ -156,9 +162,14 @@ $(eval $(call assert_booleans,\ STM32MP_DDR3_TYPE \ STM32MP_DDR4_TYPE \ STM32MP_LPDDR4_TYPE \ + STM32MP_STPMIC1L \ + STM32MP13 \ + STM32MP15 \ + STM32MP1X \ STM32MP21 \ STM32MP23 \ STM32MP25 \ + STM32MP2X \ STM32MP_BL33_EL1 \ ))) @@ -187,9 +198,14 @@ $(eval $(call add_defines,\ STM32MP_DDR3_TYPE \ STM32MP_DDR4_TYPE \ STM32MP_LPDDR4_TYPE \ + STM32MP_STPMIC1L \ + STM32MP13 \ + STM32MP15 \ + STM32MP1X \ STM32MP21 \ STM32MP23 \ STM32MP25 \ + STM32MP2X \ STM32MP_BL33_EL1 \ ))) diff --git a/plat/ti/common/include/ti_platform_defs.h b/plat/ti/common/include/ti_platform_defs.h index c61fccc30..f0626a10c 100644 --- a/plat/ti/common/include/ti_platform_defs.h +++ b/plat/ti/common/include/ti_platform_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2026, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2026, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ ******************************************************************************/ /* Size of cacheable stack */ -#if IMAGE_BL31 || IMAGE_BL1 +#if defined(IMAGE_BL31) || defined(IMAGE_BL1) #define PLATFORM_STACK_SIZE 0x800 #else #define PLATFORM_STACK_SIZE 0x1000 @@ -70,7 +70,7 @@ * used, choose the smallest value needed to map the required virtual addresses * for each BL stage. */ -#if IMAGE_BL1 +#ifdef IMAGE_BL1 #define MAX_XLAT_TABLES 2 #else #define MAX_XLAT_TABLES 4 diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c index 0f7d3756e..7c88eb2fc 100644 --- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c +++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c @@ -1922,6 +1922,7 @@ enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode, uint32_t flag) { uint32_t payload[PAYLOAD_ARG_CNT]; + uint32_t mode_val = 0U; enum pm_ret_status ret = PM_RET_SUCCESS; /* Check if given node ID is a PLL node */ @@ -1930,7 +1931,10 @@ enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode, } else { /* Send request to the PMU */ PM_PACK_PAYLOAD2(payload, flag, PM_PLL_GET_MODE, nid); - ret = pm_ipi_send_sync(primary_proc, payload, mode, 1); + ret = pm_ipi_send_sync(primary_proc, payload, &mode_val, 1); + if (ret == PM_RET_SUCCESS) { + *mode = (enum pm_pll_mode)mode_val; + } } return ret; diff --git a/services/std_svc/firme/firme_base_service.c b/services/std_svc/firme/firme_base_service.c index 27c414a00..347f8f980 100644 --- a/services/std_svc/firme/firme_base_service.c +++ b/services/std_svc/firme/firme_base_service.c @@ -45,6 +45,12 @@ static uint64_t firme_base_get_feat_reg_1(firme_instance_e instance) reg |= FIRME_BASE_SERVICE_GRANULE_MGMT_BIT; } + info = firme_mecid_service_get_info(); + if ((info != NULL) && + ((info->instance_support & BIT(instance)) != 0U)) { + reg |= FIRME_BASE_SERVICE_MECID_BIT; + } + return reg; } @@ -64,6 +70,9 @@ static int32_t get_firme_service_version(firme_instance_e instance, case FIRME_GRANULE_MGMT_ID: info = firme_granule_mgmt_service_get_info(); break; + case FIRME_MECID_MGMT_ID: + info = firme_mecid_service_get_info(); + break; default: return FIRME_NOT_SUPPORTED; } @@ -99,6 +108,9 @@ static int32_t get_firme_feature_reg(uint64_t *reg, firme_instance_e instance, case FIRME_GRANULE_MGMT_ID: info = firme_granule_mgmt_service_get_info(); break; + case FIRME_MECID_MGMT_ID: + info = firme_mecid_service_get_info(); + break; } if ((info != NULL) && (reg_index < info->num_feature_regs) && diff --git a/services/std_svc/firme/firme_main.c b/services/std_svc/firme/firme_main.c index c2bf33d4b..96cde89fc 100644 --- a/services/std_svc/firme/firme_main.c +++ b/services/std_svc/firme/firme_main.c @@ -29,9 +29,9 @@ static inline bool is_granule_mgmt_service_fid(uint32_t fid) { switch (fid) { case FIRME_GM_GPI_SET_FID: - case FIRME_GM_GPI_OP_CONTINUE: - case FIRME_GM_L1_GPT_CREATE: - case FIRME_GM_L1_GPT_DESTROY: + case FIRME_GM_GPI_OP_CONTINUE_FID: + case FIRME_GM_L1_GPT_CREATE_FID: + case FIRME_GM_L1_GPT_DESTROY_FID: return true; default: return false; @@ -41,10 +41,10 @@ static inline bool is_granule_mgmt_service_fid(uint32_t fid) static inline bool is_ide_key_mgmt_service_fid(uint32_t fid) { switch (fid) { - case FIRME_IDE_KEYSET_PROG: - case FIRME_IDE_KEYSET_GO: - case FIRME_IDE_KEYSET_STOP: - case FIRME_IDE_KEYSET_POLL: + case FIRME_IDE_KEYSET_PROG_FID: + case FIRME_IDE_KEYSET_GO_FID: + case FIRME_IDE_KEYSET_STOP_FID: + case FIRME_IDE_KEYSET_POLL_FID: return true; default: return false; @@ -53,7 +53,7 @@ static inline bool is_ide_key_mgmt_service_fid(uint32_t fid) static inline bool is_mecid_service_fid(uint32_t fid) { - if (fid == FIRME_MEC_REFRESH) { + if (fid == FIRME_MEC_REFRESH_FID) { return true; } else { return false; @@ -63,12 +63,12 @@ static inline bool is_mecid_service_fid(uint32_t fid) static inline bool is_attestation_service_fid(uint32_t fid) { switch (fid) { - case FIRME_ATTEST_PAT_GET: - case FIRME_ATTEST_RAK_GET: - case FIRME_ATTEST_RAT_SIGN: - case FIRME_ATTEST_PAT_EXT_CLAIMS_STAGE: - case FIRME_ATTEST_PAT_EXT_CLAIMS_CLEAR: - case FIRME_ATTEST_PAT_EXT_CLAIMS_FINALISE: + case FIRME_ATTEST_PAT_GET_FID: + case FIRME_ATTEST_RAK_GET_FID: + case FIRME_ATTEST_RAT_SIGN_FID: + case FIRME_ATTEST_PAT_EXT_CLAIMS_STAGE_FID: + case FIRME_ATTEST_PAT_EXT_CLAIMS_CLEAR_FID: + case FIRME_ATTEST_PAT_EXT_CLAIMS_FINALISE_FID: return true; default: return false; @@ -78,8 +78,8 @@ static inline bool is_attestation_service_fid(uint32_t fid) static inline bool is_integrated_device_mgmt_service_fid(uint32_t fid) { switch (fid) { - case FIRME_IDEV_OP_START: - case FIRME_IDEV_OP_CONTINUE: + case FIRME_IDEV_OP_START_FID: + case FIRME_IDEV_OP_CONTINUE_FID: return true; default: return false; @@ -99,6 +99,11 @@ static inline firme_instance_e get_instance_from_flags(uint64_t flags) panic(); } +int32_t firme_init(void) +{ + return firme_mecid_service_init(); +} + uint64_t firme_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *cookie, void *handle, uint64_t flags) { @@ -120,6 +125,9 @@ uint64_t firme_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, } else if (is_mecid_service_fid(smc_fid)) { + return firme_mecid_service_handler(instance, smc_fid, x1, x2, + x3, x4, cookie, handle, + flags); } else if (is_attestation_service_fid(smc_fid)) { diff --git a/services/std_svc/firme/firme_mecid.c b/services/std_svc/firme/firme_mecid.c new file mode 100644 index 000000000..ee26cb6cd --- /dev/null +++ b/services/std_svc/firme/firme_mecid.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2026, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> +#include <stdint.h> + +#include <arch.h> +#include <arch_features.h> +#include <services/firme_svc.h> +#include <smccc_helpers.h> + +/* Only supported ABI is MEC_REFRESH for Realm callers. */ +static firme_service_info_t mecid_info = { + .version = FIRME_VERSION(FIRME_MECID_MGMT_VERSION_MAJOR, + FIRME_MECID_MGMT_VERSION_MINOR), + .instance_support = BIT(FIRME_REALM), + .num_feature_regs = FIRME_MECID_FEATURE_REG_COUNT, + .feature_reg = { FIRME_MECID_FEAT_REG0_MEC_REFRESH_BIT, 0U }, +}; + +firme_service_info_t *firme_mecid_service_get_info(void) +{ + if (!is_feat_mec_supported()) { + return NULL; + } + + return &mecid_info; +} + +int32_t firme_mecid_service_init(void) +{ + uint64_t __maybe_unused mecid_width; + + if (is_feat_mec_supported()) { + mecid_width = (uint64_t)plat_firme_get_common_mecid_width(); + if ((mecid_width & + ~FIRME_MECID_FEAT_REG1_COMMON_MECID_WIDTH_BITS_MASK) != 0U) { + return FIRME_INVALID_PARAMETERS; + } + + mecid_info.feature_reg[1] = EXTRACT(FIRME_MECID_FEAT_REG1_COMMON_MECID_WIDTH_BITS, mecid_width); + } + + return 0; +} + +static int firme_mec_refresh(u_register_t mec_params) +{ + uint64_t common_mecid_width; + uint16_t mecid; + + /* + * Check whether FEAT_MEC is supported by the hardware. If not, return + * unknown SMC. + */ + if (!is_feat_mec_supported()) { + return FIRME_NOT_SUPPORTED; + } + + /* + * Check whether the MECID parameter fits within the common MECID width. + */ + common_mecid_width = (mecid_info.feature_reg[1] & + FIRME_MECID_FEAT_REG1_COMMON_MECID_WIDTH_BITS_MASK) + 1U; + mecid = EXTRACT(MEC_PARAM_MECID, mec_params); + + if (mecid > common_mecid_width) { + return FIRME_INVALID_PARAMETERS; + } + + return plat_firme_mec_refresh(mecid, mec_params & BIT(0)); +} + +u_register_t firme_mecid_service_handler(firme_instance_e instance, + uint32_t smc_fid, uint64_t x1, + uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, + void *handle, uint64_t flags) +{ + (void)instance; + (void)x2; + (void)x3; + (void)x4; + (void)cookie; + (void)handle; + (void)flags; + + if (smc_fid != FIRME_MEC_REFRESH_FID || instance != FIRME_REALM) { + SMC_RET1(handle, FIRME_NOT_SUPPORTED); + } + + SMC_RET1(handle, firme_mec_refresh(x1)); +} diff --git a/services/std_svc/pci_svc.c b/services/std_svc/pci_svc.c index a02b8a745..5d7eac433 100644 --- a/services/std_svc/pci_svc.c +++ b/services/std_svc/pci_svc.c @@ -68,7 +68,7 @@ uint64_t pci_smc_handler(uint32_t smc_fid, } break; case SMC_PCI_READ: { - uint32_t ret; + uint32_t ret = 0U; if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) { SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U); diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c index 521bb9e16..c648a452a 100644 --- a/services/std_svc/rmmd/rmmd_main.c +++ b/services/std_svc/rmmd/rmmd_main.c @@ -32,6 +32,7 @@ #include <plat/common/platform.h> #include <platform_def.h> #include <services/rmmd_svc.h> +#include <services/firme_svc.h> #include <smccc_helpers.h> #include <lib/extensions/sme.h> #include <lib/extensions/sve.h> @@ -455,46 +456,6 @@ static int rmm_el3_ifc_get_feat_register(uint64_t feat_reg_idx, return E_RMM_OK; } -/* - * Update encryption key associated with mecid included in x1. - */ -static int rmmd_mecid_key_update(uint64_t x1) -{ - uint64_t mecid_width, mecid_width_mask; - uint16_t mecid; - unsigned int reason; - int ret; - - /* - * Check whether FEAT_MEC is supported by the hardware. If not, return - * unknown SMC. - */ - if (is_feat_mec_supported() == false) { - return E_RMM_UNK; - } - - /* - * Check whether the mecid parameter is at most MECIDR_EL2.MECIDWidthm1 + 1 - * in length. - */ - mecid_width = ((read_mecidr_el2() >> MECIDR_EL2_MECIDWidthm1_SHIFT) & - MECIDR_EL2_MECIDWidthm1_MASK) + 1UL; - mecid_width_mask = ((1UL << mecid_width) - 1UL); - - mecid = (x1 >> MECID_SHIFT) & MECID_MASK; - if ((mecid & ~mecid_width_mask) != 0U) { - return E_RMM_INVAL; - } - - reason = (x1 >> MEC_REFRESH_REASON_SHIFT) & MEC_REFRESH_REASON_MASK; - ret = plat_rmmd_mecid_key_update(mecid, reason); - - if (ret != 0) { - return E_RMM_UNK; - } - return E_RMM_OK; -} - /******************************************************************************* * This function handles RMM-EL3 interface SMCs ******************************************************************************/ @@ -585,7 +546,8 @@ uint64_t rmmd_rmm_el3_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, rmmd_rmm_sync_exit(x1); } case RMM_MEC_REFRESH: - ret = rmmd_mecid_key_update(x1); + ret = firme_handler(FIRME_MEC_REFRESH_FID, x1, x2, x3, x4, + cookie, handle, flags); SMC_RET1(handle, ret); default: WARN("RMMD: Unsupported RMM-EL3 call 0x%08x\n", smc_fid); diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c index c2b953fc2..fb402cc6e 100644 --- a/services/std_svc/std_svc_setup.c +++ b/services/std_svc/std_svc_setup.c @@ -83,6 +83,12 @@ static int32_t std_svc_setup(void) trng_setup(); #endif /* TRNG_SUPPORT */ +#if FIRME_SUPPORT + if (firme_init() != 0) { + ret = 1; + } +#endif /* FIRME_SUPPORT */ + #if DRTM_SUPPORT if (drtm_setup() != 0) { ret = 1; |