diff options
| author | Tom Rini <trini@konsulko.com> | 2026-06-28 08:27:59 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2026-06-28 08:27:59 -0600 |
| commit | 835a18f80f25731dc818bf9b771bfa111ea3dbeb (patch) | |
| tree | 1770bab11f8acfae0dc84a8505a0c25ed5fc54e6 | |
| parent | 63f6cc8ba618396cb9c0161bb5c6d217604ae1d0 (diff) | |
| parent | 8757c2428252eac46de7d1cadc43cf11211e867e (diff) | |
| download | u-boot-835a18f80f25731dc818bf9b771bfa111ea3dbeb.tar.gz u-boot-835a18f80f25731dc818bf9b771bfa111ea3dbeb.zip | |
Merge tag 'u-boot-imx-next-20260627' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI:https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/30547
- Move environment variables to .env file on imx7ul-evk/imx6ull-evk/mx6-sabre
- imx ipuv3 improvements.
- Initial support for aquila imx95
- Add support for OPTEE on i.MX93
- Allow users to inhibit i.MX trip point setup
- Add support for imx93_frdm 2CS 2GB DRAM support
- Add optee binary to i.MX9 platform types
- Enable booting Image.gz on imx8m-evk/imx9-evk
107 files changed, 4949 insertions, 455 deletions
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index ab135fc8a47..50ecb6cad39 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -82,25 +82,25 @@ }; ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; align-end = <4>; type = "blob-ext"; }; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 8993605af3c..690f56e65bb 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -137,7 +137,7 @@ ddr-1d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_imem.bin"; + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; #elif CONFIG_IMX8M_DDR4 filename = "ddr4_imem_1d_201810.bin"; #else @@ -149,7 +149,7 @@ ddr-1d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_dmem.bin"; + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; #elif CONFIG_IMX8M_DDR4 filename = "ddr4_dmem_1d_201810.bin"; #else @@ -162,7 +162,7 @@ #if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4) ddr-2d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_imem.bin"; + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; #else filename = "ddr4_imem_2d_201810.bin"; #endif @@ -172,7 +172,7 @@ ddr-2d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_dmem.bin"; + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; #else filename = "ddr4_dmem_2d_201810.bin"; #endif diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index ed2c704f2e5..b4deaa92160 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -96,25 +96,25 @@ }; ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; align-end = <4>; type = "blob-ext"; }; diff --git a/arch/arm/dts/imx93-u-boot.dtsi b/arch/arm/dts/imx93-u-boot.dtsi index a84cdf2bc45..bd970c955cf 100644 --- a/arch/arm/dts/imx93-u-boot.dtsi +++ b/arch/arm/dts/imx93-u-boot.dtsi @@ -69,6 +69,9 @@ container; image0 = "a55", "bl31.bin", "0x204E0000"; image1 = "a55", "u-boot.bin", "0x80200000"; +#if defined(CONFIG_OPTEE) + image2 = "a55", "tee.bin", "0x96000000"; +#endif }; }; }; diff --git a/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi b/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi new file mode 100644 index 00000000000..92ec0d3efa3 --- /dev/null +++ b/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) Toradex */ + +#include "imx95-u-boot.dtsi" + +/ { + sysinfo { + compatible = "toradex,sysinfo"; + }; +}; + +&lpuart1 { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&usb3 { + bootph-pre-ram; +}; + +&usb3_dwc3 { + bootph-pre-ram; + compatible = "fsl,imx95a-dwc3", "fsl,imx8mq-dwc3", "snps,dwc3"; +}; + +&usdhc1 { + bootph-pre-ram; +}; + diff --git a/arch/arm/dts/imx95-aquila-dev.dts b/arch/arm/dts/imx95-aquila-dev.dts new file mode 100644 index 00000000000..3df17700b63 --- /dev/null +++ b/arch/arm/dts/imx95-aquila-dev.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/aquila-development-board-kit + */ + +/dts-v1/; + +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> +#include "imx95-aquila.dtsi" + +/ { + model = "Aquila iMX95 on Aquila Development Board"; + compatible = "toradex,aquila-imx95-dev", + "toradex,aquila-imx95", + "fsl,imx95"; + + aliases { + eeprom1 = &carrier_eeprom; + }; + + dp_1_connector: dp0-connector { + compatible = "dp-connector"; + dp-pwr-supply = <®_dp_3p3v>; + type = "full-size"; + + port { + dp_1_connector_in: endpoint { + remote-endpoint = <&dsi2dp_out>; + }; + }; + }; + + reg_carrier_1p8v: regulator-carrier-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier 1V8"; + }; + + reg_dp_3p3v: regulator-dp-3p3v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_21_dp>; + /* Aquila GPIO_21_DP */ + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "DP_3V3"; + startup-delay-us = <10000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "aquila-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack", + "IN1R", "Digital Mic"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Digital Mic", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + status = "okay"; +}; + +/* Aquila CTRL_WAKE1_MICO# */ +&aquila_key_wake { + status = "okay"; +}; + +&dsi2dp_out { + remote-endpoint = <&dp_1_connector_in>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + status = "okay"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + status = "okay"; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + status = "okay"; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-0 = <&pinctrl_flexspi1_4bit>, + <&pinctrl_qspi_cs1>; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_8>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + cooling-levels = <255>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_mclk>; + clocks = <&scmi_clk IMX95_CLK_SAI2>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + AVDD-supply = <®_carrier_1p8v>; + CPVDD-supply = <®_carrier_1p8v>; + DBVDD-supply = <®_carrier_1p8v>; + DCVDD-supply = <®_carrier_1p8v>; + MICVDD-supply = <®_carrier_1p8v>; + wlf,drc-cfg-names = "default", "peaklimiter"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + wlf,in1r-as-dmicdat2; + }; + + /* Current measurement into module VCC */ + hwmon@41 { + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + /* USB-C OTG (TCPC USB PD PHY) */ + tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + op-sink-microwatt = <0>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb1_con_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb1_con_ss>; + }; + }; + }; + }; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_2 */ +&i3c2 { + status = "okay"; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + status = "okay"; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + status = "okay"; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + /* I2C on DSI Connector Pin #4 and #6 */ + i2c_dsi_0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* I2C on DSI Connector Pin #52 and #54 */ + i2c_dsi_1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + status = "okay"; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + status = "okay"; +}; + +/* Aquila UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Aquila UART_1 */ +&lpuart3 { + status = "okay"; +}; + +/* Aquila UART_2 as RS485 */ +&lpuart7 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + status = "okay"; +}; + +/* Aquila PWM_1 */ +&tpm3 { + status = "okay"; +}; + +/* Aquila PWM_2 */ +&tpm6 { + status = "okay"; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + status = "okay"; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + status = "okay"; +}; + +/* Aquila USB_1 */ +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + status = "okay"; + + port { + usb1_con_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + + status = "okay"; + + port { + usb1_con_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +/* Aquila SD_1 */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx95-aquila.dtsi b/arch/arm/dts/imx95-aquila.dtsi new file mode 100644 index 00000000000..69dc962a24a --- /dev/null +++ b/arch/arm/dts/imx95-aquila.dtsi @@ -0,0 +1,1160 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + */ + +#include <dt-bindings/net/ti-dp83867.h> +#include "imx95.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + can3 = &flexcan4; + eeprom0 = &som_eeprom; + ethernet0 = &enetc_port0; + i2c0 = &lpi2c3; + i2c1 = &lpi2c2; + i2c2 = &i3c2; + i2c3 = &lpi2c8; + i2c4 = &lpi2c4; + i2c6 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &rtc_i2c; + rtc1 = &scmi_bbm; + serial0 = &lpuart3; + serial1 = &lpuart7; + serial2 = &lpuart1; + serial3 = &lpuart2; + usb0 = &usb3; + usb1 = &usb2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aquila_key_wake: gpio-key-wakeup { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + + status = "disabled"; + + key-wakeup { + /* Aquila CTRL_WAKE1_MICO# */ + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + label = "Wake Up"; + wakeup-source; + linux,code = <KEY_WAKEUP>; + }; + }; + + clk_dsi2dp_refclk: clock-dsi2dp-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_dsi2dp_refclk_en: clock-dsi2dp-refclk-en { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_dp_clk_en>; + clocks = <&clk_dsi2dp_refclk>; + #clock-cells = <0>; + /* CTRL_DP_CLK_EN */ + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + clk_serdes_eth_ref: clock-serdes-eth-ref { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + /* CTRL_ETH_REF_CLK_STBY */ + enable-gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_LOW>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8"; + }; + + reg_dp_1p2v: regulator-dp-1p2v { + compatible = "regulator-fixed"; + /* CTRL_DP_BRIDGE_EN */ + gpios = <&som_gpio_expander_0 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "On-module +V1.2_DP"; + vin-supply = <®_1p8v>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_1_EN */ + gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_2_EN */ + gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_2_H_EN"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + /* Aquila SD_1_PWR_EN */ + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "SD_1_PWR_EN"; + startup-delay-us = <20000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + /* PMIC_SD_1_VSEL */ + gpios = <&som_gpio_expander_1 9 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "PMIC_SD_1_VSEL"; + states = <1800000 0x1>, + <3300000 0x0>; + }; + + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + linux,cma-default; + }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + vref-supply = <®_1p8v>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan4>; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1_8bit>, + <&pinctrl_qspi_cs1>; +}; + +&gpio1 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_C24", /* 10 */ + "", + "AQUILA_B17", + "CTRL_GPIO_EXP_INT#", + "AQUILA_B18"; + + status = "okay"; +}; + +&gpio2 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "AQUILA_B42", + "", + "AQUILA_B43"; +}; + +&gpio3 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_A11", + "", /* 20 */ + "AQUILA_B57", + "AQUILA_B19"; +}; + +&gpio4 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "AQUILA_C22", + "AQUILA_C21", + "AQUILA_C20", + "", /* 20 */ + "", + "", + "AQUILA_C23", + "AQUILA_D23", + "AQUILA_D24", + "", + "AQUILA_D25"; +}; + +&gpio5 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "AQUILA_B44", + "AQUILA_B45"; +}; + +/* Aquila I2C_2 */ +&i3c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2>; + i2c-scl-hz = <100000>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* On-module I2C - I2C_SOM */ +&lpi2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>, <&pinctrl_ctrl_gpio_exp_int>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>, <&pinctrl_ctrl_gpio_exp_int>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + status = "okay"; + + som_gpio_expander_0: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C38", /* 0 */ + "PCIE_2_RESET#", + "AQUILA_B77", + "USB_2_H_EN", + "BT_DISABLE#", + "WIFI_DISABLE#", + "CTRL_ETH_REF_CLK_STBY", + "CTRL_DP_BRIDGE_EN"; + }; + + som_gpio_expander_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C1", /* 0 */ + "AQUILA_C2", + "AQUILA_C3", + "AQUILA_C4", + "AQUILA_C36", + "AQUILA_B74", + "AQUILA_B75", + "USB_2_H_OC#", + "AQUILA_B81", + "PMIC_SD_1_VSEL", + "ETH_1_INT#", /* 10 */ + "CTRL_TPM_INT#", + "SPI_2_CS2_TPM", + "PCIE_WAKE_WIFI#", + "WIFI_WAKE_BT", + "WIFI_WAKEUP_HOST"; + }; + + som_dsi2dp_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clocks = <&clk_dsi2dp_refclk_en>; + clock-names = "refclk"; + vcc-supply = <®_dp_1p2v>; + vcca-supply = <®_dp_1p2v>; + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_out: endpoint { + data-lanes = <3 2 1 0>; + }; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila SPI_2 */ +&lpspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi4>; + cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>, + <&som_gpio_expander_1 12 GPIO_ACTIVE_LOW>; + + status = "okay"; + + som_tpm: tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0x1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + /* + * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz + * here as lpspi4's per-clock (2x the max speed) is 24 MHz. + */ + spi-max-frequency = <12000000>; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Aquila UART_4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* Aquila UART_1 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; +}; + +/* Aquila UART_2 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; +}; + +&mu7 { + status = "okay"; +}; + +/* Aquila ETH_2_XGMII_MDIO, shared between all ethernet ports */ +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + + status = "okay"; + + ethphy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + }; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_timer { + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpios = <&som_gpio_expander_0 0 GPIO_ACTIVE_LOW>; +}; + +/* On-module Wi-Fi or Aquila PCIE_2 */ +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI2>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; +}; + +&scmi_bbm { + linux,code = <KEY_POWER>; +}; + +&thermal_zones { + /* PF09 Main PMIC */ + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_ARM PMIC */ + pf53-arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_SOC PMIC */ + pf53-soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +/* Aquila PWM_1 */ +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +/* Aquila PWM_2 */ +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_dsi>, <&pinctrl_pwm4_dp>; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + dr_mode = "host"; + vbus-supply = <®_usb2_vbus>; +}; + +/* Aquila USB_1 */ +&usb3 { + fsl,disable-port-power-control; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; +}; + +&usb3_phy { + vbus-supply = <®_usb1_vbus>; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + + status = "okay"; +}; + +/* Aquila SD_1 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_sd1_cd_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_sd1_cd_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + +&wdog3 { + fsl,ext-reset-output; + + status = "okay"; +}; + +&scmi_iomuxc { + /* Aquila CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: ctrlwake1micogrp { + fsl,pins = <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e>; /* Aquila D6 */ + }; + + pinctrl_ctrl_dp_clk_en: dpclkengrp { + fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x11e>; /* CTRL_DP_CLK_EN */ + }; + + /* Aquila ETH_2_XGMII_MDIO */ + pinctrl_emdio: emdiogrp { + fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e>, /* Aquila B90 */ + <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e>; /* Aquila B89 */ + }; + + /* Aquila ETH_1 */ + pinctrl_enetc0: enetc0grp { + fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */ + <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */ + <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */ + <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */ + <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */ + <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */ + <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */ + <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */ + <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */ + <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */ + <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */ + <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */ + }; + + /* Aquila CAN_1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* Aquila B48 */ + <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* Aquila B49 */ + }; + + /* Aquila CAN_2 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* Aquila B50 */ + <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* Aquila B51 */ + }; + + /* Aquila CAN_3 */ + pinctrl_flexcan3: flexcan3grp { + fsl,pins = <IMX95_PAD_CCM_CLKO3__CAN3_TX 0x39e>, /* Aquila B53 */ + <IMX95_PAD_CCM_CLKO4__CAN3_RX 0x39e>; /* Aquila B54 */ + }; + + /* Aquila CAN_4 */ + pinctrl_flexcan4: flexcan4grp { + fsl,pins = <IMX95_PAD_GPIO_IO04__CAN4_TX 0x39e>, /* Aquila B55 */ + <IMX95_PAD_GPIO_IO05__CAN4_RX 0x39e>; /* Aquila B56 */ + }; + + /* Aquila QSPI_1 (4 bit) */ + pinctrl_flexspi1_4bit: flexspi14bitgrp { + fsl,pins = <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>, /* Aquila B65 */ + <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>, /* Aquila B68 */ + <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>, /* Aquila B67 */ + <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>, /* Aquila B61 */ + <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>, /* Aquila B60 */ + <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>; /* Aquila B63 */ + }; + + /* Aquila QSPI_1 (8 bit) */ + pinctrl_flexspi1_8bit: flexspi18bitgrp { + fsl,pins = <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>, /* Aquila B65 */ + <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>, /* Aquila B68 */ + <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>, /* Aquila B67 */ + <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>, /* Aquila B61 */ + <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>, /* Aquila B60 */ + <IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe>, /* Aquila B70 */ + <IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe>, /* Aquila B71 */ + <IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe>, /* Aquila B72 */ + <IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe>, /* Aquila B73 */ + <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>; /* Aquila B63 */ + }; + + /* Aquila GPIO_01 */ + pinctrl_gpio_1: gpio1grp { + fsl,pins = <IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x31e>; /* Aquila D23 */ + }; + + /* Aquila GPIO_02 */ + pinctrl_gpio_2: gpio2grp { + fsl,pins = <IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x31e>; /* Aquila D24 */ + }; + + /* Aquila GPIO_03 */ + pinctrl_gpio_3: gpio3grp { + fsl,pins = <IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x31e>; /* Aquila D25 */ + }; + + /* Aquila GPIO_04 */ + pinctrl_gpio_4: gpio4grp { + fsl,pins = <IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x31e>; /* Aquila C20 */ + }; + + /* Aquila GPIO_05 */ + pinctrl_gpio_5: gpio5grp { + fsl,pins = <IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x31e>; /* Aquila C21 */ + }; + + /* Aquila GPIO_06 */ + pinctrl_gpio_6: gpio6grp { + fsl,pins = <IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x31e>; /* Aquila C22 */ + }; + + /* Aquila GPIO_07 */ + pinctrl_gpio_7: gpio7grp { + fsl,pins = <IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x31e>; /* Aquila C23 */ + }; + + /* Aquila GPIO_08 */ + pinctrl_gpio_8: gpio8grp { + fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x31e>; /* Aquila C24 */ + }; + + /* Aquila GPIO_09_CSI_1 */ + pinctrl_gpio_9_csi_1: gpio9csi1grp { + fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x31e>; /* Aquila B17 */ + }; + + /* Aquila GPIO_10_CSI_1 */ + pinctrl_gpio_10_csi_1: gpio10csi1grp { + fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* Aquila B18 */ + }; + + /* Aquila GPIO_11_CSI_1 */ + pinctrl_gpio_11_csi_1: gpio11csi1grp { + fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x31e>; /* Aquila A11*/ + }; + + /* Aquila GPIO_12_CSI_1 */ + pinctrl_gpio_12_csi_1: gpio12csi1grp { + fsl,pins = <IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x31e>; /* Aquila B19 */ + }; + + /* Aquila GPIO_17_DSI_1 */ + pinctrl_gpio_17_dsi_1: gpio17dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x31e>; /* Aquila B42 */ + }; + + /* Aquila GPIO_18_DSI_1 */ + pinctrl_gpio_18_dsi_1: gpio18dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x31e>; /* Aquila B43 */ + }; + + /* Aquila GPIO_19_DSI_1 */ + pinctrl_gpio_19_dsi_1: gpio19dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e>; /* Aquila B44 */ + }; + + /* Aquila GPIO_20_DSI_1 */ + pinctrl_gpio_20_dsi_1: gpio20dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e>; /* Aquila B45 */ + }; + + /* Aquila GPIO_21_DP */ + pinctrl_gpio_21_dp: gpio21dpgrp { + fsl,pins = <IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x31e>; /* Aquila B57 */ + }; + + pinctrl_ctrl_gpio_exp_int: gpioexpintgrp { + fsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x31e>; /* CTRL_GPIO_EXP_INT# */ + }; + + /* Aquila I2C_2 */ + pinctrl_i3c2: i3c2cgrp { + fsl,pins = <IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40001186>, /* Aquila C17 */ + <IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40001186>; /* Aquila C16 */ + }; + + /* Aquila I2C_1 as GPIOs */ + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* Aquila D8 */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* Aquila D7 */ + }; + + /* Aquila I2C_1 */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* Aquila D8 */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* Aquila D7 */ + }; + + /* On-module I2C as GPIOs */ + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* I2C_SOM_SDA */ + <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* I2C_SOM_SCL */ + }; + + /* On-module I2C */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* I2C_SOM_SDA */ + <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* I2C_SOM_SCL */ + }; + + /* Aquila I2C_4_CSI1 as GPIO */ + pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>, /* Aquila A12 */ + <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>; /* Aquila A13 */ + }; + + /* Aquila I2C_4_CSI1 */ + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>, /* Aquila A12 */ + <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>; /* Aquila A13 */ + }; + + /* Aquila I2C_6 as GPIO */ + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* Aquila C18 */ + <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* Aquila C19 */ + }; + + /* Aquila I2C_6 */ + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* Aquila C18 */ + <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* Aquila C19 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 as GPIO */ + pinctrl_lpi2c8_gpio: lpi2c8gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x40001b9e>, /* Aquila C5/B40 */ + <IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x40001b9e>; /* Aquila C6/B41 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 */ + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = <IMX95_PAD_GPIO_IO12__LPI2C8_SDA 0x40001b9e>, /* Aquila C5/B40 */ + <IMX95_PAD_GPIO_IO13__LPI2C8_SCL 0x40001b9e>; /* Aquila C6/B41 */ + }; + + /* Aquila SPI_2 */ + pinctrl_lpspi4: lpspi4grp { + fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x3fe>, /* Aquila D16 */ + <IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x3fe>, /* Aquila D15 */ + <IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x3fe>, /* Aquila D17 */ + <IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x3fe>; /* Aquila D14 */ + }; + + /* Aquila SPI_1 */ + pinctrl_lpspi6: lpspi6grp { + fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x3fe>, /* Aquila D9 */ + <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* Aquila D10 */ + <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* Aquila D11 */ + <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* Aquila D12 */ + }; + + /* Aquila PCIE_1 */ + pinctrl_pcie0: pcie0grp { + fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40001b1e>; /* Aquila C37 */ + }; + + /* Aquila PCIE_2 */ + pinctrl_pcie1: pcie1grp { + fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x40001b1e>; /* Aquila C34 */ + }; + + /* Aquila QSPI_1_CS1# */ + pinctrl_qspi_cs1: qspics1grp { + fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>; /* Aquila B66 */ + }; + + /* Aquila QSPI_1_CS2# as GPIO */ + pinctrl_qspi_cs2_gpio: qspics2gpiogrp { + fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x3fe>; /* Aquila B62 */ + }; + + /* Aquila I2S_1 */ + pinctrl_sai2: sai2grp { + fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x11e>, /* Aquila B21 */ + <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x11e>, /* Aquila B20 */ + <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x11e>, /* Aquila B23 */ + <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x11e>; /* Aquila B22 */ + }; + + pinctrl_sai2_mclk: sai2mclkgrp { + fsl,pins = <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e>; /* Aquila B24 */ + }; + + /* Aquila SD_1_CD# as GPIO */ + pinctrl_sd1_cd_gpio: sd1cdgpiogrp { + fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* Aquila A1 */ + }; + + /* Aquila SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: sd1pwrengpiogrp { + fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* Aquila A6 */ + }; + + /* Aquila PWM_1 */ + pinctrl_pwm1: tpm3ch3grp { + fsl,pins = <IMX95_PAD_GPIO_IO24__TPM3_CH3 0x11e>; /* Aquila C25 */ + }; + + /* Aquila PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: tpm5ch0gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x11e>; /* Aquila B46 */ + }; + + /* Aquila PWM_3_DSI */ + pinctrl_pwm3_dsi: tpm5ch0grp { + fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* Aquila B46 */ + }; + + /* Aquila PWM_4_DP */ + pinctrl_pwm4_dp: tpm5ch3grp { + fsl,pins = <IMX95_PAD_GPIO_IO26__TPM5_CH3 0x11e>; /* Aquila B58 */ + }; + + /* Aquila PWM_2 */ + pinctrl_pwm2: tpm6ch0grp { + fsl,pins = <IMX95_PAD_GPIO_IO08__TPM6_CH0 0x11e>; /* Aquila C26 */ + }; + + /* Aquila UART_3 */ + pinctrl_uart1: uart1grp { + fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, /* Aquila D20 */ + <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>; /* Aquila D19 */ + }; + + /* Aquila UART_4 */ + pinctrl_uart2: uart2grp { + fsl,pins = <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>, /* Aquila D22 */ + <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>; /* Aquila D21 */ + }; + + /* Aquila UART_1 */ + pinctrl_uart3: uart3grp { + fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX 0x31e>, /* Aquila B37 */ + <IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>, /* Aquila B35 */ + <IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 0x31e>, /* Aquila B36 */ + <IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 0x31e>; /* Aquila B38 */ + }; + + /* Aquila UART_2 */ + pinctrl_uart7: uart7grp { + fsl,pins = <IMX95_PAD_GPIO_IO36__LPUART7_TX 0x31e>, /* Aquila B33 */ + <IMX95_PAD_GPIO_IO37__LPUART7_RX 0x31e>, /* Aquila B31 */ + <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e>, /* Aquila B32 */ + <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>; /* Aquila B34 */ + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* eMMC_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* eMMC_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* eMMC_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* eMMC_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* eMMC_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* eMMC_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* eMMC_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* eMMC_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* eMMC_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* eMMC_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* eMMC_STROBE */ + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* eMMC_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* eMMC_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* eMMC_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* eMMC_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* eMMC_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* eMMC_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* eMMC_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* eMMC_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* eMMC_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* eMMC_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* eMMC_STROBE */ + }; + + /* Aquila SD_1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* Aquila A5 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* Aquila A7 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* Aquila A3 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* Aquila A2 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* Aquila A10 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* Aquila A8 */ + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* Aquila A5 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* Aquila A7 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* Aquila A3 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* Aquila A2 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* Aquila A10 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* Aquila A8 */ + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* Aquila A5 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* Aquila A7 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* Aquila A3 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* Aquila A2 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* Aquila A10 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* Aquila A8 */ + }; +}; diff --git a/arch/arm/dts/imx952-u-boot.dtsi b/arch/arm/dts/imx952-u-boot.dtsi index 28f47244356..80399e6ff2a 100644 --- a/arch/arm/dts/imx952-u-boot.dtsi +++ b/arch/arm/dts/imx952-u-boot.dtsi @@ -181,12 +181,7 @@ bootph-all; }; -&gpio1 { - reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>; -}; - &gpio2 { - reg = <0 0x43810000 0 0x1000>, <0 0x43810040 0 0x40>; bootph-pre-ram; /* * Use one SPL/U-Boot for mx952evk and mx952evkrpmsg, since GPIO2 @@ -196,17 +191,14 @@ }; &gpio3 { - reg = <0 0x43820000 0 0x1000>, <0 0x43820040 0 0x40>; bootph-pre-ram; }; &gpio4 { - reg = <0 0x43840000 0 0x1000>, <0 0x43840040 0 0x40>; bootph-pre-ram; }; &gpio5 { - reg = <0 0x43850000 0 0x1000>, <0 0x43850040 0 0x40>; bootph-pre-ram; }; diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 81af89c631f..9c5f3090bd8 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -82,7 +82,7 @@ int enable_lcdif_clock(u32 base_addr, bool enable); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); void mxs_set_lcdclk(u32 base_addr, u32 freq); -void select_ldb_di_clock_source(enum ldb_di_clock clk); +void select_ldb_di_clock_source(enum ldb_di_clock clk0, enum ldb_di_clock clk1); void enable_eim_clk(unsigned char enable); int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 04e7f20a2a6..8d779d6ae1b 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -30,6 +30,7 @@ #define ELE_START_RNG (0xA3) #define ELE_CMD_DERIVE_KEY (0xA9) #define ELE_GENERATE_DEK_BLOB (0xAF) +#define ELE_V2X_GET_STATE_REQ (0xB2) #define ELE_ENABLE_PATCH_REQ (0xC3) #define ELE_RELEASE_RDC_REQ (0xC4) #define ELE_GET_FW_STATUS_REQ (0xC5) @@ -141,6 +142,12 @@ struct ele_get_info_data { u32 reserved[8]; }; +struct v2x_get_state { + u8 v2x_state; + u8 v2x_power_state; + u32 v2x_err_code; +}; + int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response); int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response); int ele_release_container(u32 *response); @@ -166,4 +173,5 @@ int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response); int ele_set_gmid(u32 *response); int ele_volt_change_start_req(void); int ele_volt_change_finish_req(void); +int ele_v2x_get_state(struct v2x_get_state *state, u32 *response); #endif diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index c49ad44ac2d..93be5644c88 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -47,7 +47,7 @@ u32 get_imx_reset_cause(void) return reset_cause; } -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) && !CONFIG_IS_ENABLED(CPU) static char *get_reset_cause(void) { switch (get_imx_reset_cause()) { @@ -75,11 +75,6 @@ static char *get_reset_cause(void) return "WDOG4"; case 0x00200: return "TEMPSENSE"; -#elif defined(CONFIG_IMX8M) - case 0x00100: - return "WDOG2"; - case 0x00200: - return "TEMPSENSE"; #else case 0x00100: return "TEMPSENSE"; @@ -90,63 +85,10 @@ static char *get_reset_cause(void) return "unknown reset"; } } -#endif - -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case MXC_CPU_IMX8MP: - return "8MP[8]"; /* Quad-core version of the imx8mp */ - case MXC_CPU_IMX8MPD2: - return "8MP Dual[2]"; /* Dual-core version of the imx8mp, low cost industrial & HMI */ - case MXC_CPU_IMX8MPD: - return "8MP Dual[3]"; /* Dual-core version of the imx8mp */ - case MXC_CPU_IMX8MPL: - return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */ - case MXC_CPU_IMX8MP5: - return "8MP[5]"; /* Quad-core version of the imx8mp, low cost industrial & HMI */ - case MXC_CPU_IMX8MP6: - return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */ - case MXC_CPU_IMX8MPUL: - return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */ - case MXC_CPU_IMX8MN: - return "8MNano Quad"; /* Quad-core version */ - case MXC_CPU_IMX8MND: - return "8MNano Dual"; /* Dual-core version */ - case MXC_CPU_IMX8MNS: - return "8MNano Solo"; /* Single-core version */ - case MXC_CPU_IMX8MNL: - return "8MNano QuadLite"; /* Quad-core Lite version */ - case MXC_CPU_IMX8MNDL: - return "8MNano DualLite"; /* Dual-core Lite version */ - case MXC_CPU_IMX8MNSL: - return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */ - case MXC_CPU_IMX8MNUQ: - return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */ - case MXC_CPU_IMX8MNUD: - return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */ - case MXC_CPU_IMX8MNUS: - return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */ - case MXC_CPU_IMX8MM: - return "8MMQ"; /* Quad-core version of the imx8mm */ - case MXC_CPU_IMX8MML: - return "8MMQL"; /* Quad-core Lite version of the imx8mm */ - case MXC_CPU_IMX8MMD: - return "8MMD"; /* Dual-core version of the imx8mm */ - case MXC_CPU_IMX8MMDL: - return "8MMDL"; /* Dual-core Lite version of the imx8mm */ - case MXC_CPU_IMX8MMS: - return "8MMS"; /* Single-core version of the imx8mm */ - case MXC_CPU_IMX8MMSL: - return "8MMSL"; /* Single-core Lite version of the imx8mm */ - case MXC_CPU_IMX8MQ: - return "8MQ"; /* Quad-core version of the imx8mq */ - case MXC_CPU_IMX8MQL: - return "8MQLite"; /* Quad-core Lite version of the imx8mq */ - case MXC_CPU_IMX8MD: - return "8MD"; /* Dual-core version of the imx8mq */ case MXC_CPU_MX7S: return "7S"; /* Single-core version of the mx7 */ case MXC_CPU_MX7D: diff --git a/arch/arm/mach-imx/fdt.c b/arch/arm/mach-imx/fdt.c index f19ab9edce4..1ef26718463 100644 --- a/arch/arm/mach-imx/fdt.c +++ b/arch/arm/mach-imx/fdt.c @@ -3,6 +3,7 @@ * Copyright 2024 NXP */ +#include <env.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> @@ -91,6 +92,15 @@ int fixup_thermal_trips(void *blob, const char *name) int minc, maxc; int node, trip; + /* + * During development or various dangerous experiments, it may + * be necessary to override the trip points. Allow users to do + * that. However, do keep in mind that this may damage the SoC. + */ + if (CONFIG_IS_ENABLED(ENV_SUPPORT)) + if (env_get("imx_skip_fixup_thermal_trips")) + return 0; + node = fdt_path_offset(blob, "/thermal-zones"); if (node < 0) return node; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 0d22d3b4e3a..5f7d7e4c66e 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -10,6 +10,7 @@ config IMX8M select ARMV8_CRYPTO imply CPU imply CPU_IMX + imply DM_THERMAL imply IMX_TMU config IMX8MQ diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index e600fd6b33e..909bd7476db 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1480,6 +1480,33 @@ void reset_cpu(void) #endif #if IS_ENABLED(CONFIG_ARCH_MISC_INIT) +static char *get_reset_cause(void) +{ + switch (get_imx_reset_cause()) { + case 0x00001: + case 0x00011: + return "POR"; + case 0x00004: + return "CSU"; + case 0x00008: + return "IPP USER"; + case 0x00010: + return "WDOG"; + case 0x00020: + return "JTAG HIGH-Z"; + case 0x00040: + return "JTAG SW"; + case 0x00080: + return "WDOG3"; + case 0x00100: + return "WDOG2"; + case 0x00200: + return "TEMPSENSE"; + default: + return "unknown reset"; + } +} + int arch_misc_init(void) { if (IS_ENABLED(CONFIG_FSL_CAAM)) { @@ -1491,6 +1518,9 @@ int arch_misc_init(void) printf("Failed to initialize caam_jr: %d\n", ret); } + if (IS_ENABLED(CONFIG_XPL_BUILD)) + printf("Reset cause: %s\n", get_reset_cause()); + return 0; } #endif diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 6d6f3b81aca..3e9566bd7ca 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -254,11 +254,6 @@ static char *get_reset_cause(char *ret) } #if defined(CONFIG_DISPLAY_CPUINFO) -const char *get_imx_type(u32 imxtype) -{ - return "8ULP"; -} - int print_cpuinfo(void) { u32 cpurev; @@ -266,8 +261,7 @@ int print_cpuinfo(void) cpurev = get_cpu_rev(); - printf("CPU: i.MX%s rev%d.%d at %d MHz\n", - get_imx_type((cpurev & 0xFF000) >> 12), + printf("CPU: i.MX8ULP rev%d.%d at %d MHz\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 0a7a4360eaf..cbd0078ba2a 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -14,6 +14,7 @@ config IMX9 select HAS_CAAM select ROM_UNIFIED_SECTIONS imply IMX_TMU + imply OF_LIVE config IMX93 bool @@ -172,6 +173,10 @@ config TARGET_IMX943_EVK imply BOOTSTD_FULL imply OF_UPSTREAM +config TARGET_AQUILA_IMX95 + bool "Support Toradex Aquila iMX95" + select IMX95 + config TARGET_TORADEX_SMARC_IMX95 bool "Support Toradex SMARC iMX95" select IMX95 @@ -205,6 +210,7 @@ source "board/phytec/phycore_imx91_93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" +source "board/toradex/aquila-imx95/Kconfig" source "board/toradex/smarc-imx95/Kconfig" source "board/toradex/verdin-imx95/Kconfig" source "board/nxp/imx952_evk/Kconfig" diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile index 80b697396ea..ec08430d41d 100644 --- a/arch/arm/mach-imx/imx9/Makefile +++ b/arch/arm/mach-imx/imx9/Makefile @@ -11,7 +11,7 @@ obj-y += soc.o clock.o clock_root.o trdc.o endif ifneq ($(CONFIG_SPL_BUILD),y) -obj-y += imx_bootaux.o +obj-y += imx_bootaux.o misc.o endif obj-$(CONFIG_$(PHASE_)IMX_QB) += qb.o diff --git a/arch/arm/mach-imx/imx9/misc.c b/arch/arm/mach-imx/imx9/misc.c new file mode 100644 index 00000000000..3cad67aed43 --- /dev/null +++ b/arch/arm/mach-imx/imx9/misc.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023-2026 NXP + * + */ + +#include <command.h> +#include <cpu_func.h> +#include <init.h> +#include <log.h> +#include <asm/io.h> +#include <errno.h> +#include <linux/bitops.h> +#include <asm/arch-imx/cpu.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/arch/sys_proto.h> +#include <linux/delay.h> +#include <linux/sizes.h> +#include <display_options.h> + +static int do_v2x_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + u32 resp = 0; + struct v2x_get_state state; + + if (is_imx91() || is_imx93()) { + printf("No V2X supported\n"); + return CMD_RET_FAILURE; + } + + ret = ele_v2x_get_state(&state, &resp); + if (ret) { + printf("get v2x state failed, resp 0x%x, ret %d\n", resp, ret); + return CMD_RET_FAILURE; + } + + printf("V2X state: 0x%x\n", state.v2x_state); + printf("V2X power state: 0x%x\n", state.v2x_power_state); + printf("V2X err code: 0x%x\n", state.v2x_err_code); + + return CMD_RET_SUCCESS; +} + +static int do_ele_info(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + u32 res = 0, length; + struct ele_get_info_data *info; + + /* ELE can't access full DDR */ + info = (struct ele_get_info_data *)(CONFIG_TEXT_BASE + SZ_2M - + sizeof(struct ele_get_info_data)); + flush_dcache_range((ulong)info, (ulong)info + sizeof(struct ele_get_info_data)); + + ret = ele_get_info(info, &res); + if (ret) { + printf("Get ELE info failed, resp 0x%x, ret %d\n", res, ret); + return CMD_RET_FAILURE; + } + + invalidate_dcache_range((ulong)info, (ulong)info + sizeof(struct ele_get_info_data)); + + printf("SOC: 0x%x\n", info->soc); + printf("LC: 0x%x\n", info->lc); + + printf("\nUID:\n"); + print_buffer(0, &info->uid, 4, 4, 0); + + printf("\nSHA256 ROM PATCH:\n"); + print_buffer(0, &info->sha256_rom_patch, 4, 8, 0); + + printf("\nSHA FW:\n"); + print_buffer(0, &info->sha_fw, 4, 8, 0); + + printf("\nOEM SRKH:\n"); + print_buffer(0, &info->oem_srkh, 4, 16, 0); + + printf("\nSTATE: 0x%x\n", info->state); + + length = (info->hdr >> 16) & 0xffff; + if (length == sizeof(struct ele_get_info_data)) { + printf("\nOEM PQC SRKH:\n"); + print_buffer(0, &info->oem_pqc_srkh, 4, 16, 0); + } + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(v2x_status, CONFIG_SYS_MAXARGS, 1, do_v2x_status, + "display v2x status", + "" +); + +U_BOOT_CMD(ele_info, CONFIG_SYS_MAXARGS, 1, do_ele_info, + "display ELE information", + "" +); diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 0c731e76329..dcf2fff1aa6 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -21,6 +21,7 @@ #include <asm/armv8/mmu.h> #include <dm/device.h> #include <dm/device_compat.h> +#include <dm/ofnode.h> #include <dm/uclass.h> #include <env.h> #include <env_internal.h> @@ -738,13 +739,16 @@ int arch_cpu_init(void) int imx9_probe_mu(void) { struct udevice *devp; - int node, ret; + ofnode node; + int ret; u32 res; struct ele_get_info_data info; - node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4"); + node = ofnode_by_compatible(ofnode_null(), "fsl,imx93-mu-s4"); + if (!ofnode_valid(node)) + return -ENODEV; - ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); + ret = uclass_get_device_by_ofnode(UCLASS_MISC, node, &devp); if (ret) return ret; diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index b5aa606b8d0..d366180e788 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1452,7 +1452,7 @@ static void enable_ldb_di_clock_sources(void) * Try call this function as early in the boot process as possible since the * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5. */ -void select_ldb_di_clock_source(enum ldb_di_clock clk) +void select_ldb_di_clock_source(enum ldb_di_clock clk0, enum ldb_di_clock clk1) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; int reg; @@ -1525,8 +1525,8 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk) reg = readl(&mxc_ccm->cs2cdr); reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK); - reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) - | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)); + reg |= ((clk0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (clk1 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)); writel(reg, &mxc_ccm->cs2cdr); /* Unbypass pll3_sw_clk */ diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index ca1cf759fe1..1dd350cf50e 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -259,11 +259,6 @@ void reset_cpu(void) #endif #if defined(CONFIG_DISPLAY_CPUINFO) -const char *get_imx_type(u32 imxtype) -{ - return "7ULP"; -} - int print_cpuinfo(void) { u32 cpurev; @@ -271,8 +266,7 @@ int print_cpuinfo(void) cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", - get_imx_type((cpurev & 0xFF000) >> 12), + printf("CPU: Freescale i.MX7ULP rev%d.%d at %d MHz\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 8cfac9fbb34..4a2349e165b 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -218,7 +218,7 @@ static void set_gpr_register(void) int board_early_init_f(void) { - select_ldb_di_clock_source(MXC_PLL5_CLK); + select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK); set_gpr_register(); /* diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c index ddb7304d493..f7751fd6fb1 100644 --- a/board/ge/b1x5v2/b1x5v2.c +++ b/board/ge/b1x5v2/b1x5v2.c @@ -320,7 +320,7 @@ int overwrite_console(void) int board_early_init_f(void) { - select_ldb_di_clock_source(MXC_PLL5_CLK); + select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK); return 0; } diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index e1d08475e94..9fc5f604a49 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -383,7 +383,7 @@ int board_early_init_f(void) #if defined(CONFIG_VIDEO_IPUV3) /* Set LDB clock to Video PLL */ - select_ldb_di_clock_source(MXC_PLL5_CLK); + select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK); #endif return 0; } diff --git a/board/nxp/imx8mm_evk/imx8mm_evk.env b/board/nxp/imx8mm_evk/imx8mm_evk.env index d59bd6fd5ed..88eefaa35e5 100644 --- a/board/nxp/imx8mm_evk/imx8mm_evk.env +++ b/board/nxp/imx8mm_evk/imx8mm_evk.env @@ -12,6 +12,8 @@ initrd_addr=0x48080000 image=Image ip_dyn=yes kernel_addr_r=0x42000000 +kernel_comp_addr_r=0x60000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mn_evk/imx8mn_evk.env b/board/nxp/imx8mn_evk/imx8mn_evk.env index cffa83bf792..fbdf202c573 100644 --- a/board/nxp/imx8mn_evk/imx8mn_evk.env +++ b/board/nxp/imx8mn_evk/imx8mn_evk.env @@ -12,6 +12,8 @@ initrd_addr=0x48080000 image=Image ip_dyn=yes kernel_addr_r=0x42000000 +kernel_comp_addr_r=0x60000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.env b/board/nxp/imx8mp_evk/imx8mp_evk.env index e994b93b168..dfc922e6215 100644 --- a/board/nxp/imx8mp_evk/imx8mp_evk.env +++ b/board/nxp/imx8mp_evk/imx8mp_evk.env @@ -10,6 +10,8 @@ fdt_addr=0x43000000 fdtfile=DEFAULT_FDT_FILE image=Image ip_dyn=yes +kernel_comp_addr_r=0x80000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw diff --git a/board/nxp/imx8mq_evk/imx8mq_evk.env b/board/nxp/imx8mq_evk/imx8mq_evk.env index 6575dd7cb07..dd674afac91 100644 --- a/board/nxp/imx8mq_evk/imx8mq_evk.env +++ b/board/nxp/imx8mq_evk/imx8mq_evk.env @@ -10,6 +10,8 @@ initrd_addr=0x43800000 image=Image ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x80000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx93_evk/imx93_evk.env b/board/nxp/imx93_evk/imx93_evk.env index b2ed1901a2b..76fadc00eeb 100644 --- a/board/nxp/imx93_evk/imx93_evk.env +++ b/board/nxp/imx93_evk/imx93_evk.env @@ -10,13 +10,16 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted -kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} diff --git a/board/nxp/imx93_frdm/Makefile b/board/nxp/imx93_frdm/Makefile index 9612b1fa55b..751ebfc9458 100644 --- a/board/nxp/imx93_frdm/Makefile +++ b/board/nxp/imx93_frdm/Makefile @@ -7,5 +7,5 @@ obj-y += imx93_frdm.o ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o +obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_1cs_2gb_timing.o lpddr4x_2cs_2gb_timing.o endif diff --git a/board/nxp/imx93_frdm/imx93_frdm.env b/board/nxp/imx93_frdm/imx93_frdm.env index 9af3bdfd714..96096bc51a0 100644 --- a/board/nxp/imx93_frdm/imx93_frdm.env +++ b/board/nxp/imx93_frdm/imx93_frdm.env @@ -10,12 +10,15 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=1 mmcpart=1 mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw mmcautodetect=yes mmcargs=setenv bootargs console=${console} root=${mmcroot} -kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} boot_os=booti ${loadaddr} - ${fdt_addr_r} diff --git a/board/nxp/imx93_frdm/lpddr4_timing.h b/board/nxp/imx93_frdm/lpddr4_timing.h index 192bc9e1519..3ff50d8519b 100644 --- a/board/nxp/imx93_frdm/lpddr4_timing.h +++ b/board/nxp/imx93_frdm/lpddr4_timing.h @@ -7,6 +7,7 @@ #define __LPDDR4_TIMING_H__ extern struct dram_timing_info dram_timing_1GB; -extern struct dram_timing_info dram_timing_2GB; +extern struct dram_timing_info dram_timing_1CS_2GB; +extern struct dram_timing_info dram_timing_2CS_2GB; #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_1cs_2gb_timing.c index cd129e12959..5439a039c3d 100644 --- a/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c +++ b/board/nxp/imx93_frdm/lpddr4x_1cs_2gb_timing.c @@ -1978,7 +1978,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_2GB = { +struct dram_timing_info dram_timing_1CS_2GB = { .ddrc_cfg = ddr_ddrc_cfg, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), .ddrphy_cfg = ddr_ddrphy_cfg, diff --git a/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c new file mode 100644 index 00000000000..79539941412 --- /dev/null +++ b/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c @@ -0,0 +1,2006 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + * + * Generated code from DDR Gear + * + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44104001 }, + { 0x4e301000, 0x0 }, + { 0x4e300000, 0x8000ff }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000412 }, + { 0x4e300084, 0x80000412 }, + { 0x4e300114, 0x1002 }, + { 0x4e300260, 0x80 }, + { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, + { 0x4e300800, 0x43b30002 }, + { 0x4e300804, 0x1f1f1f1f }, + { 0x4e301240, 0x0 }, + { 0x4e301244, 0x0 }, + { 0x4e301248, 0x0 }, + { 0x4e30124c, 0x0 }, + { 0x4e301250, 0x0 }, + { 0x4e301254, 0x0 }, + { 0x4e301258, 0x0 }, + { 0x4e30125c, 0x0 }, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + { 0x4e300100, 0x24a0321b }, + { 0x4e300104, 0xfaee001b }, + { 0x4e300108, 0x2f2e3233 }, + { 0x4e30010c, 0x5c18b }, + { 0x4e300124, 0x1c790000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x35f00000 }, + { 0x4e300170, 0x8b0b0608 }, + { 0x4e300250, 0x28 }, + { 0x4e300254, 0xfe00fe }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + { 0x4e300300, 0x224f2213 }, + { 0x4e300304, 0xfe2213 }, + { 0x4e300308, 0xa380e3c }, + }, + { + { 0x01, 0xe4 }, + { 0x02, 0x36 }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 0, + }, + { + { + { 0x4e300100, 0x124f2100 }, + { 0x4e300104, 0xf877000e }, + { 0x4e300108, 0x1816e4aa }, + { 0x4e30010c, 0x5101e6 }, + { 0x4e300124, 0xe3c0000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x30900000 }, + { 0x4e300170, 0x8a0a0508 }, + { 0x4e300250, 0x14 }, + { 0x4e300254, 0x7b007b }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + }, + { + { 0x01, 0xb4 }, + { 0x02, 0x1b }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 0, + }, + { + { + { 0x4e300100, 0x51000 }, + { 0x4e300104, 0xf855000a }, + { 0x4e300108, 0x6e620a48 }, + { 0x4e30010c, 0x31010d }, + { 0x4e300124, 0x4c50000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x30000000 }, + { 0x4e300170, 0x89090408 }, + { 0x4e300250, 0x7 }, + { 0x4e300254, 0x240024 }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + }, + { + { 0x01, 0x94 }, + { 0x02, 0x09 }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 1, + }, +}; + +/* Auto Generated by SNPS PHY Init code + * which inlcude PHYINIT, 1D/2D message block + * rerention CSR, PIE + */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { +/* ADDR mapping is from ds file. */ + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, +/* End of ADDR mapping. */ + { 0x1005f, 0x5ff}, + { 0x1015f, 0x5ff}, + { 0x1105f, 0x5ff}, + { 0x1115f, 0x5ff}, + { 0x11005f, 0x5ff}, + { 0x11015f, 0x5ff}, + { 0x11105f, 0x5ff}, + { 0x11115f, 0x5ff}, + { 0x21005f, 0x5ff}, + { 0x21015f, 0x5ff}, + { 0x21105f, 0x5ff}, + { 0x21115f, 0x5ff}, + { 0x55, 0x1ff}, + { 0x1055, 0x1ff}, + { 0x2055, 0x1ff}, + { 0x200c5, 0x19}, + { 0x1200c5, 0xb}, + { 0x2200c5, 0x7}, + { 0x2002e, 0x2}, + { 0x12002e, 0x2}, + { 0x22002e, 0x2}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x20024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x2007d, 0x212}, + { 0x2007c, 0x61}, + { 0x120024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x12007d, 0x212}, + { 0x12007c, 0x61}, + { 0x220024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x22007d, 0x212}, + { 0x22007c, 0x61}, + { 0x20056, 0x3}, + { 0x120056, 0x3}, + { 0x220056, 0x3}, + { 0x1004d, 0x600}, + { 0x1014d, 0x600}, + { 0x1104d, 0x600}, + { 0x1114d, 0x600}, + { 0x11004d, 0x600}, + { 0x11014d, 0x600}, + { 0x11104d, 0x600}, + { 0x11114d, 0x600}, + { 0x21004d, 0x600}, + { 0x21014d, 0x600}, + { 0x21104d, 0x600}, + { 0x21114d, 0x600}, + { 0x10049, 0xe00}, + { 0x10149, 0xe00}, + { 0x11049, 0xe00}, + { 0x11149, 0xe00}, + { 0x110049, 0xe00}, + { 0x110149, 0xe00}, + { 0x111049, 0xe00}, + { 0x111149, 0xe00}, + { 0x210049, 0xe00}, + { 0x210149, 0xe00}, + { 0x211049, 0xe00}, + { 0x211149, 0xe00}, + { 0x43, 0x60}, + { 0x1043, 0x60}, + { 0x2043, 0x60}, + { 0x20018, 0x1}, + { 0x20075, 0x4}, + { 0x20050, 0x0}, + { 0x2009b, 0x2}, + { 0x20008, 0x3a5}, + { 0x120008, 0x1d3}, + { 0x220008, 0x9c}, + { 0x20088, 0x9}, + { 0x200b2, 0x10c}, + { 0x10043, 0x5a1}, + { 0x10143, 0x5a1}, + { 0x11043, 0x5a1}, + { 0x11143, 0x5a1}, + { 0x1200b2, 0x10c}, + { 0x110043, 0x5a1}, + { 0x110143, 0x5a1}, + { 0x111043, 0x5a1}, + { 0x111143, 0x5a1}, + { 0x2200b2, 0x10c}, + { 0x210043, 0x5a1}, + { 0x210143, 0x5a1}, + { 0x211043, 0x5a1}, + { 0x211143, 0x5a1}, + { 0x200fa, 0x2}, + { 0x1200fa, 0x2}, + { 0x2200fa, 0x2}, + { 0x20019, 0x1}, + { 0x120019, 0x1}, + { 0x220019, 0x1}, + { 0x200f0, 0x600}, + { 0x200f1, 0x0}, + { 0x200f2, 0x4444}, + { 0x200f3, 0x8888}, + { 0x200f4, 0x5655}, + { 0x200f5, 0x0}, + { 0x200f6, 0x0}, + { 0x200f7, 0xf000}, + { 0x1004a, 0x500}, + { 0x1104a, 0x500}, + { 0x20025, 0x0}, + { 0x2002d, 0x0}, + { 0x12002d, 0x0}, + { 0x22002d, 0x0}, + { 0x2002c, 0x0}, + /* workaround STAR_3141216 marker */ + { 0x20021, 0x0}, + /* workaround STAR_3975199 marker */ + { 0x200c7, 0x21}, + /* workaround STAR_3975199 marker */ + { 0x200ca, 0x24}, + /* workaround STAR_3975199 marker */ + { 0x1200c7, 0x21}, + /* workaround STAR_3975199 marker */ + { 0x1200ca, 0x24}, +}; + +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x1005f, 0x0}, + { 0x1015f, 0x0}, + { 0x1105f, 0x0}, + { 0x1115f, 0x0}, + { 0x11005f, 0x0}, + { 0x11015f, 0x0}, + { 0x11105f, 0x0}, + { 0x11115f, 0x0}, + { 0x21005f, 0x0}, + { 0x21015f, 0x0}, + { 0x21105f, 0x0}, + { 0x21115f, 0x0}, + { 0x55, 0x0}, + { 0x1055, 0x0}, + { 0x2055, 0x0}, + { 0x200c5, 0x0}, + { 0x1200c5, 0x0}, + { 0x2200c5, 0x0}, + { 0x2002e, 0x0}, + { 0x12002e, 0x0}, + { 0x22002e, 0x0}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x20024, 0x0}, + { 0x2003a, 0x0}, + { 0x2007d, 0x0}, + { 0x2007c, 0x0}, + { 0x120024, 0x0}, + { 0x12007d, 0x0}, + { 0x12007c, 0x0}, + { 0x220024, 0x0}, + { 0x22007d, 0x0}, + { 0x22007c, 0x0}, + { 0x20056, 0x0}, + { 0x120056, 0x0}, + { 0x220056, 0x0}, + { 0x1004d, 0x0}, + { 0x1014d, 0x0}, + { 0x1104d, 0x0}, + { 0x1114d, 0x0}, + { 0x11004d, 0x0}, + { 0x11014d, 0x0}, + { 0x11104d, 0x0}, + { 0x11114d, 0x0}, + { 0x21004d, 0x0}, + { 0x21014d, 0x0}, + { 0x21104d, 0x0}, + { 0x21114d, 0x0}, + { 0x10049, 0x0}, + { 0x10149, 0x0}, + { 0x11049, 0x0}, + { 0x11149, 0x0}, + { 0x110049, 0x0}, + { 0x110149, 0x0}, + { 0x111049, 0x0}, + { 0x111149, 0x0}, + { 0x210049, 0x0}, + { 0x210149, 0x0}, + { 0x211049, 0x0}, + { 0x211149, 0x0}, + { 0x43, 0x0}, + { 0x1043, 0x0}, + { 0x2043, 0x0}, + { 0x20018, 0x0}, + { 0x20075, 0x0}, + { 0x20050, 0x0}, + { 0x2009b, 0x0}, + { 0x20008, 0x0}, + { 0x120008, 0x0}, + { 0x220008, 0x0}, + { 0x20088, 0x0}, + { 0x200b2, 0x0}, + { 0x10043, 0x0}, + { 0x10143, 0x0}, + { 0x11043, 0x0}, + { 0x11143, 0x0}, + { 0x1200b2, 0x0}, + { 0x110043, 0x0}, + { 0x110143, 0x0}, + { 0x111043, 0x0}, + { 0x111143, 0x0}, + { 0x2200b2, 0x0}, + { 0x210043, 0x0}, + { 0x210143, 0x0}, + { 0x211043, 0x0}, + { 0x211143, 0x0}, + { 0x200fa, 0x0}, + { 0x1200fa, 0x0}, + { 0x2200fa, 0x0}, + { 0x20019, 0x0}, + { 0x120019, 0x0}, + { 0x220019, 0x0}, + { 0x200f0, 0x0}, + { 0x200f1, 0x0}, + { 0x200f2, 0x0}, + { 0x200f3, 0x0}, + { 0x200f4, 0x0}, + { 0x200f5, 0x0}, + { 0x200f6, 0x0}, + { 0x200f7, 0x0}, + { 0x1004a, 0x0}, + { 0x1104a, 0x0}, + { 0x20025, 0x0}, + { 0x2002d, 0x0}, + { 0x12002d, 0x0}, + { 0x22002d, 0x0}, + { 0x2002c, 0x0}, + { 0xd0000, 0x0}, + { 0x90000, 0x0}, + { 0x90001, 0x0}, + { 0x90002, 0x0}, + { 0x90003, 0x0}, + { 0x90004, 0x0}, + { 0x90005, 0x0}, + { 0x90029, 0x0}, + { 0x9002a, 0x0}, + { 0x9002b, 0x0}, + { 0x9002c, 0x0}, + { 0x9002d, 0x0}, + { 0x9002e, 0x0}, + { 0x9002f, 0x0}, + { 0x90030, 0x0}, + { 0x90031, 0x0}, + { 0x90032, 0x0}, + { 0x90033, 0x0}, + { 0x90034, 0x0}, + { 0x90035, 0x0}, + { 0x90036, 0x0}, + { 0x90037, 0x0}, + { 0x90038, 0x0}, + { 0x90039, 0x0}, + { 0x9003a, 0x0}, + { 0x9003b, 0x0}, + { 0x9003c, 0x0}, + { 0x9003d, 0x0}, + { 0x9003e, 0x0}, + { 0x9003f, 0x0}, + { 0x90040, 0x0}, + { 0x90041, 0x0}, + { 0x90042, 0x0}, + { 0x90043, 0x0}, + { 0x90044, 0x0}, + { 0x90045, 0x0}, + { 0x90046, 0x0}, + { 0x90047, 0x0}, + { 0x90048, 0x0}, + { 0x90049, 0x0}, + { 0x9004a, 0x0}, + { 0x9004b, 0x0}, + { 0x9004c, 0x0}, + { 0x9004d, 0x0}, + { 0x9004e, 0x0}, + { 0x9004f, 0x0}, + { 0x90050, 0x0}, + { 0x90051, 0x0}, + { 0x90052, 0x0}, + { 0x90053, 0x0}, + { 0x90054, 0x0}, + { 0x90055, 0x0}, + { 0x90056, 0x0}, + { 0x90057, 0x0}, + { 0x90058, 0x0}, + { 0x90059, 0x0}, + { 0x9005a, 0x0}, + { 0x9005b, 0x0}, + { 0x9005c, 0x0}, + { 0x9005d, 0x0}, + { 0x9005e, 0x0}, + { 0x9005f, 0x0}, + { 0x90060, 0x0}, + { 0x90061, 0x0}, + { 0x90062, 0x0}, + { 0x90063, 0x0}, + { 0x90064, 0x0}, + { 0x90065, 0x0}, + { 0x90066, 0x0}, + { 0x90067, 0x0}, + { 0x90068, 0x0}, + { 0x90069, 0x0}, + { 0x9006a, 0x0}, + { 0x9006b, 0x0}, + { 0x9006c, 0x0}, + { 0x9006d, 0x0}, + { 0x9006e, 0x0}, + { 0x9006f, 0x0}, + { 0x90070, 0x0}, + { 0x90071, 0x0}, + { 0x90072, 0x0}, + { 0x90073, 0x0}, + { 0x90074, 0x0}, + { 0x90075, 0x0}, + { 0x90076, 0x0}, + { 0x90077, 0x0}, + { 0x90078, 0x0}, + { 0x90079, 0x0}, + { 0x9007a, 0x0}, + { 0x9007b, 0x0}, + { 0x9007c, 0x0}, + { 0x9007d, 0x0}, + { 0x9007e, 0x0}, + { 0x9007f, 0x0}, + { 0x90080, 0x0}, + { 0x90081, 0x0}, + { 0x90082, 0x0}, + { 0x90083, 0x0}, + { 0x90084, 0x0}, + { 0x90085, 0x0}, + { 0x90086, 0x0}, + { 0x90087, 0x0}, + { 0x90088, 0x0}, + { 0x90089, 0x0}, + { 0x9008a, 0x0}, + { 0x9008b, 0x0}, + { 0x9008c, 0x0}, + { 0x9008d, 0x0}, + { 0x9008e, 0x0}, + { 0x9008f, 0x0}, + { 0x90090, 0x0}, + { 0x90091, 0x0}, + { 0x90092, 0x0}, + { 0x90093, 0x0}, + { 0x90094, 0x0}, + { 0x90095, 0x0}, + { 0x90096, 0x0}, + { 0x90097, 0x0}, + { 0x90098, 0x0}, + { 0x90099, 0x0}, + { 0x9009a, 0x0}, + { 0x9009b, 0x0}, + { 0x9009c, 0x0}, + { 0x9009d, 0x0}, + { 0x9009e, 0x0}, + { 0x9009f, 0x0}, + { 0x900a0, 0x0}, + { 0x900a1, 0x0}, + { 0x900a2, 0x0}, + { 0x900a3, 0x0}, + { 0x900a4, 0x0}, + { 0x900a5, 0x0}, + { 0x900a6, 0x0}, + { 0x900a7, 0x0}, + { 0x900a8, 0x0}, + { 0x900a9, 0x0}, + { 0x40000, 0x0}, + { 0x40020, 0x0}, + { 0x40040, 0x0}, + { 0x40060, 0x0}, + { 0x40001, 0x0}, + { 0x40021, 0x0}, + { 0x40041, 0x0}, + { 0x40061, 0x0}, + { 0x40002, 0x0}, + { 0x40022, 0x0}, + { 0x40042, 0x0}, + { 0x40062, 0x0}, + { 0x40003, 0x0}, + { 0x40023, 0x0}, + { 0x40043, 0x0}, + { 0x40063, 0x0}, + { 0x40004, 0x0}, + { 0x40024, 0x0}, + { 0x40044, 0x0}, + { 0x40064, 0x0}, + { 0x40005, 0x0}, + { 0x40025, 0x0}, + { 0x40045, 0x0}, + { 0x40065, 0x0}, + { 0x40006, 0x0}, + { 0x40026, 0x0}, + { 0x40046, 0x0}, + { 0x40066, 0x0}, + { 0x40007, 0x0}, + { 0x40027, 0x0}, + { 0x40047, 0x0}, + { 0x40067, 0x0}, + { 0x40008, 0x0}, + { 0x40028, 0x0}, + { 0x40048, 0x0}, + { 0x40068, 0x0}, + { 0x40009, 0x0}, + { 0x40029, 0x0}, + { 0x40049, 0x0}, + { 0x40069, 0x0}, + { 0x4000a, 0x0}, + { 0x4002a, 0x0}, + { 0x4004a, 0x0}, + { 0x4006a, 0x0}, + { 0x4000b, 0x0}, + { 0x4002b, 0x0}, + { 0x4004b, 0x0}, + { 0x4006b, 0x0}, + { 0x4000c, 0x0}, + { 0x4002c, 0x0}, + { 0x4004c, 0x0}, + { 0x4006c, 0x0}, + { 0x4000d, 0x0}, + { 0x4002d, 0x0}, + { 0x4004d, 0x0}, + { 0x4006d, 0x0}, + { 0x4000e, 0x0}, + { 0x4002e, 0x0}, + { 0x4004e, 0x0}, + { 0x4006e, 0x0}, + { 0x4000f, 0x0}, + { 0x4002f, 0x0}, + { 0x4004f, 0x0}, + { 0x4006f, 0x0}, + { 0x40010, 0x0}, + { 0x40030, 0x0}, + { 0x40050, 0x0}, + { 0x40070, 0x0}, + { 0x40011, 0x0}, + { 0x40031, 0x0}, + { 0x40051, 0x0}, + { 0x40071, 0x0}, + { 0x40012, 0x0}, + { 0x40032, 0x0}, + { 0x40052, 0x0}, + { 0x40072, 0x0}, + { 0x40013, 0x0}, + { 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0x0}, + { 0x90202, 0x0}, + { 0x90203, 0x0}, + { 0x90205, 0x0}, + { 0x90206, 0x0}, + { 0x90207, 0x0}, + { 0x90208, 0x0}, + { 0x20020, 0x0}, + { 0x100080, 0x0}, + { 0x101080, 0x0}, + { 0x102080, 0x0}, + { 0x110020, 0x0}, + { 0x110080, 0x0}, + { 0x110081, 0x0}, + { 0x1100d0, 0x0}, + { 0x1100d1, 0x0}, + { 0x11008c, 0x0}, + { 0x11008d, 0x0}, + { 0x110180, 0x0}, + { 0x110181, 0x0}, + { 0x1101d0, 0x0}, + { 0x1101d1, 0x0}, + { 0x11018c, 0x0}, + { 0x11018d, 0x0}, + { 0x1100c0, 0x0}, + { 0x1100c1, 0x0}, + { 0x1101c0, 0x0}, + { 0x1101c1, 0x0}, + { 0x1102c0, 0x0}, + { 0x1102c1, 0x0}, + { 0x1103c0, 0x0}, + { 0x1103c1, 0x0}, + { 0x1104c0, 0x0}, + { 0x1104c1, 0x0}, + { 0x1105c0, 0x0}, + { 0x1105c1, 0x0}, + { 0x1106c0, 0x0}, + { 0x1106c1, 0x0}, + { 0x1107c0, 0x0}, + { 0x1107c1, 0x0}, + { 0x1108c0, 0x0}, + { 0x1108c1, 0x0}, + { 0x1100ae, 0x0}, + { 0x1100af, 0x0}, + { 0x111020, 0x0}, + { 0x111080, 0x0}, + { 0x111081, 0x0}, + { 0x1110d0, 0x0}, + { 0x1110d1, 0x0}, + { 0x11108c, 0x0}, + { 0x11108d, 0x0}, + { 0x111180, 0x0}, + { 0x111181, 0x0}, + { 0x1111d0, 0x0}, + { 0x1111d1, 0x0}, + { 0x11118c, 0x0}, + { 0x11118d, 0x0}, + { 0x1110c0, 0x0}, + { 0x1110c1, 0x0}, + { 0x1111c0, 0x0}, + { 0x1111c1, 0x0}, + { 0x1112c0, 0x0}, + { 0x1112c1, 0x0}, + { 0x1113c0, 0x0}, + { 0x1113c1, 0x0}, + { 0x1114c0, 0x0}, + { 0x1114c1, 0x0}, + { 0x1115c0, 0x0}, + { 0x1115c1, 0x0}, + { 0x1116c0, 0x0}, + { 0x1116c1, 0x0}, + { 0x1117c0, 0x0}, + { 0x1117c1, 0x0}, + { 0x1118c0, 0x0}, + { 0x1118c1, 0x0}, + { 0x1110ae, 0x0}, + { 0x1110af, 0x0}, + { 0x190201, 0x0}, + { 0x190202, 0x0}, + { 0x190203, 0x0}, + { 0x190205, 0x0}, + { 0x190206, 0x0}, + { 0x190207, 0x0}, + { 0x190208, 0x0}, + { 0x120020, 0x0}, + { 0x200080, 0x0}, + { 0x201080, 0x0}, + { 0x202080, 0x0}, + { 0x210020, 0x0}, + { 0x210080, 0x0}, + { 0x210081, 0x0}, + { 0x2100d0, 0x0}, + { 0x2100d1, 0x0}, + { 0x21008c, 0x0}, + { 0x21008d, 0x0}, + { 0x210180, 0x0}, + { 0x210181, 0x0}, + { 0x2101d0, 0x0}, + { 0x2101d1, 0x0}, + { 0x21018c, 0x0}, + { 0x21018d, 0x0}, + { 0x2100c0, 0x0}, + { 0x2100c1, 0x0}, + { 0x2101c0, 0x0}, + { 0x2101c1, 0x0}, + { 0x2102c0, 0x0}, + { 0x2102c1, 0x0}, + { 0x2103c0, 0x0}, + { 0x2103c1, 0x0}, + { 0x2104c0, 0x0}, + { 0x2104c1, 0x0}, + { 0x2105c0, 0x0}, + { 0x2105c1, 0x0}, + { 0x2106c0, 0x0}, + { 0x2106c1, 0x0}, + { 0x2107c0, 0x0}, + { 0x2107c1, 0x0}, + { 0x2108c0, 0x0}, + { 0x2108c1, 0x0}, + { 0x2100ae, 0x0}, + { 0x2100af, 0x0}, + { 0x211020, 0x0}, + { 0x211080, 0x0}, + { 0x211081, 0x0}, + { 0x2110d0, 0x0}, + { 0x2110d1, 0x0}, + { 0x21108c, 0x0}, + { 0x21108d, 0x0}, + { 0x211180, 0x0}, + { 0x211181, 0x0}, + { 0x2111d0, 0x0}, + { 0x2111d1, 0x0}, + { 0x21118c, 0x0}, + { 0x21118d, 0x0}, + { 0x2110c0, 0x0}, + { 0x2110c1, 0x0}, + { 0x2111c0, 0x0}, + { 0x2111c1, 0x0}, + { 0x2112c0, 0x0}, + { 0x2112c1, 0x0}, + { 0x2113c0, 0x0}, + { 0x2113c1, 0x0}, + { 0x2114c0, 0x0}, + { 0x2114c1, 0x0}, + { 0x2115c0, 0x0}, + { 0x2115c1, 0x0}, + { 0x2116c0, 0x0}, + { 0x2116c1, 0x0}, + { 0x2117c0, 0x0}, + { 0x2117c1, 0x0}, + { 0x2118c0, 0x0}, + { 0x2118c1, 0x0}, + { 0x2110ae, 0x0}, + { 0x2110af, 0x0}, + { 0x290201, 0x0}, + { 0x290202, 0x0}, + { 0x290203, 0x0}, + { 0x290205, 0x0}, + { 0x290206, 0x0}, + { 0x290207, 0x0}, + { 0x290208, 0x0}, + { 0x220020, 0x0}, + { 0x20077, 0x0}, + { 0x20072, 0x0}, + { 0x20073, 0x0}, + { 0x400c0, 0x0}, + { 0x10040, 0x0}, + { 0x10140, 0x0}, + { 0x10240, 0x0}, + { 0x10340, 0x0}, + { 0x10440, 0x0}, + { 0x10540, 0x0}, + { 0x10640, 0x0}, + { 0x10740, 0x0}, + { 0x10840, 0x0}, + { 0x11040, 0x0}, + { 0x11140, 0x0}, + { 0x11240, 0x0}, + { 0x11340, 0x0}, + { 0x11440, 0x0}, + { 0x11540, 0x0}, + { 0x11640, 0x0}, + { 0x11740, 0x0}, + { 0x11840, 0x0}, +}; + +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0}, + { 0x54003, 0xe94}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x131f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x36e4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x36e4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xe400}, + { 0x54033, 0x3236}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xe400}, + { 0x54039, 0x3236}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0}, + { 0x54002, 0x1}, + { 0x54003, 0x74a}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x121f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x1bb4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x1bb4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xb400}, + { 0x54033, 0x321b}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xb400}, + { 0x54039, 0x321b}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0}, + { 0x54002, 0x102}, + { 0x54003, 0x270}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x121f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x994}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1100}, + { 0x5401e, 0x4}, + { 0x5401f, 0x994}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1100}, + { 0x54024, 0x4}, + { 0x54032, 0x9400}, + { 0x54033, 0x3209}, + { 0x54034, 0x2600}, + { 0x54035, 0x11}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0x9400}, + { 0x54039, 0x3209}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x11}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0}, + { 0x54003, 0xe94}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x61}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54010, 0x2080}, + { 0x54012, 0x310}, + { 0x54019, 0x36e4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x36e4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xe400}, + { 0x54033, 0x3236}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xe400}, + { 0x54039, 0x3236}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0}, + { 0x90000, 0x10}, + { 0x90001, 0x400}, + { 0x90002, 0x10e}, + { 0x90003, 0x0}, + { 0x90004, 0x0}, + { 0x90005, 0x8}, + { 0x90029, 0xb}, + { 0x9002a, 0x480}, + { 0x9002b, 0x109}, + { 0x9002c, 0x8}, + { 0x9002d, 0x448}, + { 0x9002e, 0x139}, + { 0x9002f, 0x8}, + { 0x90030, 0x478}, + { 0x90031, 0x109}, + { 0x90032, 0x0}, + { 0x90033, 0xe8}, + { 0x90034, 0x109}, + { 0x90035, 0x2}, + { 0x90036, 0x10}, + { 0x90037, 0x139}, + { 0x90038, 0xb}, + { 0x90039, 0x7c0}, + { 0x9003a, 0x139}, + { 0x9003b, 0x44}, + { 0x9003c, 0x633}, + { 0x9003d, 0x159}, + { 0x9003e, 0x14f}, + { 0x9003f, 0x630}, + { 0x90040, 0x159}, + { 0x90041, 0x47}, + { 0x90042, 0x633}, + { 0x90043, 0x149}, + { 0x90044, 0x4f}, + { 0x90045, 0x633}, + { 0x90046, 0x179}, + { 0x90047, 0x8}, + { 0x90048, 0xe0}, + { 0x90049, 0x109}, + { 0x9004a, 0x0}, + { 0x9004b, 0x7c8}, + { 0x9004c, 0x109}, + { 0x9004d, 0x0}, + { 0x9004e, 0x1}, + { 0x9004f, 0x8}, + { 0x90050, 0x30}, + { 0x90051, 0x65a}, + { 0x90052, 0x9}, + { 0x90053, 0x0}, + { 0x90054, 0x45a}, + { 0x90055, 0x9}, + { 0x90056, 0x0}, + { 0x90057, 0x448}, + { 0x90058, 0x109}, + { 0x90059, 0x40}, + { 0x9005a, 0x633}, + { 0x9005b, 0x179}, + { 0x9005c, 0x1}, + { 0x9005d, 0x618}, + { 0x9005e, 0x109}, + { 0x9005f, 0x40c0}, + { 0x90060, 0x633}, + { 0x90061, 0x149}, + { 0x90062, 0x8}, + { 0x90063, 0x4}, + { 0x90064, 0x48}, + { 0x90065, 0x4040}, + { 0x90066, 0x633}, + { 0x90067, 0x149}, + { 0x90068, 0x0}, + { 0x90069, 0x4}, + { 0x9006a, 0x48}, + { 0x9006b, 0x40}, + { 0x9006c, 0x633}, + { 0x9006d, 0x149}, + { 0x9006e, 0x0}, + { 0x9006f, 0x658}, + { 0x90070, 0x109}, + { 0x90071, 0x10}, + { 0x90072, 0x4}, + { 0x90073, 0x18}, + { 0x90074, 0x0}, + { 0x90075, 0x4}, + { 0x90076, 0x78}, + { 0x90077, 0x549}, + { 0x90078, 0x633}, + { 0x90079, 0x159}, + { 0x9007a, 0xd49}, + { 0x9007b, 0x633}, + { 0x9007c, 0x159}, + { 0x9007d, 0x94a}, + { 0x9007e, 0x633}, + { 0x9007f, 0x159}, + { 0x90080, 0x441}, + { 0x90081, 0x633}, + { 0x90082, 0x149}, + { 0x90083, 0x42}, + { 0x90084, 0x633}, + { 0x90085, 0x149}, + { 0x90086, 0x1}, + { 0x90087, 0x633}, + { 0x90088, 0x149}, + { 0x90089, 0x0}, + { 0x9008a, 0xe0}, + { 0x9008b, 0x109}, + { 0x9008c, 0xa}, + { 0x9008d, 0x10}, + { 0x9008e, 0x109}, + { 0x9008f, 0x9}, + { 0x90090, 0x3c0}, + { 0x90091, 0x149}, + { 0x90092, 0x9}, + { 0x90093, 0x3c0}, + { 0x90094, 0x159}, + { 0x90095, 0x18}, + { 0x90096, 0x10}, + { 0x90097, 0x109}, + { 0x90098, 0x0}, + { 0x90099, 0x3c0}, + { 0x9009a, 0x109}, + { 0x9009b, 0x18}, + { 0x9009c, 0x4}, + { 0x9009d, 0x48}, + { 0x9009e, 0x18}, + { 0x9009f, 0x4}, + { 0x900a0, 0x58}, + { 0x900a1, 0xb}, + { 0x900a2, 0x10}, + { 0x900a3, 0x109}, + { 0x900a4, 0x1}, + { 0x900a5, 0x10}, + { 0x900a6, 0x109}, + { 0x900a7, 0x5}, + { 0x900a8, 0x7c0}, + { 0x900a9, 0x109}, + { 0x40000, 0x811}, + { 0x40020, 0x880}, + { 0x40040, 0x0}, + { 0x40060, 0x0}, + { 0x40001, 0x4008}, + { 0x40021, 0x83}, + { 0x40041, 0x4f}, + { 0x40061, 0x0}, + { 0x40002, 0x4040}, + { 0x40022, 0x83}, + { 0x40042, 0x51}, + { 0x40062, 0x0}, + { 0x40003, 0x811}, + { 0x40023, 0x880}, + { 0x40043, 0x0}, + { 0x40063, 0x0}, + { 0x40004, 0x720}, + { 0x40024, 0xf}, + { 0x40044, 0x1740}, + { 0x40064, 0x0}, + { 0x40005, 0x16}, + { 0x40025, 0x83}, + { 0x40045, 0x4b}, + { 0x40065, 0x0}, + { 0x40006, 0x716}, + { 0x40026, 0xf}, + { 0x40046, 0x2001}, + { 0x40066, 0x0}, + { 0x40007, 0x716}, + { 0x40027, 0xf}, + { 0x40047, 0x2800}, + { 0x40067, 0x0}, + { 0x40008, 0x716}, + { 0x40028, 0xf}, + { 0x40048, 0xf00}, + { 0x40068, 0x0}, + { 0x40009, 0x720}, + { 0x40029, 0xf}, + { 0x40049, 0x1400}, + { 0x40069, 0x0}, + { 0x4000a, 0xe08}, + { 0x4002a, 0xc15}, + { 0x4004a, 0x0}, + { 0x4006a, 0x0}, + { 0x4000b, 0x625}, + { 0x4002b, 0x15}, + { 0x4004b, 0x0}, + { 0x4006b, 0x0}, + { 0x4000c, 0x4028}, + { 0x4002c, 0x80}, + { 0x4004c, 0x0}, + { 0x4006c, 0x0}, + { 0x4000d, 0xe08}, + { 0x4002d, 0xc1a}, + { 0x4004d, 0x0}, + { 0x4006d, 0x0}, + { 0x4000e, 0x625}, + { 0x4002e, 0x1a}, + { 0x4004e, 0x0}, + { 0x4006e, 0x0}, + { 0x4000f, 0x4040}, + { 0x4002f, 0x80}, + { 0x4004f, 0x0}, + { 0x4006f, 0x0}, + { 0x40010, 0x2604}, + { 0x40030, 0x15}, + { 0x40050, 0x0}, + { 0x40070, 0x0}, + { 0x40011, 0x708}, + { 0x40031, 0x5}, + { 0x40051, 0x0}, + { 0x40071, 0x2002}, + { 0x40012, 0x8}, + { 0x40032, 0x80}, + { 0x40052, 0x0}, + { 0x40072, 0x0}, + { 0x40013, 0x2604}, + { 0x40033, 0x1a}, + { 0x40053, 0x0}, + { 0x40073, 0x0}, + { 0x40014, 0x708}, + { 0x40034, 0xa}, + { 0x40054, 0x0}, + { 0x40074, 0x2002}, + { 0x40015, 0x4040}, + { 0x40035, 0x80}, + { 0x40055, 0x0}, + { 0x40075, 0x0}, + { 0x40016, 0x60a}, + { 0x40036, 0x15}, + { 0x40056, 0x1200}, + { 0x40076, 0x0}, + { 0x40017, 0x61a}, + { 0x40037, 0x15}, + { 0x40057, 0x1300}, + { 0x40077, 0x0}, + { 0x40018, 0x60a}, + { 0x40038, 0x1a}, + { 0x40058, 0x1200}, + { 0x40078, 0x0}, + { 0x40019, 0x642}, + { 0x40039, 0x1a}, + { 0x40059, 0x1300}, + { 0x40079, 0x0}, + { 0x4001a, 0x4808}, + { 0x4003a, 0x880}, + { 0x4005a, 0x0}, + { 0x4007a, 0x0}, + { 0x900aa, 0x0}, + { 0x900ab, 0x790}, + { 0x900ac, 0x11a}, + { 0x900ad, 0x8}, + { 0x900ae, 0x7aa}, + { 0x900af, 0x2a}, + { 0x900b0, 0x10}, + { 0x900b1, 0x7b2}, + { 0x900b2, 0x2a}, + { 0x900b3, 0x0}, + { 0x900b4, 0x7c8}, + { 0x900b5, 0x109}, + { 0x900b6, 0x10}, + { 0x900b7, 0x10}, + { 0x900b8, 0x109}, + { 0x900b9, 0x10}, + { 0x900ba, 0x2a8}, + { 0x900bb, 0x129}, + { 0x900bc, 0x8}, + { 0x900bd, 0x370}, + { 0x900be, 0x129}, + { 0x900bf, 0xa}, + { 0x900c0, 0x3c8}, + { 0x900c1, 0x1a9}, + { 0x900c2, 0xc}, + { 0x900c3, 0x408}, + { 0x900c4, 0x199}, + { 0x900c5, 0x14}, + { 0x900c6, 0x790}, + { 0x900c7, 0x11a}, + { 0x900c8, 0x8}, + { 0x900c9, 0x4}, + { 0x900ca, 0x18}, + { 0x900cb, 0xe}, + { 0x900cc, 0x408}, + { 0x900cd, 0x199}, + { 0x900ce, 0x8}, + { 0x900cf, 0x8568}, + { 0x900d0, 0x108}, + { 0x900d1, 0x18}, + { 0x900d2, 0x790}, + { 0x900d3, 0x16a}, + { 0x900d4, 0x8}, + { 0x900d5, 0x1d8}, + { 0x900d6, 0x169}, + { 0x900d7, 0x10}, + { 0x900d8, 0x8558}, + { 0x900d9, 0x168}, + { 0x900da, 0x1ff8}, + { 0x900db, 0x85a8}, + { 0x900dc, 0x1e8}, + { 0x900dd, 0x50}, + { 0x900de, 0x798}, + { 0x900df, 0x16a}, + { 0x900e0, 0x60}, + { 0x900e1, 0x7a0}, + { 0x900e2, 0x16a}, + { 0x900e3, 0x8}, + { 0x900e4, 0x8310}, + { 0x900e5, 0x168}, + { 0x900e6, 0x8}, + { 0x900e7, 0xa310}, + { 0x900e8, 0x168}, + { 0x900e9, 0xa}, + { 0x900ea, 0x408}, + { 0x900eb, 0x169}, + { 0x900ec, 0x6e}, + { 0x900ed, 0x0}, + { 0x900ee, 0x68}, + { 0x900ef, 0x0}, + { 0x900f0, 0x408}, + { 0x900f1, 0x169}, + { 0x900f2, 0x0}, + { 0x900f3, 0x8310}, + { 0x900f4, 0x168}, + { 0x900f5, 0x0}, + { 0x900f6, 0xa310}, + { 0x900f7, 0x168}, + { 0x900f8, 0x1ff8}, + { 0x900f9, 0x85a8}, + { 0x900fa, 0x1e8}, + { 0x900fb, 0x68}, + { 0x900fc, 0x798}, + { 0x900fd, 0x16a}, + { 0x900fe, 0x78}, + { 0x900ff, 0x7a0}, + { 0x90100, 0x16a}, + { 0x90101, 0x68}, + { 0x90102, 0x790}, + { 0x90103, 0x16a}, + { 0x90104, 0x8}, + { 0x90105, 0x8b10}, + { 0x90106, 0x168}, + { 0x90107, 0x8}, + { 0x90108, 0xab10}, + { 0x90109, 0x168}, + { 0x9010a, 0xa}, + { 0x9010b, 0x408}, + { 0x9010c, 0x169}, + { 0x9010d, 0x58}, + { 0x9010e, 0x0}, + { 0x9010f, 0x68}, + { 0x90110, 0x0}, + { 0x90111, 0x408}, + { 0x90112, 0x169}, + { 0x90113, 0x0}, + { 0x90114, 0x8b10}, + { 0x90115, 0x168}, + { 0x90116, 0x1}, + { 0x90117, 0xab10}, + { 0x90118, 0x168}, + { 0x90119, 0x0}, + { 0x9011a, 0x1d8}, + { 0x9011b, 0x169}, + { 0x9011c, 0x80}, + { 0x9011d, 0x790}, + { 0x9011e, 0x16a}, + { 0x9011f, 0x18}, + { 0x90120, 0x7aa}, + { 0x90121, 0x6a}, + { 0x90122, 0xa}, + { 0x90123, 0x0}, + { 0x90124, 0x1e9}, + { 0x90125, 0x8}, + { 0x90126, 0x8080}, + { 0x90127, 0x108}, + { 0x90128, 0xf}, + { 0x90129, 0x408}, + { 0x9012a, 0x169}, + { 0x9012b, 0xc}, + { 0x9012c, 0x0}, + { 0x9012d, 0x68}, + { 0x9012e, 0x9}, + { 0x9012f, 0x0}, + { 0x90130, 0x1a9}, + { 0x90131, 0x0}, + { 0x90132, 0x408}, + { 0x90133, 0x169}, + { 0x90134, 0x0}, + { 0x90135, 0x8080}, + { 0x90136, 0x108}, + { 0x90137, 0x8}, + { 0x90138, 0x7aa}, + { 0x90139, 0x6a}, + { 0x9013a, 0x0}, + { 0x9013b, 0x8568}, + { 0x9013c, 0x108}, + { 0x9013d, 0xb7}, + { 0x9013e, 0x790}, + { 0x9013f, 0x16a}, + { 0x90140, 0x1f}, + { 0x90141, 0x0}, + { 0x90142, 0x68}, + { 0x90143, 0x8}, + { 0x90144, 0x8558}, + { 0x90145, 0x168}, + { 0x90146, 0xf}, + { 0x90147, 0x408}, + { 0x90148, 0x169}, + { 0x90149, 0xd}, + { 0x9014a, 0x0}, + { 0x9014b, 0x68}, + { 0x9014c, 0x0}, + { 0x9014d, 0x408}, + { 0x9014e, 0x169}, + { 0x9014f, 0x0}, + { 0x90150, 0x8558}, + { 0x90151, 0x168}, + { 0x90152, 0x8}, + { 0x90153, 0x3c8}, + { 0x90154, 0x1a9}, + { 0x90155, 0x3}, + { 0x90156, 0x370}, + { 0x90157, 0x129}, + { 0x90158, 0x20}, + { 0x90159, 0x2aa}, + { 0x9015a, 0x9}, + { 0x9015b, 0x8}, + { 0x9015c, 0xe8}, + { 0x9015d, 0x109}, + { 0x9015e, 0x0}, + { 0x9015f, 0x8140}, + { 0x90160, 0x10c}, + { 0x90161, 0x10}, + { 0x90162, 0x8138}, + { 0x90163, 0x104}, + { 0x90164, 0x8}, + { 0x90165, 0x448}, + { 0x90166, 0x109}, + { 0x90167, 0xf}, + { 0x90168, 0x7c0}, + { 0x90169, 0x109}, + { 0x9016a, 0x0}, + { 0x9016b, 0xe8}, + { 0x9016c, 0x109}, + { 0x9016d, 0x47}, + { 0x9016e, 0x630}, + { 0x9016f, 0x109}, + { 0x90170, 0x8}, + { 0x90171, 0x618}, + { 0x90172, 0x109}, + { 0x90173, 0x8}, + { 0x90174, 0xe0}, + { 0x90175, 0x109}, + { 0x90176, 0x0}, + { 0x90177, 0x7c8}, + { 0x90178, 0x109}, + { 0x90179, 0x8}, + { 0x9017a, 0x8140}, + { 0x9017b, 0x10c}, + { 0x9017c, 0x0}, + { 0x9017d, 0x478}, + { 0x9017e, 0x109}, + { 0x9017f, 0x0}, + { 0x90180, 0x1}, + { 0x90181, 0x8}, + { 0x90182, 0x8}, + { 0x90183, 0x4}, + { 0x90184, 0x0}, + { 0x90006, 0x8}, + { 0x90007, 0x7c8}, + { 0x90008, 0x109}, + { 0x90009, 0x0}, + { 0x9000a, 0x400}, + { 0x9000b, 0x106}, + { 0xd00e7, 0x400}, + { 0x90017, 0x0}, + { 0x9001f, 0x2b}, + { 0x90026, 0x69}, + { 0x400d0, 0x0}, + { 0x400d1, 0x101}, + { 0x400d2, 0x105}, + { 0x400d3, 0x107}, + { 0x400d4, 0x10f}, + { 0x400d5, 0x202}, + { 0x400d6, 0x20a}, + { 0x400d7, 0x20b}, + { 0x2003a, 0x2}, + { 0x200be, 0x3}, + { 0x2000b, 0x75}, + { 0x2000c, 0xe9}, + { 0x2000d, 0x91c}, + { 0x2000e, 0x2c}, + { 0x12000b, 0x3b}, + { 0x12000c, 0x74}, + { 0x12000d, 0x48e}, + { 0x12000e, 0x2c}, + { 0x22000b, 0x14}, + { 0x22000c, 0x27}, + { 0x22000d, 0x186}, + { 0x22000e, 0x10}, + { 0x9000c, 0x0}, + { 0x9000d, 0x173}, + { 0x9000e, 0x60}, + { 0x9000f, 0x6110}, + { 0x90010, 0x2152}, + { 0x90011, 0xdfbd}, + { 0x90012, 0x2060}, + { 0x90013, 0x6152}, + { 0x20010, 0x5a}, + { 0x20011, 0x3}, + { 0x120010, 0x5a}, + { 0x120011, 0x3}, + { 0x40080, 0xe0}, + { 0x40081, 0x12}, + { 0x40082, 0xe0}, + { 0x40083, 0x12}, + { 0x40084, 0xe0}, + { 0x40085, 0x12}, + { 0x140080, 0xe0}, + { 0x140081, 0x12}, + { 0x140082, 0xe0}, + { 0x140083, 0x12}, + { 0x140084, 0xe0}, + { 0x140085, 0x12}, + { 0x240080, 0xe0}, + { 0x240081, 0x12}, + { 0x240082, 0xe0}, + { 0x240083, 0x12}, + { 0x240084, 0xe0}, + { 0x240085, 0x12}, + { 0x400fd, 0xf}, + { 0x400f1, 0xe}, + { 0x10011, 0x1}, + { 0x10012, 0x1}, + { 0x10013, 0x180}, + { 0x10018, 0x1}, + { 0x10002, 0x6209}, + { 0x100b2, 0x1}, + { 0x101b4, 0x1}, + { 0x102b4, 0x1}, + { 0x103b4, 0x1}, + { 0x104b4, 0x1}, + { 0x105b4, 0x1}, + { 0x106b4, 0x1}, + { 0x107b4, 0x1}, + { 0x108b4, 0x1}, + { 0x11011, 0x1}, + { 0x11012, 0x1}, + { 0x11013, 0x180}, + { 0x11018, 0x1}, + { 0x11002, 0x6209}, + { 0x110b2, 0x1}, + { 0x111b4, 0x1}, + { 0x112b4, 0x1}, + { 0x113b4, 0x1}, + { 0x114b4, 0x1}, + { 0x115b4, 0x1}, + { 0x116b4, 0x1}, + { 0x117b4, 0x1}, + { 0x118b4, 0x1}, + { 0x20089, 0x1}, + { 0x20088, 0x19}, + { 0xc0080, 0x0}, + /* workaround STAR_3256585 marker */ + { 0x2000b, 0x41a}, + /* workaround STAR_3256585 marker */ + { 0x12000b, 0x20d}, + /* workaround STAR_3256585 marker */ + { 0x22000b, 0xb0}, + { 0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2CS_2GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx93_frdm/spl.c b/board/nxp/imx93_frdm/spl.c index 068091ba0e9..40054ff72d0 100644 --- a/board/nxp/imx93_frdm/spl.c +++ b/board/nxp/imx93_frdm/spl.c @@ -33,9 +33,10 @@ static struct _drams { u8 mr8; struct dram_timing_info *pdram_timing; char *name; -} frdm_drams[2] = { +} frdm_drams[3] = { {0x10, &dram_timing_1GB, "1GB DRAM" }, - {0x18, &dram_timing_2GB, "2GB DRAM" }, + {0x12, &dram_timing_2CS_2GB, "2CS_2GB DRAM" }, + {0x18, &dram_timing_1CS_2GB, "1CS_2GB DRAM" }, }; int spl_board_boot_device(enum boot_device boot_dev_spl) diff --git a/board/nxp/imx93_qsb/imx93_qsb.env b/board/nxp/imx93_qsb/imx93_qsb.env index d669c6e3133..d14a1b6c9bd 100644 --- a/board/nxp/imx93_qsb/imx93_qsb.env +++ b/board/nxp/imx93_qsb/imx93_qsb.env @@ -10,6 +10,10 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw diff --git a/board/nxp/imx94_evk/imx94_evk.env b/board/nxp/imx94_evk/imx94_evk.env index 894f5975812..c2006c95529 100644 --- a/board/nxp/imx94_evk/imx94_evk.env +++ b/board/nxp/imx94_evk/imx94_evk.env @@ -19,7 +19,10 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 +ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 image=Image splashimage=0xA0000000 console=ttyLP0,115200 earlycon diff --git a/board/nxp/imx952_evk/imx952_evk.env b/board/nxp/imx952_evk/imx952_evk.env index 6ecaf9724c1..07faeb9fc9a 100644 --- a/board/nxp/imx952_evk/imx952_evk.env +++ b/board/nxp/imx952_evk/imx952_evk.env @@ -52,7 +52,10 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 +ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 image=Image splashimage=0xA0000000 console=ttyLP0,115200 earlycon diff --git a/board/nxp/imx95_evk/imx95_evk.env b/board/nxp/imx95_evk/imx95_evk.env index 19f9bd5c16e..1d63a74aefa 100644 --- a/board/nxp/imx95_evk/imx95_evk.env +++ b/board/nxp/imx95_evk/imx95_evk.env @@ -3,8 +3,11 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 -kernel_addr_r=CONFIG_SYS_LOAD_ADDR image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 splashimage=0xA0000000 console=ttyLP0,115200 earlycon fdt_addr_r=0x93000000 diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.env b/board/nxp/mx6sabreauto/mx6sabreauto.env new file mode 100644 index 00000000000..31a16905ef5 --- /dev/null +++ b/board/nxp/mx6sabreauto/mx6sabreauto.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc3 + +#include <env/nxp/mx6sabre_common.env> diff --git a/board/nxp/mx6sabresd/mx6sabresd.env b/board/nxp/mx6sabresd/mx6sabresd.env new file mode 100644 index 00000000000..3608e931665 --- /dev/null +++ b/board/nxp/mx6sabresd/mx6sabresd.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc0 + +#include <env/nxp/mx6sabre_common.env> diff --git a/board/nxp/mx6ullevk/mx6ullevk.env b/board/nxp/mx6ullevk/mx6ullevk.env new file mode 100644 index 00000000000..0fce3aaaa4e --- /dev/null +++ b/board/nxp/mx6ullevk/mx6ullevk.env @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttymxc0 +initrd_high=0xffffffff +fdt_file=undefined +fdt_addr=0x83000000 +boot_fdt=try +ip_dyn=yes +videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +findfdt=if test $fdt_file = undefined; then + if test $board_name = ULZ-EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ulz-14x14-evk.dtb; + fi; + if test $board_name = EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ull-14x14-evk.dtb; + fi; + if test $fdt_file = undefined; then + echo WARNING: Could not determine dtb to use; + fi; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/board/nxp/mx7ulp_evk/mx7ulp_evk.env b/board/nxp/mx7ulp_evk/mx7ulp_evk.env new file mode 100644 index 00000000000..f5a384a61de --- /dev/null +++ b/board/nxp/mx7ulp_evk/mx7ulp_evk.env @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttyLP0 +initrd_high=0xffffffff +fdt_file=imx7ulp-evk.dtb +fdt_addr=0x63000000 +boot_fdt=try +earlycon=lpuart32,0x402D0010 +ip_dyn=yes +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk0p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + usb start; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/board/toradex/aquila-imx95/Kconfig b/board/toradex/aquila-imx95/Kconfig new file mode 100644 index 00000000000..5936946e1af --- /dev/null +++ b/board/toradex/aquila-imx95/Kconfig @@ -0,0 +1,36 @@ +if TARGET_AQUILA_IMX95 + +config SYS_BOARD + default "aquila-imx95" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "aquila-imx95" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/aquila-imx95/MAINTAINERS b/board/toradex/aquila-imx95/MAINTAINERS new file mode 100644 index 00000000000..d2a74a53f5e --- /dev/null +++ b/board/toradex/aquila-imx95/MAINTAINERS @@ -0,0 +1,11 @@ +Aquila iMX95 +F: arch/arm/dts/imx95-aquila.dtsi +F: arch/arm/dts/imx95-aquila-dev.dts +F: arch/arm/dts/imx95-aquila-dev-u-boot.dtsi +F: board/toradex/aquila-imx95/ +F: configs/aquila-imx95_defconfig +F: doc/board/toradex/aquila-imx95.rst +F: include/configs/aquila-imx95.h +M: Francesco Dolcini <francesco.dolcini@toradex.com> +S: Maintained +W: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 diff --git a/board/toradex/aquila-imx95/Makefile b/board/toradex/aquila-imx95/Makefile new file mode 100644 index 00000000000..caaf09465c8 --- /dev/null +++ b/board/toradex/aquila-imx95/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (c) Toradex + +obj-y += aquila-imx95.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/toradex/aquila-imx95/aquila-imx95.c b/board/toradex/aquila-imx95/aquila-imx95.c new file mode 100644 index 00000000000..0c6473e4b3a --- /dev/null +++ b/board/toradex/aquila-imx95/aquila-imx95.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <fdt_support.h> +#include <init.h> + +#include "../common/tdx-cfg-block.h" + +int board_phys_sdram_size(phys_size_t *size) +{ + *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + + return 0; +} + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif diff --git a/board/toradex/aquila-imx95/aquila-imx95.env b/board/toradex/aquila-imx95/aquila-imx95.env new file mode 100644 index 00000000000..5ca6cb18aaa --- /dev/null +++ b/board/toradex/aquila-imx95/aquila-imx95.env @@ -0,0 +1,20 @@ +boot_scripts=boot.scr +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyLP2 +fdt_board=dev +fdt_addr=0x9c400000 +fdt_addr_r=0x9c400000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x94400000 +kernel_comp_size=0x8000000 +ramdisk_addr_r=0x9c800000 +scriptaddr=0x9c600000 + +update_uboot= + askenv confirm Did you load flash.bin (y/N)?; + if test "$confirm" = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt + ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 + ${blkcnt}; + fi diff --git a/board/toradex/aquila-imx95/spl.c b/board/toradex/aquila-imx95/spl.c new file mode 100644 index 00000000000..9f501c11c1d --- /dev/null +++ b/board/toradex/aquila-imx95/spl.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/sections.h> +#include <asm/global_data.h> +#include <clk.h> +#include <dm/uclass.h> +#include <hang.h> +#include <i2c.h> +#include <init.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION)) + spl_save_restore_data(); + + timer_init(); + + /* Need dm_init() to run before any SCMI calls */ + spl_early_init(); + + /* Need to enable SCMI drivers and ELE driver before console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* MU not probed, nothing can be outputed, hang */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/configs/aquila-imx95_defconfig b/configs/aquila-imx95_defconfig new file mode 100644 index 00000000000..bb3d475ef4d --- /dev/null +++ b/configs/aquila-imx95_defconfig @@ -0,0 +1,186 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x90200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx95-aquila-dev" +CONFIG_TARGET_AQUILA_IMX95=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x204d6000 +CONFIG_SPL_TEXT_BASE=0x20480000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x204d6000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x90400000 +CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 +CONFIG_SPL=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_PCI=y +CONFIG_SYS_MEMTEST_START=0x90000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTDELAY=1 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan -b" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n \"${fdtfile}\" || setenv fdtfile imx95-aquila-${fdt_board}.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_LOG=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set +CONFIG_PCI_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/scmi/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="Aquila iMX95 # " +CONFIG_CMD_ASKENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_READ=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_UUID=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_SCMI=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_VERSION_VARIABLE=y +CONFIG_PROT_UDP=y +CONFIG_IP_DEFRAG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x90400000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_SPL_FIRMWARE=y +# CONFIG_SCMI_AGENT_SMCCC is not set +CONFIG_IMX_SM_CPU=y +CONFIG_IMX_SM_LMM=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_IMX_MU_MBOX=y +CONFIG_I2C_EEPROM=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_MDIO=y +CONFIG_MII=y +CONFIG_FSL_ENETC=y +CONFIG_PHYLIB=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX_SCMI=y +CONFIG_POWER_DOMAIN=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REMOTEPROC_IMX=y +CONFIG_DM_RNG=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_USB_GADGET_OS_DESCRIPTORS=y +CONFIG_SDP_LOADADDR=0x90400000 +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_SHA1 is not set +CONFIG_LZO=y diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index 4039ef298d3..20294756d90 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -136,7 +136,6 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_TPM2_TIS_SPI=y CONFIG_TPM2_FTPM_TEE=y CONFIG_USB=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index 489d1ff2d32..ccd7bf6ed8e 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -139,7 +139,6 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_TPM2_TIS_SPI=y CONFIG_TPM2_FTPM_TEE=y CONFIG_USB=y diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index 2db503652ee..d84d60a7baf 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -88,4 +88,3 @@ CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y -CONFIG_DM_THERMAL=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 7650d7b734d..82fdd16c4d6 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -88,4 +88,3 @@ CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y -CONFIG_DM_THERMAL=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index f8a7d6060ee..3f954976c0a 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -149,7 +149,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index e34f12cabf3..9dc7fe21820 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -105,5 +105,4 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 04daa0040c1..32339e7f6e2 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -135,7 +135,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig index 6017f50e51e..8c66fad7390 100644 --- a/configs/imx8mm_beacon_fspi_defconfig +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -133,7 +133,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 7521df31f2f..05ecaeaebe4 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -18,7 +18,7 @@ CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x40400000 CONFIG_SPL=y CONFIG_EFI_MM_COMM_TEE=y CONFIG_EFI_VAR_BUF_SIZE=139264 @@ -71,6 +71,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y @@ -120,7 +121,6 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index 8ab6ee24b23..6d531efc5f7 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -21,7 +21,7 @@ CONFIG_SPL_TEXT_BASE=0x7E2000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x40400000 CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 @@ -59,6 +59,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y @@ -107,7 +108,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y CONFIG_FSPI_CONF_HEADER=y CONFIG_FSPI_CONF_FILE="fspi_header.bin" diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig index c99b8e22bac..26bb5c12f02 100644 --- a/configs/imx8mm_phg_defconfig +++ b/configs/imx8mm_phg_defconfig @@ -103,7 +103,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 0cde12d9d78..d9d1b7c6e71 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -157,7 +157,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y # CONFIG_TPM_V1 is not set CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index fd80c3065ed..83db14dc5bc 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -131,7 +131,6 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index bc2d6014b21..6a1be97318a 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -138,7 +138,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index 800f851edbc..662f8f902d0 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -137,7 +137,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 18c44e801f4..033d1670d47 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -62,6 +62,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y @@ -97,7 +98,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 3233686034b..b7bee8cf276 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -80,6 +80,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y @@ -126,6 +127,5 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y CONFIG_SHA384=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 54dce09bc9f..c5685c84d2a 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -152,7 +152,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y # CONFIG_TPM_V1 is not set CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y diff --git a/configs/imx8mp-libra-fpsc_defconfig b/configs/imx8mp-libra-fpsc_defconfig index 44f3c9fd796..142cbcf9888 100644 --- a/configs/imx8mp-libra-fpsc_defconfig +++ b/configs/imx8mp-libra-fpsc_defconfig @@ -156,7 +156,6 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index 1693264c9d6..8359f748244 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -152,7 +152,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 7af538ee367..12dcf3d1435 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -19,7 +19,7 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x98fc00 CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x40600000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x20400 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 @@ -75,6 +75,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index 401ad666011..eafaf4140be 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -159,7 +159,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index fdfd72fcd7b..6e8bb06d019 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -160,7 +160,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 49f0e0e829f..990d100f253 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -157,7 +157,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y # CONFIG_TPM_V1 is not set CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index 79c51191be0..9a8c16ccb19 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -94,6 +94,5 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y -CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y CONFIG_WDT=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 67a7f339816..cc40e7b9bf3 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -19,7 +19,7 @@ CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x180000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x40400000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_IMX_BOOTAUX=y @@ -70,6 +70,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y @@ -107,7 +108,6 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 64e3ee04293..9138bca067d 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -93,4 +93,3 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y -CONFIG_DM_THERMAL=y diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig index 23ee6278503..a63a01ba8d9 100644 --- a/configs/imx8mq_reform2_defconfig +++ b/configs/imx8mq_reform2_defconfig @@ -93,7 +93,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/imx952_evk_defconfig b/configs/imx952_evk_defconfig index b74df3a5d5f..9c12d2b32ac 100644 --- a/configs/imx952_evk_defconfig +++ b/configs/imx952_evk_defconfig @@ -35,7 +35,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" -CONFIG_DEFAULT_FDT_FILE="freescale/imx952-evk.dtb" +CONFIG_DEFAULT_FDT_FILE="imx952-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index f999ed073e8..1673cf7efad 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -192,7 +192,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y @@ -210,5 +209,4 @@ CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_SPL_USB_SDP_SUPPORT=y -# CONFIG_WATCHDOG_AUTOSTART is not set CONFIG_IMX_WATCHDOG=y diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index b216a0bb270..1b175670ffd 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -106,7 +106,6 @@ CONFIG_DM_RTC=y CONFIG_RTC_RV8803=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig index 7e450e2d356..72ffb72a137 100644 --- a/configs/librem5_defconfig +++ b/configs/librem5_defconfig @@ -130,7 +130,6 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 3767fdfb23b..10061a1ba4c 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -131,5 +131,4 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 2b2aa899632..a116c65a99e 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -162,7 +162,6 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index 2d5bfffa093..dc2263368ab 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -91,4 +91,3 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y -CONFIG_DM_THERMAL=y diff --git a/configs/toradex-smarc-imx8mp_defconfig b/configs/toradex-smarc-imx8mp_defconfig index c0185ed9ca5..7301d7a4ace 100644 --- a/configs/toradex-smarc-imx8mp_defconfig +++ b/configs/toradex-smarc-imx8mp_defconfig @@ -160,7 +160,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_DM_USB_GADGET=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index c8a2a057135..16e5ce7f406 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -145,7 +145,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 3c9dab36d90..778d56ad55d 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -162,7 +162,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_DM_USB_GADGET=y diff --git a/doc/board/toradex/aquila-imx95.rst b/doc/board/toradex/aquila-imx95.rst new file mode 100644 index 00000000000..edd40252657 --- /dev/null +++ b/doc/board/toradex/aquila-imx95.rst @@ -0,0 +1,175 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Toradex Aquila iMX95 Module +=========================== + +- SoM: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 +- Carrier board: https://www.toradex.com/products/carrier-board/aquila-development-board-kit + +Quick Start +----------- + +- Setup environment +- Get ahab-container.img +- Get DDR PHY Firmware Images +- Get and Build OEI Images +- Get and Build System Manager Image +- Get and Build the ARM Trusted Firmware +- Build the Bootloader Image +- Boot + +Setup environment +----------------- + +Suggested current toolchains are ARM 14.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads): + +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz + +.. code-block:: console + + $ export TOOLS=<path/to/directory/with/toolchains> + $ export CROSS_COMPILE_32=<path/to/arm/toolchain/bin/>arm-none-linux-gnueabihf- + $ export CROSS_COMPILE_64=<path/to/arm64/toolchain/bin/>aarch64-none-linux-gnu- + +Get ahab-container.img +---------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin + $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept + $ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree) + +Get DDR PHY Firmware Images +--------------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ sh firmware-imx-8.28-994fa14.bin --auto-accept + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr5*v202409.bin $(srctree) + +Get and Build OEI Images +------------------------ + +Note: `$srctree` is the U-Boot source directory +Get OEI from: https://git.toradex.com/cgit/imx-oei-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-oei-toradex.git/ + $ cd imx-oei-toradex + + $ make board=toradex-aquila-imx95 oei=ddr DEBUG=1 r=B0 all + $ cp build/toradex-aquila-imx95/ddr/oei-m33-ddr.bin $(srctree) + + $ make board=toradex-aquila-imx95 oei=tcm DEBUG=1 r=B0 all + $ cp build/toradex-aquila-imx95/tcm/oei-m33-tcm.bin $(srctree) + +The Makefile will set `DDR_CONFIG` automatically based on the selected silicon +revision. + +Get and Build the System Manager Image +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get System Manager from: https://git.toradex.com/cgit/imx-sm-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-sm-toradex.git/ + $ cd imx-sm-toradex + $ make config=aquila-imx95 all + $ cp build/aquila-imx95/m33_image.bin $(srctree) + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.12 + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ unset LDFLAGS + $ unset AS + $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git + $ cd imx-atf + $ make PLAT=imx95 bl31 + $ cp build/imx95/release/bl31.bin $(srctree) + +Build the Bootloader Image +-------------------------- + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ make aquila-imx95_defconfig + $ make + +Flash to eMMC +------------- + +.. code-block:: console + + > tftpboot ${loadaddr} flash.bin + > setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 + > mmc dev 0 1 && mmc write ${loadaddr} 0x0 ${blkcnt} + +As a convenience, instead of the last two commands, one may also use the update +U-Boot wrapper: + +.. code-block:: console + + > run update_uboot + +Boot +---- + +Boot sequence is: + +* SPL ---> ATF (TF-A) ---> U-Boot proper + +Output: + +.. code-block:: console + + U-Boot SPL 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200) + SYS Boot reason: por, origin: -1, errid: -1 + WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) + Trying to boot from MMC1 + Load image from MMC/SD 0xd2800 + NOTICE: BL31: v2.10.0 (release):lf-6.6.52-2.2.1-dirty + NOTICE: BL31: Built : 06:40:36, Jul 7 2025 + + + U-Boot 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200) + + CPU: NXP i.MX95 Rev2.0 A55 at 1800 MHz - invalid sensor data + DRAM: 7.8 GiB + Core: 321 devices, 30 uclasses, devicetree: separate + WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) + MMC: FSL_SDHC: 0, FSL_SDHC: 1 + Loading Environment from MMC... Reading from MMC(0)... OK + In: serial@44380000 + Out: serial@44380000 + Err: serial@44380000 + Model: Toradex 0098 Aquila iMX95 Hexa 8GB WB IT V1.0A + Serial#: 12594391 + + BuildInfo: + - ELE firmware version 2.0.2-c110ba4b + + Net: WARNING: no MAC address assigned for MAC0 + imx_get_mac_from_fuse: fuse read err: 0 + eth0: enetc-0 [PRIME] + Hit any key to stop autoboot: 0 + Aquila iMX95 # diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index 2a45bde6991..c5955ea1ad8 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -8,6 +8,7 @@ Toradex apalis-imx8 aquila-am69 + aquila-imx95 colibri_imx7 colibri-imx8x smarc-imx8mp diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index e692b9c2167..d30786a9e6c 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -228,20 +228,30 @@ static struct clk *_register_divider(struct udevice *dev, const char *name, return clk; } -struct clk *clk_register_divider(struct udevice *dev, const char *name, +struct clk *clk_register_divider_table(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags) + u8 clk_divider_flags, const struct clk_div_table *table) { struct clk *clk; clk = _register_divider(dev, name, parent_name, flags, reg, shift, - width, clk_divider_flags, NULL); + width, clk_divider_flags, table); if (IS_ERR(clk)) return ERR_CAST(clk); return clk; } +struct clk *clk_register_divider(struct udevice *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags) +{ + return clk_register_divider_table(dev, name, parent_name, flags, reg, + shift, width, clk_divider_flags, + NULL); +} + U_BOOT_DRIVER(ccf_clk_divider) = { .name = UBOOT_DM_CLK_CCF_DIVIDER, .id = UCLASS_CLK, diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index f57ac79f8ca..846b8011f5c 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -9,6 +9,7 @@ #include <log.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <dm/of_access.h> #include <dt-bindings/clock/imx6qdl-clock.h> #include "clk.h" @@ -46,6 +47,33 @@ static struct clk_ops imx6q_clk_ops = { .disable = ccf_clk_disable, }; +static const char *const pll_bypass_src_sels[] = { + "osc", + "lvds1_in", + "lvds2_in", + "dummy", +}; + +static const char *const pll2_bypass_sels[] = { + "pll2", + "pll2_bypass_src", +}; + +static const char *const pll3_bypass_sels[] = { + "pll3", + "pll3_bypass_src", +}; + +static const char *const pll5_bypass_sels[] = { + "pll5", + "pll5_bypass_src", +}; + +static const char *const pll6_bypass_sels[] = { + "pll6", + "pll6_bypass_src", +}; + static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", @@ -72,6 +100,23 @@ static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; + +static const struct clk_div_table post_div_table[] = { + { .val = 2, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 0, .div = 4, }, + { /* sentinel */ } +}; + +static const struct clk_div_table video_div_table[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 1, }, + { .val = 3, .div = 4, }, + { /* sentinel */ } +}; + +#if CONFIG_IS_ENABLED(VIDEO) static const char *const ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", @@ -113,6 +158,122 @@ static const char *ipu2_di1_sels_2[] = { static unsigned int share_count_mipi_core_cfg; +static void of_assigned_ldb_sels(struct udevice *dev, int *ldb_di0_sel, + int *ldb_di1_sel) +{ + struct ofnode_phandle_args clk_args, parent_args; + ofnode node = dev_ofnode(dev); + int count, err; + + count = dev_count_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0); + if (count <= 0) { + if (count == 0) + debug("%s: no assigned_clocks found\n", dev->name); + else + pr_err("%s: failed to get phandle count (%d)\n", + dev->name, count); + return; + } + + for (int i = 0; i < count; i++) { + err = dev_read_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0, i, + &clk_args); + if (err == -ENOENT) + /* Skip empty handles */ + continue; + else if (err < 0) + return; + + if (!ofnode_equal(clk_args.node, node) || + clk_args.args[0] >= IMX6QDL_CLK_END) { + pr_err("%s: clock %d not in ccm\n", dev->name, i); + return; + } + + err = dev_read_phandle_with_args(dev, "assigned-clock-parents", + "#clock-cells", 0, i, + &parent_args); + if (err < 0) + return; + + if (!ofnode_equal(parent_args.node, node) || + parent_args.args[0] >= IMX6QDL_CLK_END) { + pr_err("%s: parent clock %d not in ccm\n", dev->name, + i); + return; + } + + if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI0_SEL) + *ldb_di0_sel = parent_args.args[0]; + else if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI1_SEL) + *ldb_di1_sel = parent_args.args[0]; + } +} + +static void imx6q_init_ldb_clks(struct udevice *dev) +{ + int ldb_di_sel[] = { IMX6QDL_CLK_END, IMX6QDL_CLK_END }; + enum ldb_di_clock ldb_di_clk[] = { MXC_MMDC_CH1_CLK, MXC_MMDC_CH1_CLK }; + + of_assigned_ldb_sels(dev, &ldb_di_sel[0], &ldb_di_sel[1]); + for (int i = 0; i < 2; i++) { + switch (ldb_di_sel[i]) { + case IMX6QDL_CLK_PLL5_VIDEO_DIV: + ldb_di_clk[i] = MXC_PLL5_CLK; + break; + case IMX6QDL_CLK_PLL2_PFD0_352M: + ldb_di_clk[i] = MXC_PLL2_PFD0_CLK; + break; + case IMX6QDL_CLK_PLL2_PFD2_396M: { + struct clk *clk, *parent; + + int err = clk_get_by_id(IMX6QDL_CLK_PERIPH_PRE, &clk); + + if (err) { + pr_err("%s: failed to get periph_pre clock " + "(%d)\n", + dev->name, err); + return; + } + + err = clk_get_by_id(IMX6QDL_CLK_PLL2_PFD2_396M, + &parent); + if (err) { + pr_err("%s: failed to get pll2_pfd2_396m clock" + " (%d)\n", + dev->name, err); + return; + } + + if (parent == clk) { + pr_err("%s: ldb_di%d_sel: couldn't disable " + "pll2_pfd2_396m clock\n", + dev->name, i); + return; + } + + ldb_di_clk[i] = MXC_PLL2_PFD2_CLK; + break; + } + case IMX6QDL_CLK_MMDC_CH1_AXI: + case IMX6QDL_CLK_END: + /* use the default clock */ + break; + case IMX6QDL_CLK_PLL3_USB_OTG: + ldb_di_clk[i] = MXC_PLL3_SW_CLK; + break; + default: + pr_err("%s: invalid LDB clock parent\n", dev->name); + return; + } + } + + select_ldb_di_clock_source(ldb_di_clk[0], ldb_di_clk[1]); +} +#endif /* CONFIG_IS_ENABLED(VIDEO) */ + static int imx6q_clk_probe(struct udevice *dev) { void *base; @@ -120,26 +281,70 @@ static int imx6q_clk_probe(struct udevice *dev) /* Anatop clocks */ base = (void *)ANATOP_BASE_ADDR; - clk_dm(IMX6QDL_CLK_PLL2, - imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc", - base + 0x30, 0x1)); + clk_dm(IMX6QDL_PLL2_BYPASS_SRC, + imx_clk_mux(dev, "pll2_bypass_src", base + 0x30, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL3_BYPASS_SRC, + imx_clk_mux(dev, "pll3_bypass_src", base + 0x10, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL5_BYPASS_SRC, + imx_clk_mux(dev, "pll5_bypass_src", base + 0xa0, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL6_BYPASS_SRC, + imx_clk_mux(dev, "pll6_bypass_src", base + 0xe0, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + + clk_dm(IMX6QDL_CLK_PLL2, imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2", + "osc", base + 0x30, 0x1)); + clk_dm(IMX6QDL_CLK_PLL3, imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3", + "osc", base + 0x10, 0x3)); + clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", + base + 0xa0, 0x7f)); + clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", + "osc", base + 0xe0, 0x3)); + + clk_dm(IMX6QDL_PLL2_BYPASS, + imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1, + pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL3_BYPASS, + imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1, + pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL5_BYPASS, + imx_clk_mux_flags(dev, "pll5_bypass", base + 0xa0, 16, 1, + pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL6_BYPASS, + imx_clk_mux_flags(dev, "pll6_bypass", base + 0xe0, 16, 1, + pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), + CLK_SET_RATE_PARENT)); + + SET_CLK_PARENT(IMX6QDL_PLL2_BYPASS, IMX6QDL_CLK_PLL2); + SET_CLK_PARENT(IMX6QDL_PLL3_BYPASS, IMX6QDL_CLK_PLL3); + SET_CLK_PARENT(IMX6QDL_PLL5_BYPASS, IMX6QDL_CLK_PLL5); + SET_CLK_PARENT(IMX6QDL_PLL6_BYPASS, IMX6QDL_CLK_PLL6); + + clk_dm(IMX6QDL_CLK_PLL2_BUS, + imx_clk_gate(dev, "pll2_bus", "pll2_bypass", base + 0x30, 13)); clk_dm(IMX6QDL_CLK_PLL3_USB_OTG, - imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", - base + 0x10, 0x3)); + imx_clk_gate(dev, "pll3_usb_otg", "pll3_bypass", base + 0x10, + 13)); + clk_dm(IMX6QDL_CLK_PLL5_VIDEO, + imx_clk_gate(dev, "pll5_video", "pll5_bypass", base + 0xa0, 13)); + clk_dm(IMX6QDL_CLK_PLL6_ENET, + imx_clk_gate(dev, "pll6_enet", "pll6_bypass", base + 0xe0, 13)); + clk_dm(IMX6QDL_CLK_PLL3_60M, imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); clk_dm(IMX6QDL_CLK_PLL3_80M, imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMX6QDL_CLK_PLL3_120M, imx_clk_fixed_factor(dev, "pll3_120m", "pll3_usb_otg", 1, 4)); - clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", - base + 0xa0, 0x7f)); - clk_dm(IMX6QDL_CLK_PLL5_VIDEO, - imx_clk_gate(dev, "pll5_video", "pll5", base + 0xa0, 13)); - clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", - "osc", base + 0xe0, 0x3)); - clk_dm(IMX6QDL_CLK_PLL6_ENET, - imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); @@ -151,10 +356,14 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_PLL2_198M, imx_clk_fixed_factor(dev, "pll2_198m", "pll2_pfd2_396m", 1, 2)); clk_dm(IMX6QDL_CLK_PLL5_POST_DIV, - imx_clk_fixed_factor(dev, "pll5_post_div", "pll5_video", 1, 1)); + clk_register_divider_table(dev, "pll5_post_div", "pll5_video", + CLK_SET_RATE_PARENT, base + 0xa0, 19, + 2, 0, post_div_table)); clk_dm(IMX6QDL_CLK_PLL5_VIDEO_DIV, - imx_clk_fixed_factor(dev, "pll5_video_div", "pll5_post_div", 1, - 1)); + clk_register_divider_table(dev, "pll5_video_div", + "pll5_post_div", CLK_SET_RATE_PARENT, + base + 0x170, 30, 2, 0, + video_div_table)); clk_dm(IMX6QDL_CLK_VIDEO_27M, imx_clk_fixed_factor(dev, "video_27m", "pll3_pfd1_540m", 1, 20)); @@ -263,6 +472,7 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22)); +#if CONFIG_IS_ENABLED(VIDEO) clk_dm(IMX6QDL_CLK_IPU1_SEL, imx_clk_mux(dev, "ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels))); @@ -279,9 +489,12 @@ static int imx6q_clk_probe(struct udevice *dev) ldb_di_sels, ARRAY_SIZE(ldb_di_sels))); } else { /* - * Need to set these as read-only due to a hardware bug. - * Keeping default mux values. Fixed on the i.MX6 QuadPlus - */ + * Need to set these as read-only due to a hardware bug. + * Keeping default mux values. Fixed on the i.MX6 QuadPlus + * Need to set the clocks now and make them read-only due to a + * hardware bug. Fixed on the i.MX6 QuadPlus + */ + imx6q_init_ldb_clks(dev); clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), @@ -413,6 +626,7 @@ static int imx6q_clk_probe(struct udevice *dev) ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT)); } +#endif /* CONFIG_IS_ENABLED(VIDEO) */ clk_dm(IMX6QDL_CLK_ECSPI1, imx_clk_gate2(dev, "ecspi1", "ecspi_root", base + 0x6c, 0)); @@ -453,6 +667,8 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1)); + +#if CONFIG_IS_ENABLED(VIDEO) clk_dm(IMX6QDL_CLK_MIPI_CORE_CFG, imx_clk_gate2_shared(dev, "mipi_core_cfg", "video_27m", base + 0x74, 16, @@ -480,6 +696,7 @@ static int imx6q_clk_probe(struct udevice *dev) SET_CLK_PARENT(IMX6QDL_CLK_IPU1_SEL, IMX6QDL_CLK_PLL3_PFD1_540M); } +#endif /* CONFIG_IS_ENABLED(VIDEO) */ return 0; } diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index 7cf178f8a48..ba3c5fcf25b 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -194,11 +194,11 @@ static int imx_rgpio2p_bind(struct udevice *dev) dual_base = true; if (dual_base) { - addr = devfdt_get_addr_index(dev, 1); + addr = dev_read_addr_index(dev, 1); if (addr == FDT_ADDR_T_NONE) return -EINVAL; } else { - addr = devfdt_get_addr_index(dev, 0); + addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 8ee0a7733ca..355fd86ed8c 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -795,6 +795,38 @@ int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_outp return ret; } +int ele_v2x_get_state(struct v2x_get_state *state, u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg = {}; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_V2X_GET_STATE_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + state->v2x_state = msg.data[1] & 0xFF; + state->v2x_power_state = (msg.data[1] & 0xFF00) >> 8; + state->v2x_err_code = msg.data[2]; + + return ret; +} + int ele_volt_change_start_req(void) { struct udevice *dev = gd->arch.ele_dev; diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index cdb85b999db..65a4779c041 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -209,7 +209,7 @@ static int imx8ulp_mu_probe(struct udevice *dev) debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); - addr = devfdt_get_addr(dev); + addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 3f5fadfc80a..955f1c96407 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -519,8 +519,7 @@ static int lpuart_serial_probe(struct udevice *dev) static int lpuart_serial_of_to_plat(struct udevice *dev) { struct lpuart_serial_plat *plat = dev_get_plat(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); + ofnode node = dev_ofnode(dev); fdt_addr_t addr; addr = dev_read_addr(dev); @@ -530,18 +529,18 @@ static int lpuart_serial_of_to_plat(struct udevice *dev) plat->reg = (void *)addr; plat->flags = dev_get_driver_data(dev); - if (fdtdec_get_bool(blob, node, "little-endian")) + if (ofnode_read_bool(node, "little-endian")) plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG; - if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart")) + if (ofnode_device_is_compatible(node, "fsl,ls1021a-lpuart")) plat->devtype = DEV_LS1021A; - else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imx7ulp-lpuart")) plat->devtype = DEV_MX7ULP; - else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,vf610-lpuart")) plat->devtype = DEV_VF610; - else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imx8qm-lpuart")) plat->devtype = DEV_IMX8; - else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imxrt-lpuart")) plat->devtype = DEV_IMXRT; return 0; diff --git a/drivers/video/imx/ipu.h b/drivers/video/imx/ipu.h index ae40e20bc28..aecb6adffce 100644 --- a/drivers/video/imx/ipu.h +++ b/drivers/video/imx/ipu.h @@ -136,7 +136,6 @@ struct ipu_ctx { struct clk *ipu_clk; struct clk *ldb_clk; - unsigned char ipu_clk_enabled; struct clk *di_clk[2]; struct clk *pixel_clk[2]; diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index 8630374a055..d3b52605731 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -299,9 +299,9 @@ struct ipu_ctx *ipu_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) clk_set_parent(ctx->pixel_clk[0], ctx->ipu_clk); clk_set_parent(ctx->pixel_clk[1], ctx->ipu_clk); +#endif clk_enable(ctx->ipu_clk); -#endif for (int i = 0; i <= 1; i++) { ret = ipu_di_clk_init(ctx, i); @@ -384,10 +384,8 @@ int32_t ipu_init_channel(struct ipu_ctx *ctx, ipu_channel_t channel, debug("init channel = %d\n", IPU_CHAN_ID(channel)); - if (ctx->ipu_clk_enabled == 0) { - ctx->ipu_clk_enabled = 1; + if (!ipu_clk_enabled(ctx)) clk_enable(ipu_clk); - } if (*channel_init_mask & (1L << IPU_CHAN_ID(channel))) { printf("Warning: channel already initialized %d\n", @@ -543,7 +541,6 @@ void ipu_uninit_channel(struct ipu_ctx *ctx, ipu_channel_t channel) if (ipu_conf == 0) { clk_disable(ctx->ipu_clk); - ctx->ipu_clk_enabled = 0; } } @@ -1045,5 +1042,9 @@ ipu_color_space_t format_to_colorspace(u32 fmt) bool ipu_clk_enabled(struct ipu_ctx *ctx) { - return ctx->ipu_clk_enabled; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return clk_get_usecount(ctx->ipu_clk); +#else + return ctx->ipu_clk->enable_count; +#endif } diff --git a/include/configs/aquila-imx95.h b/include/configs/aquila-imx95.h new file mode 100644 index 00000000000..07d09d138cb --- /dev/null +++ b/include/configs/aquila-imx95.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) Toradex */ + +#ifndef __AQUILA_IMX95_H +#define __AQUILA_IMX95_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above */ +#define SZ_6G _AC(0x180000000, ULL) + +/* first 256MB reserved for firmware */ +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 +#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M) +#define PHYS_SDRAM_2_SIZE SZ_6G + +#define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */ +#define CFG_SYS_SECURE_SDRAM_SIZE 0x06000000 + +#endif diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index ef2848b71f3..d3a57a10a16 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -8,133 +8,11 @@ #ifndef __MX6QSABRE_COMMON_CONFIG_H #define __MX6QSABRE_COMMON_CONFIG_H -#include <linux/stringify.h> - #include "mx6_common.h" /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#ifdef CONFIG_SUPPORT_EMMC_BOOT -#define EMMC_ENV \ - "emmcdev=2\0" \ - "update_emmc_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "if mmc dev ${emmcdev} 1; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" -#else -#define EMMC_ENV "" -#endif - -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdtfile=undefined\0" \ - "fdt_addr=0x18000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ - "dfu_alt_info_spl=spl raw 0x400\0" \ - "dfu_alt_info_img=u-boot raw 0x10000\0" \ - "dfu_alt_info=spl raw 0x400\0" \ - "initrd_high=0xffffffff\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - EMMC_ENV \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadbootscript=" \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || " \ - "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $fdtfile = undefined; then " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabreauto.dtb; fi; " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabreauto.dtb; fi; " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabreauto.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabresd.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabresd.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabresd.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; " \ - "fi;\0" \ - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index e491af3e927..b5602def87d 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -9,7 +9,6 @@ #define __MX6SABREAUTO_CONFIG_H #define CFG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" #define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index e34947c94d0..1ea08f835dd 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -9,7 +9,6 @@ #define __MX6SABRESD_CONFIG_H #define CFG_MXC_UART_BASE UART1_BASE -#define CONSOLE_DEV "ttymxc0" #include "mx6sabre_common.h" diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 88b535e1bd0..a535163fd19 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -9,7 +9,6 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#include <linux/stringify.h> #include "mx6_common.h" #include <asm/mach-imx/gpio.h> @@ -23,78 +22,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=undefined\0" \ - "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $fdt_file = undefined; then " \ - "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \ - "if test $board_name = EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \ - "if test $fdt_file = undefined; then " \ - "echo WARNING: Could not determine dtb to use; " \ - "fi; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - /* Miscellaneous configurable options */ /* Physical Memory Map */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 21dbec837f0..f36265f13e6 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -24,69 +24,6 @@ #define PHYS_SDRAM_SIZE SZ_1G #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttyLP0\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx7ulp-evk.dtb\0" \ - "fdt_addr=0x63000000\0" \ - "boot_fdt=try\0" \ - "earlycon=lpuart32,0x402D0010\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "usb start; "\ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE SZ_256K diff --git a/include/env/nxp/mx6sabre_common.env b/include/env/nxp/mx6sabre_common.env new file mode 100644 index 00000000000..5346cd4e953 --- /dev/null +++ b/include/env/nxp/mx6sabre_common.env @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +fdtfile=undefined +fdt_addr=0x18000000 +boot_fdt=try +ip_dyn=yes +dfuspi=dfu 0 sf 0:0:10000000:0 +dfu_alt_info_spl=spl raw 0x400 +dfu_alt_info_img=u-boot raw 0x10000 +dfu_alt_info=spl raw 0x400 +initrd_high=0xffffffff +splashimage=CONFIG_SYS_LOAD_ADDR +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +finduuid=part uuid mmc ${mmcdev}:2 uuid +update_sd_firmware=if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if mmc dev ${mmcdev}; then + if ${get_cmd} ${update_sd_firmware_filename}; then + setexpr fw_sz ${filesize} / 0x200; + setexpr fw_sz ${fw_sz} + 1; + mmc write ${loadaddr} 0x2 ${fw_sz}; + fi; + fi +#ifdef CONFIG_SUPPORT_EMMC_BOOT +emmcdev=2 +update_emmc_firmware=if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if ${get_cmd} ${update_sd_firmware_filename}; then + if mmc dev ${emmcdev} 1; then + setexpr fw_sz ${filesize} / 0x200; + setexpr fw_sz ${fw_sz} + 1; + mmc write ${loadaddr} 0x2 ${fw_sz}; + fi; + fi +#endif +mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw +loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || + load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || + load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image} +loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || + load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile} +mmcboot=echo Booting from mmc ...; + run finduuid; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdtfile}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +findfdt=if test $fdtfile = undefined; then + if test $board_name = SABREAUTO && test $board_rev = MX6QP; then + setenv fdtfile imx6qp-sabreauto.dtb; + fi; + if test $board_name = SABREAUTO && test $board_rev = MX6Q; then + setenv fdtfile imx6q-sabreauto.dtb; + fi; + if test $board_name = SABREAUTO && test $board_rev = MX6DL; then + setenv fdtfile imx6dl-sabreauto.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6QP; then + setenv fdtfile imx6qp-sabresd.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6Q; then + setenv fdtfile imx6q-sabresd.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6DL; then + setenv fdtfile imx6dl-sabresd.dtb; + fi; + if test $fdtfile = undefined; then + echo WARNING: Could not determine dtb to use; + fi; + fi; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2d754fa4287..366f2d968a3 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -246,6 +246,11 @@ struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk *clk_register_divider_table(struct udevice *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table); + struct clk *clk_register_divider(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, diff --git a/tools/binman/etype/nxp_imx9image.py b/tools/binman/etype/nxp_imx9image.py index e0e806f2b7f..138563ba33a 100644 --- a/tools/binman/etype/nxp_imx9image.py +++ b/tools/binman/etype/nxp_imx9image.py @@ -36,7 +36,8 @@ class Entry_nxp_imx9image(Entry_mkimage): 'append', 'boot-from', 'cntr-version', 'container', 'dummy-ddr', 'dummy-v2x', 'hold', 'image', 'soc-type' ] - external_files = ['oei-m33-tcm.bin', 'm33_image.bin', 'bl31.bin'] + external_files = ['oei-m33-tcm.bin', 'm33_image.bin', 'bl31.bin', + 'tee.bin'] with open(self.config_filename, 'w', encoding='utf-8') as f: for prop in self._node.props.values(): |