summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorSerge Semin <fancer.lancer@gmail.com>2020-10-10 16:11:36 +0300
committerSerge Semin <fancer.lancer@gmail.com>2026-08-13 01:21:23 +0300
commit676412c0e863d3f4ae0c394e4bc6184659452734 (patch)
treed5fb84c0a49f390be27bd663a5466128a8a78539
parent2f1b58de051761c333ca3771d7db986dd2aa5e4f (diff)
downloadlinux-boot/bt1.tar.gz
linux-boot/bt1.zip
dt-bindings: sram: Add Baikal-T1 Boot SRAM bindingboot/bt1
Baikal-T1 is equipped with embedded SRAM of 64KB being accessed over the AXI interconnect. It's normally used at the SoC startup procedure to execute the system bootloader before the normal memory is initialized. Alternatively the internal SRAM can be used to automatically pre-load a bootloader code from external SPI-flash if corresponding Baikal-T1 Boot mode is enabled, But functionally the later feature isn't that useful, since SRAM is too small while the initial software can be XIP-ed right from the SPI-flash and then download the system software from any place it wants. Baikal-T1 SRAM is clocked with a dedicated AXI-clock source and can be reset by toggling the corresponding reset line. Due to the ability to serve as a target of the system startup code pre-loading SRAM is connected to the Baikal-T1 Boot Controller, which needs to be tuned in order to get a direct access to the memory. The later is implemented in the framework of the mux-controller functionality. Signed-off-by: Serge Semin <fancer.lancer@gmail.com>
-rw-r--r--Documentation/devicetree/bindings/sram/sram.yaml57
1 files changed, 42 insertions, 15 deletions
diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml
index e9faffb64463..72bfd4cd78df 100644
--- a/Documentation/devicetree/bindings/sram/sram.yaml
+++ b/Documentation/devicetree/bindings/sram/sram.yaml
@@ -37,6 +37,7 @@ properties:
- qcom,kaanapali-imem
- qcom,rpm-msg-ram
- rockchip,rk3288-pmu-sram
+ - baikal,bt1-sram
reg:
maxItems: 1
@@ -47,6 +48,15 @@ properties:
A list of phandle and clock specifier pair that controls the single
SRAM clock.
+ clock-names: true
+
+ resets:
+ description:
+ A list of phandle and reset specifier pair that controls the SRAM
+ state reset.
+
+ reset-names: true
+
"#address-cells":
const: 1
@@ -90,6 +100,7 @@ patternProperties:
- arm,juno-scp-shmem
- arm,scmi-shmem
- arm,scp-shmem
+ - baikal,bt1-boot-sram
- qcom,pil-reloc-info
- renesas,smp-sram
- rockchip,rk3066-smp-sram
@@ -144,21 +155,37 @@ required:
- compatible
- reg
-if:
- not:
- properties:
- compatible:
- contains:
- enum:
- - qcom,rpm-msg-ram
- - rockchip,rk3288-pmu-sram
-then:
- required:
- - "#address-cells"
- - "#size-cells"
- - ranges
-
-additionalProperties: false
+allOf:
+ - $ref: /schemas/mux/mux-consumer.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: baikal,bt1-sram
+ then:
+ properties:
+ mux-controls:
+ maxItems: 1
+ required:
+ - mux-controls
+ else:
+ properties:
+ mux-controls: false
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ enum:
+ - qcom,rpm-msg-ram
+ - rockchip,rk3288-pmu-sram
+ then:
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+unevaluatedProperties: false
examples:
- |