kernel/git/next/linux-next.git/Documentation/devicetree/bindings/crypto, branch stable

Merge tag 'v7.2-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

2026-06-16T03:31:23+00:00

Pull crypto updates from Herbert Xu: "API: - Drop support for off-CPU cryptography in af_alg - Document that af_alg is *always* slower - Document the deprecation of af_alg - Remove zero-copy support from skcipher and aead in af_alg - Cap AEAD AD length to 0x80000000 in af_alg - Free default RNG on module exit Algorithms: - Fix vli multiplication carry overflow in ecc - Drop unused cipher_null crypto_alg - Remove unused variants of drbg - Use lib/crypto in drbg - Use memcpy_from/to_sglist in authencesn - Allow authenc(hmac(sha{256,384}),cts(cbc(aes))) in FIPS mode - Disallow RSA PKCS#1 SHA-1 sig algs in FIPS mode - Filter out async aead implementations at alloc in krb5 - Fix non-parallel fallback by rstoring callback in pcrypt - Validate poly1305 template argument in chacha20poly1305 Drivers: - Add sysfs PCI reset support to qat - Add KPT support for GEN6 devices to qat - Remove unused character device and ioctls from qat - Add support for hw access via SMCC to mtk - Remove prng support from crypto4xx - Remove prng support from hisi-trng - Remove prng support from sun4i-ss - Remove prng support from xilinx-trng - Remove loongson-rng - Remove exynos-rng Others: - Remove support for AIO on sockets" * tag 'v7.2-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (196 commits) crypto: tegra - fix refcount leak in tegra_se_host1x_submit() crypto: rng - Free default RNG on module exit crypto: testmgr - allow authenc(hmac(sha{256,384}),cts(cbc(aes))) in FIPS mode hwrng: jh7110 - fix refcount leak in starfive_trng_read() crypto: atmel-ecc - drop dead code in atmel_ecdh_max_size crypto: cavium/cpt - fix DMA cleanup using wrong loop index crypto: marvell/octeontx - fix DMA cleanup using wrong loop index MAINTAINERS: make myself the maintainer of the Qualcomm QCE driver crypto: amcc - convert irq_of_parse_and_map to platform_get_irq crypto: sun4i-ss - Remove insecure and unused rng_alg hwrng: xilinx - Move xilinx-rng into drivers/char/hw_random/ crypto: xilinx-trng - Replace crypto_drbg_ctr_df() with HMAC-SHA512 crypto: xilinx-trng - Fix return value of xtrng_hwrng_trng_read() crypto: xilinx-trng - Remove crypto_rng interface crypto: exynos-rng - Remove exynos-rng driver hwrng: hisi-trng - Move hisi-trng into drivers/char/hw_random/ crypto: hisi-trng - Remove crypto_rng interface crypto: loongson - Remove broken and unused loongson-rng crypto: crypto4xx - Remove insecure and unused rng_alg crypto: qat - validate RSA CRT component lengths ...

dt-bindings: crypto: qcom,inline-crypto-engine: Document Hawi ICE

2026-06-05T11:36:35+00:00

The Inline Crypto Engine found in Hawi SoC is compatible with the common baseline IP 'qcom,inline-crypto-engine'. Hence, document the compatible as such. Signed-off-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski Signed-off-by: Herbert Xu

dt-bindings: crypto: qcom,prng: Document Hawi TRNG

2026-06-05T11:36:35+00:00

Hawi SoC has the True Random Number Generator (TRNG) which is compatible with the baseline IP "qcom,trng". Hence, document the compatible as such. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Signed-off-by: Herbert Xu

dt-bindings: crypto: qcom,prng: Document TRNG on Nord SoC

2026-05-15T10:08:48+00:00

Document True Random Number Generator on Qualcomm Nord SoC. Signed-off-by: Deepti Jaggi Signed-off-by: Shawn Guo Acked-by: Krzysztof Kozlowski Signed-off-by: Herbert Xu

dt-bindings: crypto: qcom-qce: document the Nord crypto engine

2026-05-15T10:08:36+00:00

Document the crypto engine on the Qualcomm Nord Platform. Signed-off-by: Bartosz Golaszewski Acked-by: Rob Herring (Arm) Signed-off-by: Herbert Xu

dt-bindings: crypto: qcom,ice: Fix missing power-domain and iface clk

2026-05-11T14:05:19+00:00

The DT bindings for inline-crypto engine do not specify the UFS_PHY_GDSC power-domain and iface clock. Without enabling the iface clock and the associated power-domain the ICE hardware cannot function correctly and leads to unclocked hardware accesses being observed during probe. Fix the DT bindings for inline-crypto engine to require the UFS_PHY_GDSC power-domain and iface clock for new devices (Eliza and Milos) introduced in the current release (7.1) with yet-to-stabilize ABI, while preserving backward compatibility for older devices. Fixes: 618195a7ac3df ("dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE") Fixes: 85faec1e85555 ("dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE") Reviewed-by: Kuldeep Singh Reviewed-by: Krzysztof Kozlowski Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-1-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson

dt-bindings: crypto: qcom,prng: Document Glymur TRNG

2026-05-07T08:10:02+00:00

Document glymur compatible for the True Random Number Generator. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Harshal Dev Signed-off-by: Herbert Xu

dt-bindings: crypto: qcom-qce: Document the Glymur crypto engine

2026-05-07T08:09:59+00:00

Document the crypto engine on Glymur platform. Signed-off-by: Harshal Dev Reviewed-by: Krzysztof Kozlowski Signed-off-by: Herbert Xu

dt-bindings: crypto: qcom-qce: Add Qualcomm Eliza QCE

2026-05-05T08:15:36+00:00

Document the QCE crypto engine on Qualcomm Eliza SoC, fully compatible with earlier generations. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Harshal Dev Reviewed-by: Kuldeep Singh Acked-by: Rob Herring (Arm) Signed-off-by: Herbert Xu

dt-bindings: crypto: qcom-qce: Document the Milos crypto engine

2026-05-05T08:15:24+00:00

Document the crypto engine on the Milos platform. Signed-off-by: Alexander Koskovich Reviewed-by: Krzysztof Kozlowski Reviewed-by: Kuldeep Singh Signed-off-by: Herbert Xu