kernel/git/next/linux-next.git/Documentation/devicetree/bindings/pinctrl, branch stable

dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl controller

2026-06-11T13:02:26+00:00

Add doc for the pinctrl controllers on the UltraRISC DP1000 RISC-V SoC. Signed-off-by: Jia Wang Reviewed-by: Conor Dooley Signed-off-by: Linus Walleij

dt-bindings: pinctrl: tegra238: add missing AON pin groups

2026-06-11T12:03:24+00:00

Add 24 pin groups, and their matching drive groups, on ports EE, FF, GG and HH to the Tegra238 AON pinmux binding. These groups are present on the AON pin controller, so device trees that mux these pins through it validate against the schema. Fixes: 9323f8a0e12c ("dt-bindings: pinctrl: Document Tegra238 pin controllers") Signed-off-by: Prathamesh Shete Acked-by: Conor Dooley Signed-off-by: Linus Walleij

dt-bindings: pinctrl: sun55i-a523: increase IRQ banks number

2026-06-11T11:47:52+00:00

The Allwinner A523 SoC implements 10 GPIO banks in the first pinctrl instance, but it skips the first bank (PortA), so their index goes from 1 to 10. The same is actually true for the IRQ banks: there are registers for 11 banks, though the first bank is not implemented (RAZ/WI). In contrast to previous SoCs, the count of the IRQ banks starts with this first unimplemented bank, so we need to provide an interrupt for it. And indeed the A523 user manual lists an interrupt number for PortA, so we need to increase the maximum number of interrupts per pin controller to 11, to be able to assign the correct interrupt number for each bank. Signed-off-by: Andre Przywara Acked-by: Rob Herring (Arm) Reviewed-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai Signed-off-by: Linus Walleij

dt-bindings: pinctrl: realtek,rtd1625: Fix input voltage property name

2026-06-08T22:46:46+00:00

The property 'input-voltage-microvolt' is a typo. Rename it to 'input-threshold-voltage-microvolt' to align with the standard pin configuration defined in pincfg-node.yaml and parsed by pinconf-generic.c. Fixes: f6ea7004e926 ("dt-bindings: pinctrl: realtek: Add RTD1625 pinctrl binding") Signed-off-by: Yu-Chun Lin Acked-by: Conor Dooley Signed-off-by: Linus Walleij

dt-bindings: pinctrl: mediatek: mt6795: document the slew-rate property

2026-06-08T22:45:51+00:00

The driver for MT6795 pinctrl already supports the slew-rate property. Add its description to the documentation. Signed-off-by: Luca Leonardo Scorcia Acked-by: Conor Dooley Signed-off-by: Linus Walleij

dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for A9

2026-05-29T20:30:02+00:00

Update dt-binding document for pinctrl of Amlogic A9. In Amlogic A9 SoC, a bank mux register reuse other banks. The multiplexed part requires special processing and is therefore incompatible with the previous SoCs. Signed-off-by: Xianwei Zhao Acked-by: Conor Dooley Signed-off-by: Linus Walleij

dt-bindings: pinctrl: Document Tegra264 pin controllers

2026-05-27T12:06:30+00:00

Tegra264 contains three pin controllers. Document their compatible strings and describe the list of pins and functions that they provide. Signed-off-by: Prathamesh Shete Reviewed-by: Krzysztof Kozlowski Reviewed-by: Jon Hunter Signed-off-by: Linus Walleij

dt-bindings: pinctrl: Document Tegra238 pin controllers

2026-05-27T12:03:14+00:00

Tegra238 contains two pin controllers. Document their compatible strings and describe the list of pins and functions that they provide. Signed-off-by: Prathamesh Shete Reviewed-by: Krzysztof Kozlowski Reviewed-by: Jon Hunter Signed-off-by: Linus Walleij

dt-bindings: pinctrl: Add aspeed,ast2700-soc1-pinctrl

2026-05-25T08:04:19+00:00

SoC1 in the AST2700 integrates its own pin controller responsible for pin multiplexing and pin configuration. The controller manages various peripheral functions such as eSPI, LPC, VPI, SD, UART, I2C, I3C, PWM and others through SCU registers. The binding reuses the standard pinmux and generic pin configuration schemas and does not introduce custom Devicetree properties. Acked-by: Conor Dooley Signed-off-by: Billy Tsai Signed-off-by: Linus Walleij

dt-bindings: pinctrl: qcom,eliza-tlmm: Merge QUP1_SE4 lane functions

2026-05-23T09:04:06+00:00

QUP1_SE4 uses GPIO36 and GPIO37 for two selectable lane pairs. The previous split added one function name per lane. Since these are usually configured in pairs in devicetree, it makes more sense to have them grouped. So replace the per-lane qup1_se4_l[0-3] names with names for the two selectable pairs, qup1_se4_01 and qup1_se4_23. Fixes: 1bd5c56253c5 ("dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP1_SE4 lanes") Suggested-by: Bjorn Andersson Acked-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij