kernel/git/next/linux-next.git/drivers/clk/mediatek/Makefile, branch master

clk: mediatek: Add mt8173-mfgtop driver

2026-07-28T15:25:30+00:00

The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP in the datasheet, that contains clock gates, some power sequence signal delays, and other unknown registers that get toggled when the GPU is powered on. The clock gates are exposed as clocks provided by a clock controller, while the power sequencing bits are exposed as one singular power domain. Tested-by: Icenowy Zheng Reviewed-by: Brian Masney Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Chen-Yu Tsai Signed-off-by: Brian Masney

clk: mediatek: Add MT8196 vencsys clock support

2025-09-21T16:36:22+00:00

Add support for the MT8196 vencsys clock controller, which provides clock gate control for the video encoder. Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8196 vdecsys clock support

2025-09-21T16:36:20+00:00

Add support for the MT8196 vdecsys clock controller, which provides clock gate control for the video decoder. Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8196 ovl1 clock support

2025-09-21T16:36:19+00:00

Add support for the MT8196 ovl1 clock controller, which provides clock gate control for the display system. It is integrated with the mtk-mmsys driver, which registers the ovl1 clock driver via platform_device_register_data(). Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8196 ovl0 clock support

2025-09-21T16:36:18+00:00

Add support for the MT8196 ovl0 clock controller, which provides clock gate control for the display system. It is integrated with the mtk-mmsys driver, which registers the ovl0 clock driver via platform_device_register_data(). Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8196 disp-ao clock support

2025-09-21T16:36:17+00:00

Add support for the MT8196 disp-ao clock controller, which provides clock gate control for the display system. It is integrated with the mtk-mmsys driver, which registers the disp-ao clock driver via platform_device_register_data(). Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8196 disp1 clock support

2025-09-21T16:36:15+00:00

Add support for the MT8196 disp1 clock controller, which provides clock gate control for the display system. It is integrated with the mtk-mmsys driver, which registers the disp1 clock driver via platform_device_register_data(). Reviewed-by: Chen-Yu Tsai # CLK_OPS_PARENT_ENABLE removal Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8196 disp0 clock support

2025-09-21T16:36:14+00:00

Add support for the MT8196 disp0 clock controller, which provides clock gate control for the display system. It is integrated with the mtk-mmsys driver, which registers the disp0 clock driver via platform_device_register_data(). Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8196 mfg clock support

2025-09-21T16:36:13+00:00

Add support for the MT8196 mfg clock controller, which provides PLL control for the GPU. Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8196 mdpsys clock support

2025-09-21T16:36:12+00:00

Add support for the MT8196 mdpsys clock controller, which provides clock gate control for MDP. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai # CLK_OPS_PARENT_ENABLE removal Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd