kernel/git/next/linux-next.git/drivers/clk/nuvoton, branch master

clk: nuvoton: ma35d1: fix ma35d1_clk_pll_determine_rate logic

2026-06-29T17:27:28+00:00

ma35d1_clk_pll_determine_rate() called ma35d1_pll_find_closest() unconditionally before the switch statement, and then every case branch overwrote pll_freq by reading the current hardware registers. For CAPLL and DDRPLL this means find_closest() ran unnecessarily (and incorrectly, since those PLLs are read-only) and its result was silently discarded. Fix by moving the find_closest() call inside the APLL/EPLL/VPLL branch where it belongs. Group CAPLL and DDRPLL together as read-only PLLs that simply report their current rate; handle them with an explicit if/else to keep the CAPLL (SMIC design) and DDRPLL (standard design) paths distinct. Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller") Signed-off-by: Joey Lu Signed-off-by: Brian Masney

clk: nuvoton: ma35d1: fix PLL_CTL1_FRAC bit field width and fractional calc

2026-06-29T17:27:28+00:00

PLL_CTL1_FRAC was defined as GENMASK(31, 24), covering only 8 bits. The hardware fractional field occupies bits [31:8] (24 bits), so the mask must be GENMASK(31, 8). The previous fractional-mode calculation used FIELD_MAX(PLL_CTL1_FRAC) as the denominator to obtain 2 decimal places. With the corrected 24-bit mask the old divisor is wrong; replace the arithmetic with a proper 24-bit fixed-point rounding to 3 decimal places using the kernel's DIV_ROUND_CLOSEST_ULL helper: n_frac = n * 1000 + DIV_ROUND_CLOSEST_ULL(x * 1000, 1 << 24) Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller") Signed-off-by: Joey Lu Reviewed-by: Brian Masney Signed-off-by: Brian Masney

clk: nuvoton: ma35d1: fix ignored div_u64 return values in PLL freq calculation

2026-06-29T17:27:28+00:00

div_u64() does not modify its argument in place; the return value must be assigned. Both ma35d1_calc_smic_pll_freq() and ma35d1_calc_pll_freq() called div_u64() and discarded the result, leaving pll_freq holding the undivided product and thus returning a frequency orders of magnitude too high. Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller") Reviewed-by: Brian Masney Signed-off-by: Joey Lu Signed-off-by: Brian Masney

clk: nuvoton: ma35d1-divider: convert from divider_round_rate() to divider_determine_rate()

2026-01-22T15:48:25+00:00

The divider_round_rate() function is now deprecated, so let's migrate to divider_determine_rate() instead so that this deprecated API can be removed. Note that when the main function itself was migrated to use determine_rate, this was mistakenly converted to: req->rate = divider_round_rate(...) This is invalid in the case when an error occurs since it can set the rate to a negative value. Fixes: 215f8aa095a1 ("clk: nuvoton: ma35d1-divider: convert from round_rate() to determine_rate()") Signed-off-by: Brian Masney

clk: nuvoton: ma35d1-pll: convert from round_rate() to determine_rate()

2025-09-08T13:41:27+00:00

The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney

clk: nuvoton: ma35d1-divider: convert from round_rate() to determine_rate()

2025-09-08T13:41:27+00:00

clk: nuvoton: Do not enable by default during compile testing

2025-06-20T07:21:15+00:00

Enabling the compile test should not cause automatic enabling of all drivers. Restrict the default to ARCH also for individual driver, even though its choice is not visible without selecting parent Kconfig symbol, because otherwise selecting parent would select the child during compile testing. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250404-kconfig-defaults-clk-v1-2-4d2df5603332@linaro.org Signed-off-by: Stephen Boyd

clk: nuvoton: Convert to devm_platform_ioremap_resource()

2023-08-22T21:52:11+00:00

Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/20230705065313.67043-12-frank.li@vivo.com Acked-by: Jacky Huang Signed-off-by: Stephen Boyd

clk: nuvoton: Use clk_parent_data instead of string for parent clock

2023-06-22T15:02:50+00:00

For the declaration of parent clocks, use struct clk_parent_data instead of a string. Due to the change in the passed arguments, replace the usage of devm_clk_hw_register_mux() with clk_hw_register_mux_parent_data() for all cases. Signed-off-by: Jacky Huang Signed-off-by: Arnd Bergmann

clk: nuvoton: Update all constant hex values to lowercase

2023-06-22T15:02:50+00:00

The constant hex values used to define register offsets were written in uppercase. This patch update all these constant hex values to be lowercase. Signed-off-by: Jacky Huang Signed-off-by: Arnd Bergmann