kernel/git/next/linux-next.git/drivers/clk/renesas, branch master

clk: renesas: Make sure clk_init_data is fully initialized

2026-09-01T07:13:40+00:00

The clk_init_data structure contains several mutually-exclusive members for different methods to specify the possible parents of a clock, prompting drivers to initialize only the members they need. However, not initializing all members may cause subtle issues, which are only exposed when CONFIG_INIT_STACK_ALL_PATTERN or CONFIG_INIT_STACK_NONE is enabled. Make sure all members are fully initialized, to avoid such bugs, and to prevent future breakage when converting drivers to a different method for specifying the parents. Signed-off-by: Geert Uytterhoeven Reviewed-by: Brian Masney Link: https://patch.msgid.link/b3473adc50c71aec5bc5f7ce6f5cda1727e26635.1787239813.git.geert+renesas@glider.be

clk: renesas: r9a08g046: Add clock and reset entries for LVDS

2026-08-31T10:19:12+00:00

Add clock and reset entries for LVDS. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das Link: https://patch.msgid.link/20260811182729.360959-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries

2026-08-31T10:19:12+00:00

Add clock and reset entries for the MIPI DSI and LCDC peripherals on the RZ/G3L (R9A08G046) SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260811182729.360959-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a08g046: Sort macro definitions alphabetically

2026-08-31T10:19:12+00:00

Reorder the DDIV_PACK() and SEL_PLL_PACK() macro definitions so they are grouped alphabetically by name, improving readability and making it easier to spot duplicates or gaps. No functional change. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260811182729.360959-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Add support for RZ/G3L DSI mux

2026-08-31T10:19:12+00:00

Add support for RZ/G3L DSI mux that supports 2 duty cycles. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260811182729.360959-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty cycle

2026-08-31T10:19:12+00:00

Add a new CLK_TYPE_G3L_LVDS_DIV clock type and register function for a fixed-factor divider used by the LVDS clock, which cannot produce a 50% duty cycle for odd divider values. Implement a custom get_duty_cycle() callback that reports the actual (div + 1) / 2 : div duty cycle, and add the DEF_G3L_LVDS_DIV() macro to define such clocks. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260811182729.360959-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Add support for divider flags

2026-08-31T10:19:12+00:00

Add support for passing divider flags apart from clock flags from soc specific clock drivers. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das Link: https://patch.msgid.link/20260811182729.360959-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Rename cpg_core_clk::flag to core_flags

2026-08-31T10:19:12+00:00

Rename the 'flag' member of struct cpg_core_clk to 'core_flags' for clarity and to better distinguish it from mux_flags. Update all users and DEF_* macros accordingly. No functional change. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260811182729.360959-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Add PLL7 DSI clock support for RZ/G3L

2026-08-31T10:19:12+00:00

Add a new fractional PLL clock type (CLK_TYPE_G3L_PLLDSI) for the RZ/G3L SoC's PLL7, which drives the DSI interface and requires a dedicated parameter calculation and programming sequence distinct from other PLLs in the RZ/G2L family. PLL7 output frequency is determined by the formula: Ffdco = (NIR + NFR / 4096) * (Fosc / MR) Ffout = Ffdco / (1 << PR) where: - Fosc = 24 MHz (oscillator input) - PR in [0, 4] (post divider, power-of-two) - MR in [1, 12] (input pre-divider) - NIR in [56, 375], NFR in [0, 4095] (integer and fractional parts) The FDCO must fall within one of two valid ranges: 900–2000 MHz (rangesel=0) or 2000–3000 MHz (rangesel=1). The parameter search in rzg3l_dsi_get_pll_parameters_values() iterates over all valid (MR, PR) combinations, filtering by the required FPFD range of 8–16 MHz, then delegates to rzg3l_dsi_compute_pll_parameters() to find the NIR/NFR pair that best approximates the requested rate. An exact match returns immediately; otherwise the combination with the smallest absolute frequency error is used. Computed parameters are cached in pll7_dsi_params within pll_clk to avoid redundant recalculation in determine_rate() when the requested rate has not changed. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260811182729.360959-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l: Add DSI divider clock support for RZ/G3L

2026-08-31T10:19:12+00:00

Add a new DSI divider clock type (CLK_TYPE_G3L_PLLDSI_DIV) for the RZ/G3L SoC, which requires a different divider implementation than the existing RZ/G2L DSI divider clock. The RZ/G3L DSI divider uses two cascaded dividers, DIV_DSI_A and DIV_DSI_B, where the effective divider is: rate = parent_rate / ((1 << div_a) * (div_b + 1)) DIV_DSI_A is a power-of-two divider with values in the range [0, 5], and DIV_DSI_B is a linear divider with values in the range [1, 16]. Introduce the g3l_dsi_div_hw_data structure, rzg3l_cpg_dsi_div_ops, and rzg3l_cpg_dsi_div_clk_register() to implement the new clock type, and add the DEF_G3L_PLLDSI_DIV() macro for use in clock table definitions. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260811182729.360959-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven