The linux-next integration testing tree https://git.rulkc.org/pub/scm/linux/kernel/git/next/linux-next.git/atom?h=akpm 2022-06-28T03:56:10+00:00 2022-06-28T03:56:10+00:00 Stephen Rothwell sfr@canb.auug.org.au 2022-06-28T03:56:10+00:00 urn:sha1:3e35c72204c6c3828454103559e106dabe17f32d 2022-06-28T00:10:56+00:00 Stephen Rothwell sfr@canb.auug.org.au 2022-06-28T00:10:56+00:00 urn:sha1:410414d532c83137fff900956d3cb0b6e3c6e0ab 2022-06-28T00:10:55+00:00 Stephen Rothwell sfr@canb.auug.org.au 2022-06-28T00:10:55+00:00 urn:sha1:d4e7646d4c5f205ad02250893e855597bbfe3b11 2022-06-28T00:10:55+00:00 Stephen Rothwell sfr@canb.auug.org.au 2022-06-28T00:10:55+00:00 urn:sha1:037e5b5645958911993b34a50f4e66a765b4d1dd 2022-06-28T00:10:51+00:00 Stephen Rothwell sfr@canb.auug.org.au 2022-06-28T00:10:51+00:00 urn:sha1:25c15b87e27a7fdab41fb09f5f8c52d50361d7ba 2022-06-28T00:10:49+00:00 Stephen Rothwell sfr@canb.auug.org.au 2022-06-28T00:10:49+00:00 urn:sha1:e8fb599d88e2bb9a63fca50369de30279fbf68ed 2022-06-26T03:38:02+00:00 Johan Hovold johan+linaro@kernel.org 2022-05-20T10:09:48+00:00 urn:sha1:8d114b94fc39210b88b203b57aaf04836a87a4f0 The PCIe GDSCs can be shared with other masters and should use the APCS collapse-vote register when updating the power state. This is specifically also needed to be able to disable power domains that have been enabled by boot firmware using the vote register. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220520100948.19622-4-johan+linaro@kernel.org 2022-06-26T03:38:02+00:00 Johan Hovold johan+linaro@kernel.org 2022-05-20T10:09:47+00:00 urn:sha1:77ea2bd72da4f61f59ad2e839babe83849f35dea Recent Qualcomm platforms have APCS collapse-vote registers that allow for sharing GDSCs with other masters (e.g. LPASS). Add support for using such vote registers instead of the control register when updating the GDSC power state. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220520100948.19622-3-johan+linaro@kernel.org 2022-06-26T03:38:02+00:00 Johan Hovold johan+linaro@kernel.org 2022-05-20T10:09:46+00:00 urn:sha1:e73cb8527c597598599119fcd9c7d1752d9e9fd7 Add a helper for updating the SW_COLLAPSE bit during initialisation and state updates. Note that the update during initialisation was relying on the SW_COLLAPSE bit not having been set earlier rather than passing in zero explicitly to clear the collapse vote. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220520100948.19622-2-johan+linaro@kernel.org 2022-06-26T03:07:53+00:00 Vladimir Zapolskiy vladimir.zapolskiy@linaro.org 2022-05-18T10:35:54+00:00 urn:sha1:c4f40351901a10cd662ac2c081396d8fb04f584d Access to I/O of SM8250 camera clock controller IP depends on enabled GCC_CAMERA_AHB_CLK clock supplied by global clock controller, the latter one is inited on subsys level, so, to satisfy the dependency, it would make sense to deprive the init level of camcc-sm8250 driver. If both drivers are compiled as built-in, there is a change that a board won't boot up due to a race, which happens on the same init level. Fixes: 5d66ca79b58c ("clk: qcom: Add camera clock controller driver for SM8250") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220518103554.949511-1-vladimir.zapolskiy@linaro.org