kernel/git/next/linux-next.git/drivers/crypto/hisilicon/Makefile, branch master

crypto: hisilicon/sec - remove SEC crypto block cipher accelerator

2026-09-11T05:03:02+00:00

The Hisilicon SEC crypto cipher accelerator has been superseded by the newer SEC2 driver (drivers/crypto/hisilicon/sec2/). SEC2 provides wider algorithm coverage and is the maintained path forward, and users have migrated to it. The legacy SEC driver has had no active users for some time, and its primary maintainer, Jonathan Cameron, has moved on from Huawei and is no longer in a position to maintain it. With thanks to Jonathan for his contributions to this driver over the years, and with no one left to keep it up to date, remove it from the tree. This drops the legacy SEC driver together with all of its residual configuration, devicetree binding and board description references: - drivers/crypto/hisilicon/sec/ - CONFIG_CRYPTO_DEV_HISI_SEC Kconfig option - sec/ entry from drivers/crypto/hisilicon/Makefile - Documentation/devicetree/bindings/crypto/hisilicon,hip06-sec.yaml - hisilicon,hip07-sec device nodes and their supporting mbigen_alg / smmu_alg infrastructure from arch/arm64/boot/dts/hisilicon/hip07.dtsi Signed-off-by: Chenghai Huang Reviewed-by: Longfang Liu Acked-by: Eric Biggers Acked-by: Wei Xu Reviewed-by: Jonathan Cameron Signed-off-by: Herbert Xu

hwrng: hisi-trng - Move hisi-trng into drivers/char/hw_random/

2026-06-11T06:02:58+00:00

Since this file just implements a hwrng driver, move it into drivers/char/hw_random/. Rename the kconfig option accordingly as well. Note that this moves the file back to its original location. Signed-off-by: Eric Biggers Signed-off-by: Herbert Xu

hwrng: histb - Move driver to drivers/char/hw_random/histb-rng.c

2023-05-12T10:48:01+00:00

Move to drivers/char/hw_random since histb-(t)rng does not provide cryptography pseudo rng. histb-rng is pretty like hisi-rng, but after investigation, we confirm there is no RNG_PHY_SEED register on histb-rng so a separate driver is needed. Still we rename relevant function names to match those in hisi-rng. Link: https://lore.kernel.org/r/20230401164448.1393336-1-mmyangfl@gmail.com Signed-off-by: David Yang Signed-off-by: Herbert Xu

crypto: hisilicon/trng - add support for HiSTB TRNG

2023-04-06T08:41:28+00:00

HiSTB TRNG are found on some HiSilicon STB SoCs. Signed-off-by: David Yang Signed-off-by: Herbert Xu

crypto: hisilicon/qm - split a debugfs.c from qm

2022-11-18T09:00:22+00:00

Considering that the qm feature and debugfs feature are independent. The code related to debugfs is getting larger and larger. It should be separate as a debugfs file. So move some debugfs code to new file from qm file. The qm code logic is not modified. And maintainability is enhanced. Signed-off-by: Kai Ye Signed-off-by: Herbert Xu

crypto: hisilicon/trng - add HiSilicon TRNG driver support

2020-11-27T06:13:43+00:00

Move existing char/hw_random/hisi-trng-v2.c to crypto/hisilicon/trng.c. Signed-off-by: Weili Qian Reviewed-by: Zaibo Xu Signed-off-by: Herbert Xu

crypto: hisilicon - add HiSilicon SEC V2 driver

2019-11-22T10:48:36+00:00

SEC driver provides PCIe hardware device initiation with AES, SM4, and 3DES skcipher algorithms registered to Crypto. It uses Hisilicon QM as interface to CPU. Signed-off-by: Zaibo Xu Signed-off-by: Longfang Liu Signed-off-by: Herbert Xu

crypto: hisilicon - add HiSilicon HPRE accelerator

2019-10-10T12:36:31+00:00

The HiSilicon HPRE accelerator implements RSA and DH algorithms. It uses Hisilicon QM as interface to CPU. This patch provides PCIe driver to the accelerator and registers its algorithms to crypto akcipher and kpp interfaces. Signed-off-by: Zaibo Xu Signed-off-by: Hui Tang Signed-off-by: Herbert Xu

crypto: hisilicon - merge sgl support to hisi_qm module

2019-10-10T12:36:31+00:00

As HW SGL can be seen as a data format of QM's sqe, we merge sgl code into qm module and rename it as hisi_qm, which reduces the number of module and make the name less generic. This patch also modify the interface of SGL: - Create/free hisi_acc_sgl_pool inside. - Let user to pass the SGE number in one SGL when creating sgl pool, which is better than a unified module parameter for sgl module before. - Modify zip driver according to sgl interface change. Signed-off-by: Zhou Wang Signed-off-by: Shukun Tan Signed-off-by: Herbert Xu

crypto: hisilicon - add HiSilicon ZIP accelerator support

2019-08-09T05:11:54+00:00

The HiSilicon ZIP accelerator implements the zlib and gzip algorithm. It uses Hisilicon QM as the interface to the CPU. This patch provides PCIe driver to the accelerator and registers it to crypto acomp interface. It also uses sgl as data input/output interface. Signed-off-by: Zhou Wang Signed-off-by: Shiju Jose Signed-off-by: Kenneth Lee Signed-off-by: Hao Fang Reviewed-by: Jonathan Cameron Reviewed-by: John Garry Signed-off-by: Herbert Xu