The linux-next integration testing tree https://git.rulkc.org/pub/scm/linux/kernel/git/next/linux-next.git/atom?h=master 2026-08-28T13:12:21+00:00 2026-08-28T13:12:21+00:00 Mark Brown broonie@kernel.org 2026-08-28T13:12:21+00:00 urn:sha1:cb447d75d419bb6eb3db9fac1fe27519ced22952 2026-08-18T21:02:15+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-08-18T21:02:15+00:00 urn:sha1:8dcef8882aad8f1b8668d1c39968cde99312aa3c Pull x86 MSR updates from Ingo Molnar: - Streamline the x86 MSR handling APIs along the 64-bit variants, simplifying the interfaces. Removal of the old APIs is planned for the next cycle, to reduce churn & integration pain (Juergen Gross) * tag 'x86-msr-2026-08-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits) x86/mce: Work around build warning after MSR-interface switch cpufreq: Stop using 32-bit MSR interfaces x86/featctl: Stop using 32-bit MSR interfaces KVM/x86: Stop using 32-bit MSR interfaces x86/mtrr: Stop using 32-bit MSR interfaces acpi: Stop using 32-bit MSR interfaces powercap: Stop using 32-bit MSR interfaces thermal/intel: Stop using 32-bit MSR interfaces x86/olpc: Stop using 32-bit MSR interfaces x86/hyperv: Stop using 32-bit MSR interfaces hwmon: Stop using 32-bit MSR interfaces EDAC: Stop using 32-bit MSR interfaces x86/cpu: Stop using 32-bit MSR interfaces x86/apic: Stop using 32-bit MSR interfaces x86/resctrl: Stop using 32-bit MSR interfaces x86/tsc: Stop using 32-bit MSR interfaces x86/amd: Stop using 32-bit MSR interfaces x86/pci: Stop using 32-bit MSR interfaces x86/hygon: Stop using 32-bit MSR interfaces x86/mce: Stop using 32-bit MSR interfaces ... 2026-08-08T00:59:50+00:00 Borislav Petkov (AMD) bp@alien8.de 2026-08-08T00:59:50+00:00 urn:sha1:5464985e42c04e335fb30e38fbc409c997db9bec * ras/edac-misc: EDAC/device_sysfs: Cleanup around edac_device_ctl_poll_msec_store() EDAC/device_sysfs: Use kstrtouint() for poll_msec to prevent truncation Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> 2026-08-07T23:30:52+00:00 Borislav Petkov (AMD) bp@alien8.de 2026-08-07T21:16:17+00:00 urn:sha1:9987979189133486632842d894603813b22937e1 - Align function args - Fix comment style - Fixup formatting around edac_device_reset_delay_period() too The not-too-trivial change is converting the edac_device_reset_delay_period() msec argument to unsigned int as that is what the rest of the code expects. Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> 2026-08-07T23:11:52+00:00 Jad Keskes inasj268@gmail.com 2026-07-30T14:55:48+00:00 urn:sha1:66cc9dec919dd63d8e4b3d386f7aed3ae684e645 The poll_msec sysfs store file uses simple_strtoul() which accepts an unsigned long, but the target field (poll_msec) is unsigned int. On 64-bit systems, a value > UINT_MAX is silently truncated when stored. Fix the mismatch by using kstrtouint() instead. This rejects values larger than UINT_MAX at parse time, making truncation impossible. Also add a check for value < 1 to reject the 0-delay case, which would cause the poll work to spin without delay and consume 100% CPU. Fixes: e27e3dac6517 ("drivers/edac: add edac_device class") Signed-off-by: Jad Keskes <inasj268@gmail.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20260730145549.148229-1-inasj268@gmail.com 2026-07-30T20:15:26+00:00 Tony Luck tony.luck@intel.com 2026-07-30T20:15:26+00:00 urn:sha1:b8dcf187035749d2528e4af4298830e64a9eb5f3 * edac-drivers EDAC/igen6: Add Intel Starfire SoCs support EDAC/igen6: Refactor address translation logic EDAC/igen6: Remove redundant resource configuration tables EDAC/igen6: Detect present memory controllers at runtime EDAC/igen6: Simplify compute die ID comments EDAC/igen6: Remove unnecessary XOR on the zero-valued interleave bit EDAC/igen6: Fix Raptor Lake-P logged error address EDAC/igen6: Fix channel address decode for non-hash mode EDAC/igen6: Fix channel selection hash EDAC/igen6: Fix interleave boundary condition EDAC/ie31200: Decouple DIMM width decoding from enum order Signed-off-by: Tony Luck <tony.luck@intel.com> 2026-07-30T18:34:12+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2026-07-30T02:54:54+00:00 urn:sha1:1713cc6b0e1904cf2c2b477ff25faf163c43cbdf Starfire is a derivative of Panther Lake SoC and shares a similar memory subsystem architecture. Add Starfire compute die ID and reuse Panther Lake's configuration data for EDAC support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Jie Wang <jie.wang@intel.com> Link: https://patch.msgid.link/20260730025454.4099934-1-qiuxu.zhuo@intel.com 2026-07-30T18:33:47+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2026-07-30T02:42:38+00:00 urn:sha1:377c68b988d9c36beb6dceedf81ed0ff55331aa9 The igen6 EDAC driver implements similar interleave and hash translation logic at multiple levels of the memory hierarchy. The separate implementations duplicate decoding logic, making future changes harder and increasing the risk of behavior diverging. Consolidate the common address translation operations into shared helpers so all decoding paths use a single implementation. No functional changes intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-11-qiuxu.zhuo@intel.com 2026-07-30T18:33:24+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2026-07-30T02:42:37+00:00 urn:sha1:1f43c17ce550e8ed628afd7fb3226c904076f864 Several resource configuration tables differ only in their num_imc value, while all other fields are identical. Their only purpose is to describe the number of memory controllers supported by a platform. Since IMC count is now detected at runtime, these duplicate tables no longer carry any unique platform information. Reuse the shared configurations and remove the redundant tables. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-10-qiuxu.zhuo@intel.com 2026-07-30T18:33:06+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2026-07-30T02:42:36+00:00 urn:sha1:e492449e39b7aee9bfcb1bda3181fa942d24cdd2 The igen6_edac currently relies on res_config::num_imc to describe the number of memory controllers supported by each SoC. As a result, adding support for a new platform requires updating this configuration even though the hardware can be discovered at runtime. Instead, detect the number of present memory controllers at runtime and size the driver state accordingly. This eliminates the need to update res_config whenever a new SoC variant is added. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-9-qiuxu.zhuo@intel.com