kernel/git/next/linux-next.git/drivers/iio, branch master

Merge branch 'headers' of git://git.infradead.org/users/willy/pagecache.git

2026-09-04T18:38:02+00:00

# Conflicts: # net/ceph/osd_client.c

Merge branch 'togreg' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git

2026-09-04T17:52:17+00:00

# Conflicts: # drivers/iio/adc/ade9000.c

iio: light: vcnl4000: use sysfs_emit() for near_level

2026-09-01T15:47:06+00:00

Use sysfs_emit() instead of sprintf() for writing to the sysfs output buffer. sysfs_emit() is aware of the buffer's PAGE_SIZE limit and is the preferred helper for sysfs callbacks. Signed-off-by: Donggeun Yoo Reviewed-by: Joshua Crofts Signed-off-by: Jonathan Cameron

iio: adc: rockchip_saradc: Add support for RV1106

2026-09-01T01:28:46+00:00

The Successive Approximation ADC (SARADC) in RV1106 uses the v2 controller and supports: - 10-bit resolution - Up to 1MS/s sampling rate - 2 single-ended input channels "dt-bindings: iio: adc: rockchip-saradc: Add RV1106 compatible" documents "rockchip,rv1106-saradc" as falling back to "rockchip,rk3588-saradc" (see Link below). The two IP blocks are not equivalent, though: per the RV1106 TRM v0.3, chapter 20 (SAR-ADC), RV1106 only has 2 channels at 10-bit resolution, versus 8 channels at 12-bit on RK3588. Without a dedicated match entry, the driver binds via the fallback compatible and uses the RK3588 channel table, which reports 8 channels instead of 2, and an in_voltage_scale that is off by exactly 4x (4096 vs 1024 full-scale). Add a dedicated compatible/data pair for RV1106 with the correct 2-channel, 10-bit layout. Tested on a custom RV1106-based board, with: &saradc { vref-supply = <&vcc_saradc>; /* 1.8V fixed regulator */ status = "okay"; }; Before this patch: # ls /sys/bus/iio/devices/iio:device0/in_voltage*_raw | wc -l 8 # cat /sys/bus/iio/devices/iio:device0/in_voltage_scale 0.439453125 After this patch: # ls /sys/bus/iio/devices/iio:device0/in_voltage*_raw | wc -l 2 # cat /sys/bus/iio/devices/iio:device0/in_voltage_scale 1.757812500 Link: https://lore.kernel.org/all/20260714131631.v2.1.0b846080833e4b836793c43fc26d1c6d817cf9b4@changeid/ Signed-off-by: Vladislav Leonov Signed-off-by: Jonathan Cameron

iio: adc: ti-ads112c04: Add support for TI ADS112C04

2026-09-01T01:28:37+00:00

Add IIO driver support for the Texas Instruments ADS112C04 (16-bit) delta-sigma ADCs. The driver implements: - Single-shot conversions using the IIO raw read interface. - Dynamic parsing of single-ended and differential channels from device tree child nodes. - Hardware interrupt support via the DRDY pin, falling back to software polling if no IRQ is provided. - Per-channel reference source selection (internal 2.048V, external REFP/REFN, or AVDD) via the reference-sources device tree property. refn-supply is not yet supported. - Hardware reset via the reset controller framework, falling back to the RESET command when no reset controller is present. Signed-off-by: Kyle Hsieh Reviewed-by: Andy Shevchenko Reviewed-by: David Lechner Signed-off-by: Jonathan Cameron

iio: imu: inv_icm42600: do not read FIFO count for watermark it

2026-08-31T01:58:31+00:00

Optimize data reading for high frequencies by not reading FIFO count in case of watermark interrupt. We cannot already read more than watermark samples because of the timestamping mechanism. It is required to not perturb the timing between the watermark interrupts. Since we also know there is at least watermark samples in the FIFO, let's just read these watermark FIFO samples directly without reading FIFO count in this case. Signed-off-by: Jean-Baptiste Maneyrol Signed-off-by: Jonathan Cameron

iio: imu: inv_icm42600: simplify watermark computation by using GCD

2026-08-31T01:58:31+00:00

The watermark computation was in fact resulting in computing the GCD of the latencies when both sensors are on. GCD is required because of the IIO buffer watermark. Move to use gcd() and update documentation accordingly. Signed-off-by: Jean-Baptiste Maneyrol Signed-off-by: Jonathan Cameron

iio: imu: inv_icm42600: use 2 sensors fixed packet size of 16 bytes

2026-08-31T01:58:31+00:00

Sometimes dynamic switch between 1 sensor frame to 2 sensors frame is not working when there are too much frames already in the FIFO. By moving accel/gyro on sleep before turning FIFO on, we are storing many FIFO frames before updating the frame format hitting the bug everytime. Fix that by always using the 2 sensors frame of 16 bytes. Also update the hwfifo max watermark reported. Signed-off-by: Jean-Baptiste Maneyrol Signed-off-by: Jonathan Cameron

iio: imu: inv_icm42600: sleep before enabling FIFO data

2026-08-31T01:58:31+00:00

When turning accel or gyro on, a sleep is required for letting the mechanical part stabilize before reporting correct data. Move the sleep before enabling FIFO data to prevent push of incorrect data. We need to unlock the driver mutex while sleeping to not block data of the other sensor if it is running. There is no possible race here because we are already under IIO mode mutex locked since it is a IIO buffer callback. Signed-off-by: Jean-Baptiste Maneyrol Signed-off-by: Jonathan Cameron

iio: adc: ad4080: allow debugfs register access to both channels

2026-08-31T01:58:31+00:00

The dual-channel parts (AD4880/AD4883/AD4884) are built from two independent ADC dies, each with its own SPI chip select and register map. They are presented as a single IIO device because the FPGA interleaves both dies into one DMA stream, so only one direct_reg_access debugfs file is created and it can only reach channel A's regmap. Channel B's registers are therefore inaccessible, which blocks bring-up and debugging of the second die. Select the target die through the debugfs register address: the low 8 bits are the register offset and the upper bits are the channel index (0x0nn selects channel A, 0x1nn channel B). A read returns the real register value of the selected die and each die is addressed independently; single-channel parts only accept channel 0. Signed-off-by: Antoniu Miclaus Signed-off-by: Jonathan Cameron