The linux-next integration testing tree https://git.rulkc.org/pub/scm/linux/kernel/git/next/linux-next.git/atom?h=master 2026-09-22T10:04:27+00:00 2026-09-22T10:04:27+00:00 Mark Brown broonie@kernel.org 2026-09-22T10:04:27+00:00 urn:sha1:b73181161ded7e1286aab16827346b95cfaa9ee8 2026-09-22T10:04:24+00:00 Mark Brown broonie@kernel.org 2026-09-22T10:04:24+00:00 urn:sha1:98df1c7e293c62d7d6a3c4a316548756429fb13d 2026-09-21T13:20:45+00:00 Nuno Sá nuno.sa@analog.com 2026-09-14T13:42:01+00:00 urn:sha1:68d7115d77a873c28d8c7d2f239c3d9ca83bf39f Commit af2792abd455 ("mtd: spi-nor: sfdp: get the 1-1-8 and 1-8-8 protocol from SFDP") taught the core to discover octal read support from BFPT, but the 4-Byte Address Instruction Table parser was never extended accordingly. Parse the 1-1-8 and 1-8-8 page program bits of 4BAIT DWORD1 and set the corresponding 4-byte opcodes, so that octal writes stay available once the flash switches to the 4-byte address instruction set. This is in preparation of adding support for the ISSI IS25WX01G, a 1 Gbit octal flash which is beyond the 3-byte address range and advertises 4-byte 1-1-8 and 1-8-8 page program instructions. Signed-off-by: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Michael Walle <mwalle@kernel.org> 2026-09-21T07:52:26+00:00 Miquel Raynal miquel.raynal@bootlin.com 2026-09-21T06:43:56+00:00 urn:sha1:ceedf3193cac49ddb488518616587484093d66e4 There is an ID collision with chips of same density from the JW family (which it self conflicted with yet another family). Chips are very similar in practice, it is mostly a matter of electrical differences (mostly power consumption being lower) as well as the addition of inline ECC capability. 16 bytes chunks are protected against single errors. In case a non-aligned write happens, ECC is locally disabled until the next erase. Another significant difference is that PW chips identify themselves as supporting the new SFDP (rev F) QER field which forces an alternate write SR2 opcode (0x31). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Michael Walle <mwalle@kernel.org> 2026-09-21T07:52:26+00:00 Miquel Raynal miquel.raynal@bootlin.com 2026-09-21T06:43:55+00:00 urn:sha1:8df89f0fe8e8ecc345c5a9e3ce49e41139eb4a0c There is an ID collision with chips of same density from the JW family (which it self conflicted with yet another family). Chips are very similar in practice, it is mostly a matter of electrical differences (mostly power consumption being lower) as well as the addition of inline ECC capability. 16 bytes chunks are protected against single errors. In case a non-aligned write happens, ECC is locally disabled until the next erase. Another significant difference is that PW chips identify themselves as supporting the new SFDP (rev F) QER field which forces an alternate write SR2 opcode (0x31). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Michael Walle <mwalle@kernel.org> 2026-09-21T07:52:26+00:00 Miquel Raynal miquel.raynal@bootlin.com 2026-09-21T06:43:54+00:00 urn:sha1:d96b00b230d0512844d0e9c9bc391cdc30ab653b There is an ID collision with chips of same density from the JW family (which it self conflicted with yet another family). Chips are very similar in practice, it is mostly a matter of electrical differences (mostly power consumption being lower) as well as the addition of inline ECC capability. 16 bytes chunks are protected against single errors. In case a non-aligned write happens, ECC is locally disabled until the next erase. Another significant difference is that PW chips identify themselves as supporting the new SFDP (rev F) QER field which forces an alternate write SR2 opcode (0x31). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Michael Walle <mwalle@kernel.org> 2026-09-21T07:52:26+00:00 Miquel Raynal miquel.raynal@bootlin.com 2026-09-21T06:43:53+00:00 urn:sha1:03613e40f15d704013f90b2405c4a3bc6b751207 There is an ID collision with chips of same density from the JW family (which it self conflicted with yet another family). Chips are very similar in practice, it is mostly a matter of electrical differences (mostly power consumption being lower) as well as the addition of inline ECC capability. Unlike the other (bigger) densities from the PW family, this part has no ECC support. Another significant difference is that PW chips identify themselves as supporting the new SFDP (rev F) QER field which forces an alternate write SR2 opcode (0x31). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Michael Walle <mwalle@kernel.org> 2026-09-21T07:52:25+00:00 Miquel Raynal miquel.raynal@bootlin.com 2026-09-21T06:43:52+00:00 urn:sha1:b60627be8faf82b2c64d86c83c27c730423d0524 There is an ID collision between chips of same density from the JW family (which it self conflicted with yet another family) with new PW parts. Chips are very similar in practice, it is mostly a matter of electrical differences (mostly power consumption being lower) as well as the addition of inline ECC capability for the higher devices (> 32Mb). Chips with ECC capability protect 16 bytes chunks are against single errors. In case a non-aligned write happens, ECC is locally disabled until the next erase. Another significant difference is that PW chips identify themselves as supporting the new SFDP (rev F) QER field which forces an alternate write SR2 opcode (0x31). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Michael Walle <mwalle@kernel.org> 2026-09-21T07:52:25+00:00 Miquel Raynal miquel.raynal@bootlin.com 2026-09-21T06:43:51+00:00 urn:sha1:136588c583adc2c73934bb0e89877fd1a8b91305 There is an ID collision with chips of same density from the JW family (which it self conflicted with yet another family). Chips are very similar in practice, it is mostly a matter of electrical differences (mostly power consumption being lower) as well as the addition of inline ECC capability. 16 bytes chunks are protected against single errors. In case a non-aligned write happens, ECC is locally disabled until the next erase. Another significant difference is that PW chips identify themselves as supporting the new SFDP (rev F) QER field which forces an alternate write SR2 opcode (0x31). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Michael Walle <mwalle@kernel.org> 2026-09-21T07:52:25+00:00 Miquel Raynal miquel.raynal@bootlin.com 2026-09-21T06:43:50+00:00 urn:sha1:b8a959f55f9f1806865aa38304289d2abaceacf4 There is an ID collision with chips of same density from the JW family (which it self conflicted with yet another family). Chips are very similar in practice, it is mostly a matter of electrical differences (mostly power consumption being lower) as well as the addition of inline ECC capability. 16 bytes chunks are protected against single errors. In case a non-aligned write happens, ECC is locally disabled until the next erase. Another significant difference is that PW chips identify themselves as supporting the new SFDP (rev F) QER field which forces an alternate write SR2 opcode (0x31). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Michael Walle <mwalle@kernel.org>