kernel/git/next/linux-next.git/drivers/phy/phy-rockchip-usb.c, branch master

phy: Group vendor specific phy drivers

2017-06-01T09:58:33+00:00

Adding vendor specific directories in phy to group phy drivers under their respective vendor umbrella. Also updated the MAINTAINERS file to reflect the correct directory structure for phy drivers. Signed-off-by: Vivek Gautam Acked-by: Heiko Stuebner Acked-by: Viresh Kumar Acked-by: Krzysztof Kozlowski Acked-by: Yoshihiro Shimoda Reviewed-by: Jaehoon Chung Cc: Kishon Vijay Abraham I Cc: David S. Miller Cc: Geert Uytterhoeven Cc: Yoshihiro Shimoda Cc: Guenter Roeck Cc: Heiko Stuebner Cc: Viresh Kumar Cc: Maxime Ripard Cc: Chen-Yu Tsai Cc: Sylwester Nawrocki Cc: Krzysztof Kozlowski Cc: Jaehoon Chung Cc: Stephen Boyd Cc: Martin Blumenstingl Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-usb@vger.kernel.org Signed-off-by: Kishon Vijay Abraham I

phy: rockchip-usb: Add vbus regulator support.

2017-04-10T11:13:41+00:00

On rockchip devices vbus is supplied by a separate power supply, often through a regulator. Add support for describing the the regulator in device-tree following the same convention as several other usb phy's. Signed-off-by: Sjoerd Simons Signed-off-by: Kishon Vijay Abraham I

phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup

2016-09-10T12:01:40+00:00

It is a hardware bug in RK3288, the only way to solve it is to reset the phy. Signed-off-by: Randy Li Signed-off-by: Kishon Vijay Abraham I

phy: rockhip-usb: use devm_add_action_or_reset()

2016-07-04T12:37:39+00:00

If devm_add_action() fails we are explicitly calling the cleanup to free the resources allocated. Lets use the helper devm_add_action_or_reset() and return directly in case of error, as we know that the cleanup function has been already called by the helper if there was any error. Signed-off-by: Sudip Mukherjee Reviewed-by: Heiko Stuebner Signed-off-by: Kishon Vijay Abraham I

phy: rockchip-usb: should be a child device of the GRF

2016-07-04T12:37:39+00:00

The usb-phy is fully enclosed in the general register files (GRF). Therefore as seen from the device-tree it shouldn't be a separate platform-device but instead a sub-device of the GRF - using the simply-mfd mechanism. As the usb-phy is part of the kernel for some releases now, we keep the old (and now deprecated) binding for compatibility purposes. Signed-off-by: Heiko Stuebner Signed-off-by: Kishon Vijay Abraham I

phy: rockhip-usb: Remove CLK_IS_ROOT

2016-04-30T14:42:28+00:00

This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Cc: Heiko Stuebner Signed-off-by: Stephen Boyd Signed-off-by: Kishon Vijay Abraham I

phy: rockchip-usb: add handler for usb-uart functionality

2016-03-01T11:43:50+00:00

Most newer Rockchip SoCs provide the possibility to use a usb-phy as passthrough for the debug uart (uart2), making it possible to for example get console output without needing to open the device. This patch adds an early_initcall to enable this functionality conditionally via the commandline and also disables the corresponding usb controller in the devicetree. Currently only data for the rk3288 is provided, but at least the rk3188 and arm64 rk3368 also provide this functionality and will be enabled later. On a spliced usb cable the signals are tx on white wire(D+) and rx on green wire(D-). The one caveat is that currently the reconfiguration of the phy happens as early_initcall, as the code depends on the unflattened devicetree being available. Everything is fine if only a regular console is active as the console-replay will happen after the reconfiguation. But with earlycon active output up to smp-init currently will get lost. The phy is an optional property for the connected dwc2 controller, so we still provide the phy device but fail all phy-ops with -EBUSY to make sure the dwc2 does not try to transmit anything on the repurposed phy. Signed-off-by: Heiko Stuebner Signed-off-by: Kishon Vijay Abraham I

phy: rockchip-usb: expose the phy-internal PLLs

2015-12-20T09:51:38+00:00

The USB phys on Rockchip SoCs contain their own internal PLLs to create the 480MHz needed. Additionally this PLL output is also fed back into the core clock-controller as possible source for clocks like the GPU or others. Until now this was modelled incorrectly with a "virtual" factor clock in the clock controller. The one big caveat is that if we turn off the usb phy via the siddq signal, all analog components get turned off, including the PLLs. It is therefore possible that a source clock gets disabled without the clock driver ever knowing, possibly making the system hang. Therefore register the phy-plls as real clocks that the clock driver can then reference again normally, making the clock hirarchy finally reflect the actual hardware. The phy-ops get converted to simply turning that new clock on and off which in turn controls the siddq signal of the phy. Through this the driver gains handling for platform-specific data, to handle the phy->clock name association. Signed-off-by: Heiko Stuebner Reviewed-by: Douglas Anderson Signed-off-by: Kishon Vijay Abraham I

phy: rockchip-usb: add compatible values for rk3066a and rk3188

2015-12-20T09:51:38+00:00

We need custom handling for these two socs in the driver shortly, so add the necessary compatible values to binding and driver. Signed-off-by: Heiko Stuebner Signed-off-by: Kishon Vijay Abraham I

phy: rockchip-usb: move per-phy init into a separate function

2015-12-20T09:51:38+00:00

This unclutters the loop in probe a lot and makes current (and future) error handling easier to read. Signed-off-by: Heiko Stuebner Reviewed-by: Douglas Anderson Signed-off-by: Kishon Vijay Abraham I