kernel/git/next/linux-next.git/drivers/phy/qualcomm/phy-qcom-edp.c, branch master

phy: qcom: edp: Add PHY-specific LDO config for eDP low vdiff

2026-05-03T17:04:48+00:00

For eDP low vdiff, the LDO setting depends on the PHY version rather than being a simple 0x0 or 0x1 value. Introduce a PHY callback to program the correct LDO setting according to the HPG. Since SC7280/SC8180X uses different LDO settings from SA8775P/SC8280XP, introduce qcom_edp_phy_ops_v3 to keep the LDO setting correct. Cc: stable@vger.kernel.org Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver") Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Tested-by: Konrad Dybcio # SC8280XP X13s Link: https://patch.msgid.link/20260427-edp_phy-v5-5-3bb876824475@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: edp: Fix AUX_CFG8 programming for DP mode

2026-05-03T17:04:47+00:00

AUX_CFG8 depends on whether the PHY is operating in eDP or DP mode, not the selected swing/pre-emphasis table. All supported platforms already have the proper tables, so remove the unnecessary check. Cc: stable@vger.kernel.org Fixes: 6078b8ce070c ("phy: qcom: edp: Add set_mode op for configuring eDP/DP submode") Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Yongxing Mou Link: https://patch.msgid.link/20260427-edp_phy-v5-4-3bb876824475@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: edp: Add SC7280/SC8180X swing/pre-emphasis tables

2026-05-03T17:04:47+00:00

SC7280 and SC8180X previously shared the same cfg because they did not use swing/pre-emphasis tables. Add the corresponding tables for these platforms. Since they have different PHY sub-versions, their eDP/DP mode tables also differ, so move SC8180X to its own cfg instead of reusing the SC7280 one. Signed-off-by: Yongxing Mou Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260427-edp_phy-v5-3-3bb876824475@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: edp: Add eDP/DP mode switch support

2026-05-03T17:04:47+00:00

The eDP PHY supports both eDP/DP modes, each requiring a different swing/pre-emphasis table. However, the driver currently uses a fixed static table for eDP programming rather than selecting the appropriate table based on the current mode. Add separate tables for eDP and DP modes, and select the appropriate table dynamically based on the current mode. Glymur's DP mode table differs from the other platforms, add a dedicated table for it. This also fixes the table mismatch for X1E80100 (eDP) and SA8775P (DP). Cc: stable@vger.kernel.org Fixes: 3f12bf16213c ("phy: qcom: edp: Add support for eDP PHY on SA8775P") Reviewed-by: Konrad Dybcio Signed-off-by: Yongxing Mou Link: https://patch.msgid.link/20260427-edp_phy-v5-2-3bb876824475@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: edp: Unify generic DP/eDP swing and pre-emphasis tables

2026-05-03T17:04:47+00:00

The current eDP and DP swing/pre-emphasis tables do not match the HPG requirements for the supported platforms, correct the table accordingly. The generic tables which can be shared as follows: DP mode： -sa8775p/sc7280/sc8280xp/x1e80100 -glymur -sc8180x eDP mode(low vdiff): -glymur/sa8775p/sc8280xp/x1e80100 -sc7280 -sc8180x The proper tables for SC8180X and SC7280 will be added in a later patch, since they need separate table. Cc: stable@vger.kernel.org Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver") Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Yongxing Mou Link: https://patch.msgid.link/20260427-edp_phy-v5-1-3bb876824475@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: edp: Fix NULL pointer dereference for phy v6 (x1e80100)

2026-01-14T13:37:30+00:00

For Glymur SoC support, the com_clk_fwd_cfg callback was added, and a stub implementation was added for the v4 of the hardware. However it was omitted for the v6, causing a NULL pointer dereference oops on Hamoa/Purwa (X1E/X1P) SoC devices. Fix by adding the appropriate stub. Fixes: add66a6673bc ("phy: qcom: edp: Add Glymur platform support") Reviewed-by: Abel Vesa Signed-off-by: Val Packett Reviewed-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Tested-by: Yijie Yang # Purwa-IoT-EVK Link: https://patch.msgid.link/20260111083317.604754-1-val@packett.cool Signed-off-by: Vinod Koul

phy: qcom: edp: Add Glymur platform support

2026-01-01T11:03:58+00:00

The Qualcomm Glymur platform has the new v8 version of the eDP/DP PHY. So rework the driver to support this new version and add the platform specific configuration data. While at it, add the rest of the AUX_CFG reset values for the v4 and v5 platforms, which makes the handling of the platforms specific array cleaner, as they are single sized now. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-glymur-support-v6-4-4fcba75a6fa9@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: edp: Fix the DP_PHY_AUX_CFG registers count

2026-01-01T11:03:57+00:00

On all platforms supported by this driver, there are 13 DP_PHY_AUX_CFGx registers. This hasn't been an issue so far on currently supported platforms, because the init sequence never spanned beyond DP_PHY_AUX_CFG9. However, on the new upcoming Glymur platform, these are updated along with the rest of the init sequence. So update the size of the array holding the config to 13. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-glymur-support-v6-2-4fcba75a6fa9@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: edp: Make the number of clocks flexible

2026-01-01T11:02:59+00:00

On X Elite, the DP PHY needs another clock called ref, while all other platforms do not. The current X Elite devices supported upstream work fine without this clock, because the boot firmware leaves this clock enabled. But we should not rely on that. Also, even though this change breaks the ABI, it is needed in order to make the driver disables this clock along with the other ones, for a proper bring-down of the entire PHY. So in order to handle these clocks on different platforms, make the driver get all the clocks regardless of how many there are provided. Cc: stable@vger.kernel.org # v6.10 Fixes: db83c107dc29 ("phy: qcom: edp: Add v6 specific ops and X1E80100 platform support") Reviewed-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Signed-off-by: Abel Vesa Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-missing-refclk-v5-2-3f45d349b5ac@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: edp: Add support for eDP PHY on SA8775P

2024-10-17T14:46:30+00:00

Add support for eDP PHY v5 found on the Qualcomm SA8775P platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Soutrik Mukhopadhyay Link: https://lore.kernel.org/r/20241004103046.22209-4-quic_mukhopad@quicinc.com Signed-off-by: Vinod Koul