kernel/git/next/linux-next.git/drivers/phy/qualcomm, branch master

phy: qualcomm: qmp-combo: Add preliminary USB4 support

2026-09-15T06:25:55+00:00

Some Combo PHYs (so far only on SC8280XP, X1E80100 and Glymur), come in a flavor called USB43DP, which as the name implies, features USB4, USB3 and DP signal processing capabilities. In that architecture, USB3 and USB4 PHYs share the same USB_PLL while featuring separate logic spaces. The DP part is roughly the same as on the instances without USB4. The USB4 and USB3/DP operation modes of the PHY are mutually exclusive. Only one USB protocol (and flavor of pipe clock) can be active at a given moment (not to be confused with USB3 not being able to be tunneled as USB4 packets - that of course remains possible). The DP PLL is still used for clocking tunneled DP links. It may be turned off to save power when no tunnels are active, but that's left as a TODO item for now. Due to the nature of USB4, the Type-C handling happens entirely inside the Host Router, and as such the QMPPHY's mux_set() function is nullified for the period when USB4 PHY remains active. This is strictly necessary, as the Host Router driver is going to exercise manual control over the USB4 PHY's power state, which is needed by the suspend and resume flows. Failure to control that synchronously with other parts of the code results in a SoC crash by unlocked access. Because of that, a new struct phy is spawned to expose the USB4 mode, along with a .set_mode callback to allow toggling between USB4 and TBT3 submodes. Thunderbolt 3, having a number of differences vs USB4, requires a couple specific overrides, pertaining to electrical characteristics, which are easily accommodated for. Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam Signed-off-by: Konrad Dybcio Link: https://patch.msgid.link/20260908-topic-usb4phy-v5-3-73aac69578ef@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: qmp: Fix alignment in pcs-v8_50 register header

2026-09-15T06:25:54+00:00

Fix up the whitespace so all offsets align. No functional change. Signed-off-by: Shawn Guo Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260910011500.659353-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Shikra

2026-09-15T06:25:53+00:00

Add QMP PCIe PHY Gen2x1 support. Signed-off-by: Sushrut Shree Trivedi Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20260831-shikra-upstream-v2-4-406661d75afa@oss.qualcomm.com Signed-off-by: Vinod Koul

Merge tag 'phy-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2026-08-24T19:19:23+00:00

Pull phy updates from Vinod Koul: "As usual bunch of new device and driver support and updates to existing drivers and addition of Manivannan to help with reviews. New Support: - Mediatek MT8196 DSI PHY support - Renesas RZ/G3L usb2 support - Qualcomm SM8475 QMP USB PHY and PCIe phy, IPQ9650 QMP PCIe PHY, QUSB2 Phy for Shikra SoC, Hawi support for QMP PCIe phy and UFS PHY. Glymur QMP PCIe Multi-PHY driver and multiple link-mode support, ipq5210 PCIe phy support - Spacemit USB3/PCIe comb PHY driver Updates: - Samsung hdptx driver improvements for modernizing the register access and code cleanup - Qualcomm drop duplicate v8 DP headers, improved runtime handling for qmp drivers - Rockchip clock lane phase tuning and 2500 Mbps support and TMDS rate handling - Freescale imx8mq improvements for runtime pm, pd handling" * tag 'phy-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (76 commits) MAINTAINERS: Add Manivannan Sadhasivam as the Reviewer for Generic PHY Framework phy: rockchip-samsung-dcphy: fix out-of-range max_register phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY phy: rockchip: samsung-hdptx: Consistently use bitfield macros phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16() phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling phy: rockchip: samsung-hdptx: Consolidate consumer_put on error path phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL phy: rockchip: samsung-hdptx: Guard against clk rate integer underflow phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc phy: qcom: qmp-combo: Drop qmp_v4_calibrate_dp_phy phy: qcom: qmp-combo: Correct pre-emphasis table for QMP v4 DP PHYs phy: renesas: rcar-gen3-usb2: Ignore missing VBUS regulator phy: qcom: qmp-pcie: Add support for SM8475 Gen3x1 PCIe0 port phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHY ...

phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver

2026-08-11T16:54:03+00:00

Some QMP PCIe PHY hardware blocks support multiple link topologies (e.g. x8 or x4+x4) selected via a TCSR register. The existing single-instance QMP PCIe PHY driver has no way to model this: it assumes a single cfg per DT node and instantiates exactly one PHY. Add a dedicated driver for this class of PHY. Match data carries a per-mode cfg table; qmp_pcie_multiphy_probe() reads the current link mode from the TCSR register pointed to by "qcom,link-mode", looks up the corresponding cfg array, and instantiates one qmp_pcie per sub-PHY required by that link mode, registering the clock and #phy-cells = <1> phy providers so consumers can address individual sub-PHYs by index. The driver inherits the phy setting and link-mode programmed by firmware, so only the no_csr reset is used and no phy setting tables are provided. Add the first match data and compatible, qcom,glymur-qmp-gen5x8-pcie-phy, for the Glymur Gen5 PCIe PHY that can bifurcate into two x4 links or operate as a single x8 link. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu Link: https://patch.msgid.link/20260807-glymur_linkmode_0807-v9-2-dd1c7e236e29@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: qmp-combo: Drop qmp_v4_calibrate_dp_phy

2026-08-11T11:12:38+00:00

There are no downstream device trees that specify five values in the qcom,aux-cfg1-settings array. Plus, after cross referencing both downstream device trees and entries which refer this function, only 0x13 is specified. Since 0x13 is written at initialization time, drop this function as a whole, and remove now unused variable assignations. Fixes: aff188feb5e1 ("phy: qcom-qmp: add support for sm8250-usb3-dp phy") Reviewed-by: Dmitry Baryshkov Signed-off-by: Esteban Urrutia Link: https://patch.msgid.link/20260711-sm8450-qol-qmp-v2-2-d14353bd6ff4@proton.me Signed-off-by: Vinod Koul

phy: qcom: qmp-combo: Correct pre-emphasis table for QMP v4 DP PHYs

2026-08-11T11:12:38+00:00

Comparing sm8350 and sm8450 tables, this seems to be a typo. Fixes: ef14aff107bd ("phy: qcom: com-qmp-combo: add SM8350 & SM8450 support") Signed-off-by: Esteban Urrutia Link: https://patch.msgid.link/20260711-sm8450-qol-qmp-v2-1-d14353bd6ff4@proton.me Signed-off-by: Vinod Koul

phy: qcom: qmp-pcie: Add support for SM8475 Gen3x1 PCIe0 port

2026-08-07T06:23:37+00:00

This gets the port working. Tested with WCN6856 WLAN capabilities. Serdes, RX and PCS Misc tables had to be added, while TX and PCS tables were reused from SM8550, and PCS Lane1 was reused from SAR2130P. Signed-off-by: Esteban Urrutia Reviewed-by: Dmitry Baryshkov Link: https://patch.msgid.link/20260715-sm8475-bup-pcie-v2-3-48bd91a19abf@proton.me Signed-off-by: Vinod Koul

phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets

2026-08-07T06:23:37+00:00

Some SoCs such as SM8475 write data to registers using this offset, specifically SW_CTRL2 and MX_CTRL2. Add pcs_lane1 offset to V5 offsets to support this. Signed-off-by: Esteban Urrutia Fixes: 0fd0b31965b0 ("phy: qualcomm: qmp-pcie: add support for SAR2130P") Reviewed-by: Dmitry Baryshkov Link: https://patch.msgid.link/20260715-sm8475-bup-pcie-v2-2-48bd91a19abf@proton.me Signed-off-by: Vinod Koul

phy: qcom: qmp-usb: Prevent unnecessary PM runtime suspend at boot

2026-08-07T06:14:09+00:00

Runtime PM has to be enabled before creating the PHY, since phy_create() only enables runtime PM on the PHY device if it is already enabled on this parent device. This opens a small window where the device can be runtime suspended after pm_runtime_enable() and before the later pm_runtime_forbid(), causing an unnecessary suspend/resume cycle while the PHY is not yet registered. Take a runtime PM usage reference with pm_runtime_get_noresume() before enabling runtime PM and release it once the PHY has been created to prevent the device from being runtime suspended during that window. This also makes the probe path safe independently of pm_runtime_forbid(), which is a good preparation for potentially dropping the forbid() call in the future and letting runtime PM be enabled by default. Signed-off-by: Loic Poulain Link: https://patch.msgid.link/20260722-qcom-usb-phy-fix-null-v6-7-534f7e61b9a6@oss.qualcomm.com Signed-off-by: Vinod Koul