kernel/git/next/linux-next.git/drivers/pinctrl/qcom, branch master

Merge branch 'pinctrl-qcom/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git

2026-09-18T12:53:41+00:00

pinctrl: qcom: qcs8300: Fix intr_target_width

2026-09-17T09:49:25+00:00

The default width of the interrupt target field doesn't match the actual register layout. Fix it. Fixes: 0c4cd2cc87c8 ("pinctrl: qcom: add the tlmm driver for QCS8300 platforms") Assisted-by: LLM Signed-off-by: Konrad Dybcio Reviewed-by: Shawn Guo Link: https://patch.msgid.link/20260917-topic-tlmm_intr_width_fixes-v1-3-3bc1d056aa6b@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: maili: Fix intr_target_width

2026-09-17T09:49:25+00:00

The default width of the interrupt target field doesn't match the actual register layout. Fix it. Fixes: 251b53103a2e ("pinctrl: qcom: Add the tlmm driver for Maili platform") Assisted-by: LLM Signed-off-by: Konrad Dybcio Reviewed-by: Shawn Guo Link: https://patch.msgid.link/20260917-topic-tlmm_intr_width_fixes-v1-2-3bc1d056aa6b@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: hawi: Fix intr_target_width

2026-09-17T09:49:24+00:00

The default width of the interrupt target field doesn't match the actual register layout. Fix it. Fixes: 90700e10d2ad ("pinctrl: qcom: Add Hawi pinctrl driver") Assisted-by: LLM Signed-off-by: Konrad Dybcio Reviewed-by: Shawn Guo Link: https://patch.msgid.link/20260917-topic-tlmm_intr_width_fixes-v1-1-3bc1d056aa6b@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: nord: fix GPIO interrupt target width

2026-09-17T09:49:14+00:00

The TARGET_PROC field in the Nord GPIO_INTR_CFG registers occupies bits 11:8. Describe it as four bits wide so the common Qualcomm pinctrl code clears the complete field before routing an interrupt to the application processor. Without intr_target_width, the common code uses its three-bit default mask. Since GPIO_INTR_CFG resets with TARGET_PROC set to 0xf (NONE), bit 11 remains set when the driver programs HMSS target 3. The resulting target is 0xb (HPASS_DSP_1), observed as an interrupt configuration value of 0xb1b instead of 0x31b. The GPIO interrupt status is consequently latched, but the HMSS TLMM summary interrupt at GIC SPI 208 is never asserted. This affects all Nord GPIO interrupts using the TLMM summary path, including the Ethernet PHY interrupts on GPIO55 and GPIO141. Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms") Signed-off-by: Zhangfei Gao Reviewed-by: Konrad Dybcio Reviewed-by: Shawn Guo Link: https://patch.msgid.link/20260916085720.771498-1-zhangfei.gao@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: lpass-lpi: Include value in debugfs output

2026-09-16T09:00:49+00:00

As with other pinctrl providers, it's useful to be able to inspect the current GPIO state of the LPASS LPI pins during system integration and debugging. Extend the driver's debugfs logic to read the current value and include this in the printout. Signed-off-by: Bjorn Andersson Link: https://patch.msgid.link/20260915-pinctrl-lpass-debug-v1-1-bc49766c9f6f@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: Add MSM8952 tlmm pinctrl driver

2026-09-09T12:52:13+00:00

MSM8952 has same pin count and similar pinctrl functions mostly with msm8917, but some functions use different pins. Signed-off-by: Muzaffer Kadir Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260907-msm8952-pinctrl-v5-2-9a2d8d72ffdb@mainlining.org Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: Drop marketing name-prefixed duplicate defines

2026-09-08T07:33:10+00:00

They are identical and of no use. Drop them and use the common MSM prefix. Assisted-by: LLM Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://patch.msgid.link/20260907-topic-tlmm_define_cleanup-v1-1-accdf7859e4b@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: ipq5210: Publish the OF module alias

2026-09-07T08:51:54+00:00

The IPQ5210 TLMM platform driver can be a module and matches through ipq5210_tlmm_of_match. This table is not published for OF modalias matching. Publish the existing table, preserving arch_initcall ordering and the shared MSM pinctrl probe. Fixes: a549fe22376f ("pinctrl: qcom: Introduce IPQ5210 TLMM driver") Signed-off-by: hpp.iscas Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260905134340.67477-1-hppiscas@163.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: nord: Split QUP1 SE2/SE3 into lane-pair functions

2026-09-07T07:55:50+00:00

QUP1 SE2 and SE3 pack all four of their lanes pair-wise onto only two pins each: lanes 0/1 (I2C SDA/SCL) at mux value 2 and lanes 2/3 (UART TX/RX) at mux value 1, on gpio127/gpio128 and gpio129/gpio130 respectively. Both mux values were named "qup1_se2" (respectively "qup1_se3"), so the two distinct lane pairs became indistinguishable. msm_pinmux_set_mux() stops at the first entry matching the requested function, which means mux value 1 was always selected and the I2C lanes could never be muxed out. In practice i2c9 and i2c10 got the UART lanes and did not work, while uart9 and uart10 happened to be muxed correctly. Give each lane pair its own function, following the _01/_23 naming already used for the same hardware arrangement by the shikra, eliza, hawi and maili TLMM drivers. Both functions still cover the full pin pair, so a single pinctrl state per protocol remains sufficient. Drop gpio129/gpio130 from the SE2 group list, since those pins belong to SE3 and were never reachable through the SE2 function. Also rename QUP1 SE2/SE3 functions in the binding doc accordingly. While at it, add missing "gpio", "qup3_se0_mira" and "qup3_se0_mirb" to the binding function enum to get the list complete. Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Shawn Guo Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260830030201.135637-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski