kernel/git/next/linux-next.git/drivers/pinctrl/qcom, branch master

Merge branch 'pinctrl-qcom/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git

2026-07-21T15:16:54+00:00

Merge branch 'pinctrl-qcom/for-current' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git

2026-07-21T12:15:16+00:00

pinctrl: qcom: milos-lpass-lpi: Add Eliza LPASS LPI TLMM

2026-07-16T14:00:07+00:00

Eliza SoC has the same LPASS LPI pin mux functions as Milos but the slew rate control is in the same GPIO config register rather than a separate register. Add a new variant data struct with updated slew offsets and LPI_FLAG_SLEW_RATE_SAME_REG flag, reusing the existing pin descriptors and function table from Milos. Signed-off-by: Ravi Hothi Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260715132150.1322663-3-ravi.hothi@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now"

2026-07-08T11:47:36+00:00

This reverts commit 602cb14e310a ("pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now"). PDC interrupts no more break GPIOs PDC irqchip is updated to work for pass through or secondary mode. Update nwakeirq_map to reflect the GPIO to PDC irq map size. Signed-off-by: Maulik Shah Link: https://patch.msgid.link/20260707-hamoa_pdc_v3-v4-6-dfd1f4a3ae89@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: Acknowledge IRQs for PDC interrupt controller

2026-07-08T11:47:36+00:00

PDC needs to acknowledge incoming GPIO interrupts to clear the latched interrupt status in secondary mode of PDC. For level-triggered IRQs this happens automatically in irq_eoi() but for edge-triggered IRQs this needs to happen as early as possible in the IRQ handler. Implement this by using handle_fasteoi_ack_irq() as IRQ handler in this situation and forward the irq_ack() callback to the parent IRQ chip. Signed-off-by: Stephan Gerhold Signed-off-by: Maulik Shah Link: https://patch.msgid.link/20260707-hamoa_pdc_v3-v4-5-dfd1f4a3ae89@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

Replace by more specific (c files)

2026-07-03T05:38:17+00:00

Replace the #include of by the more specific where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich Acked-by: Takashi Sakamoto Acked-by: Bjorn Helgaas Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub)

pinctrl: qcom: Add the tlmm driver for Maili platform

2026-07-01T07:51:55+00:00

Add support for Maili TLMM configuration and control via the pinctrl framework. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Jingyi Wang Acked-by: Linus Walleij Link: https://patch.msgid.link/20260622-maili-pinctrl-v3-2-9724e1000471@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: sc8280xp: Add missing wakeup entries for GPIO143/151

2026-07-01T07:22:45+00:00

Pins 143 and 151 were not included in the PDC wakeup map. They are normally used for PCIe2A and PCIe3a PERST# respectively, so they're unlikely to be excercised in practice, but still add them for the sake of completeness. Fixes: c0e4c71a9e7c ("pinctrl: qcom: Introduce sc8280xp TLMM driver") Signed-off-by: Konrad Dybcio Link: https://patch.msgid.link/20260626-topic-8280_pinctrl_wakeup-v1-1-2ccb267148f5@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: Unconditionally mark gpio as wakeup enable

2026-06-30T14:51:33+00:00

GPIO interrupts that are wakeup capable need to be forwarded to wakeup capable parent irqchip. This is done via writing to it's wakeup_enable bit. Currently the bit is set only for PDC irqchip by checking skip_wake_irqs. skip_wake_irqs is set to differentiate between parent irqchips MPM and PDC. It is set when the parent irqchip is PDC to inform pinctrl about skipping the IRQ setting up at TLMM. However, the functionality to forward GPIO interrupts during SoC low power mode is needed regardless of which parent irqchip it is. Without the functionality it is impossible for MPM irqchip to detect the GPIO interrupt during SoC low power mode since for MPM irqchip the skip_wake_irqs is always false. Remove skip_wake_irqs condition when setting wakeup enable bit to allow forwarding GPIO interrupts for SoCs using MPM irqchip too. Fixes: 76b446f5b86e ("pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits") Signed-off-by: Sneh Mankad Reviewed-by: Maulik Shah Reviewed-by: Linus Walleij Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260616-enable_wakeup_capable_gpios-v3-1-fb59647d89cb@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski

pinctrl: qcom: Drop unused irq_data argument from msm_gpio_update_dual_edge_pos()

2026-06-30T14:34:33+00:00

The "struct irq_data *d" argument to msm_gpio_update_dual_edge_pos() is unused, drop it. Signed-off-by: Hans de Goede Acked-by: Linus Walleij Reviewed-by: Konrad Dybcio Reviewed-by: Mukesh Ojha Link: https://patch.msgid.link/20260623122732.6439-2-johannes.goede@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski