The linux-next integration testing tree https://git.rulkc.org/pub/scm/linux/kernel/git/next/linux-next.git/atom?h=master 2026-07-10T14:07:09+00:00 2026-07-10T14:07:09+00:00 Bartosz Golaszewski bartosz.golaszewski@oss.qualcomm.com 2026-07-06T12:44:31+00:00 urn:sha1:7a78fc208252c9a63eea5fe35259cbaf455b9227 Ahead of reworking the reference counting logic for platform devices, encapsulate the assignment of the OF node from another device for dynamically allocated platform devices with the provided helper. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://patch.msgid.link/20260706-pdev-fwnode-ref-v3-19-1ff028e33779@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2026-03-20T10:15:49+00:00 Biju Das biju.das.jz@bp.renesas.com 2026-03-18T12:08:52+00:00 urn:sha1:c961cc86af01246a7ce706bbc29072d314e00880 Fix a malformed MODULE_AUTHOR macro in the RZ/G2L USBPHY control driver where the author's name and opening angle bracket were missing, leaving only the email address with a stray closing >. Correct it to the standard Name <email> format. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 2026-02-23T16:03:28+00:00 Claudiu Beznea claudiu.beznea.uj@bp.renesas.com 2026-02-04T13:34:27+00:00 urn:sha1:e0cf84109bc6c6768337123f1de24ff56b41c91b The pwrrdy regmap_filed is allocated in rzg2l_usbphy_ctrl_pwrrdy_init() only if the driver data is set to RZG2L_USBPHY_CTRL_PWRRDY. Check that pwrrdy is valid before using it to avoid "Unable to handle kernel NULL pointer dereference at virtual address" errors. Fixes: c5b7cd9adefc ("reset: rzg2l-usbphy-ctrl: Add suspend/resume support") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 2026-01-24T15:40:25+00:00 Claudiu Beznea claudiu.beznea.uj@bp.renesas.com 2026-01-09T14:36:59+00:00 urn:sha1:c5b7cd9adefc5c060facaff6f54d3187480e4e1b The RZ/G2L USBPHY control driver is also used on the RZ/G3S SoC. The RZ/G3S SoC supports a power-saving mode in which power to most USB components (including the USBPHY control block) is turned off. Because of this, the USBPHY control block needs to be reconfigured when returning from power-saving mode. Add suspend/resume support to handle runtime suspend/resume of the device, assert/deassert the reset signal, and reinitialize the USBPHY control block. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 2026-01-24T15:40:24+00:00 Claudiu Beznea claudiu.beznea.uj@bp.renesas.com 2026-01-09T14:36:58+00:00 urn:sha1:2289ccd753deeb2cfe300d97e8697680c1ce556c Propagate the return value of regmap_field_update_bits() to avoid losing any possible error. With this, the return type of rzg2l_usbphy_ctrl_set_pwrrdy() was updated accordingly. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 2025-11-18T16:52:54+00:00 Dan Carpenter dan.carpenter@linaro.org 2025-11-01T13:27:07+00:00 urn:sha1:cea5d43b63b221522f8532a7894149f3d8d11f4b The devm_regmap_field_alloc() function never returns NULL, it returns error pointers. Update the error checking to match. Fixes: 58128aa88867 ("reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 2025-11-18T16:52:54+00:00 Claudiu Beznea claudiu.beznea.uj@bp.renesas.com 2025-10-23T13:58:08+00:00 urn:sha1:819ac6b055350c559dbb111f970a96e2c1c812ff The Renesas RZ/G3S SoC USB PHY HW block receives as input the USB PWRRDY signal from the system controller. Add support for the Renesas RZ/G3S SoC. Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 2025-11-18T16:52:54+00:00 Claudiu Beznea claudiu.beznea.uj@bp.renesas.com 2025-10-23T13:58:07+00:00 urn:sha1:78f2d64e484753bfede6a0e9eab0ef35830c34fb On the Renesas RZ/G3S SoC, the USB PHY block has an input signal called PWRRDY. This signal is managed by the system controller and must be de-asserted after powering on the area where USB PHY resides and asserted before powering it off. On power-on/resume the USB PWRRDY signal need to be de-asserted before enabling clock and switching the module to normal state (through MSTOP support). The power-on/resume configuration sequence must be: 1/ PWRRDY=0 2/ CLK_ON=1 3/ MSTOP=0 On power-off/suspend the configuration sequence should be: 1/ MSTOP=1 2/ CLK_ON=0 3/ PWRRDY=1 The CLK_ON and MSTOP functionalities are controlled by clock drivers. The suspend/resume support will be handled by different patches. After long discussions with the internal HW team, it has been confirmed that the HW connection b/w USB PHY block, the USB channels, the system controller, clock, MSTOP, PWRRDY signal is as follows: ┌──────────────────────────────┐ │ │◄── CPG_CLKON_USB.CLK0_ON │ USB CH0 │ ┌──────────────────────────┐ │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK2_ON │ ┌────────┐ ││host controller registers │ │ │ │ │ ││function controller registers│ │ │ PHY0 │◄──┤└───────────────────────────┘ │ │ USB PHY │ │ └────────────▲─────────────────┘ │ └────────┘ │ │ │ CPG_BUS_PERI_COM_MSTOP.MSTOP{6, 5}_ON │┌──────────────┐ ┌────────┐ ││USHPHY control│ │ │ ││ registers │ │ PHY1 │ ┌──────────────────────────────┐ │└──────────────┘ │ │◄──┤ USB CH1 │ │ └────────┘ │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK1_ON └─▲───────▲─────────▲──────┘ ││ host controller registers │ │ │ │ │ │└───────────────────────────┘ │ │ │ │ └────────────▲─────────────────┘ │ │ │ │ │ │ │ CPG_BUS_PERI_COM_MSTOP.MSTOP7_ON │PWRRDY │ │ │ │ CPG_CLK_ON_USB.CLK3_ON │ │ │ CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON │ ┌────┐ │SYSC│ └────┘ where: - CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X of different USB blocks, X in {0, 1, 2, 3} - CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the MSTOP of different USB blocks, X in {4, 5, 6, 7} - USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used by the USB CH0, USB CH1 - SYSC is the system controller block controlling the PWRRDY signal - USB CHx are individual USB block with host and function capabilities (USB CH0 have both host and function capabilities, USB CH1 has only host capabilities) The USBPHY control registers are controlled though the reset-rzg2l-usbphy-ctrl driver. The USB PHY ports are controlled by phy_rcar_gen3_usb2 (drivers/phy/renesas/phy-rcar-gen3-usb2.c file). The USB PHY ports request resets from the reset-rzg2l-usbphy-ctrl driver. The connection b/w the system controller and the USB PHY CTRL driver is implemented through the renesas,sysc-pwrrdy device tree property proposed in this patch. This property specifies the register offset and the bitmask required to control the PWRRDY signal. Since the USB PHY CTRL driver needs to be probed before any other USB-specific driver on RZ/G3S, control of PWRRDY is passed exclusively to it. This guarantees the correct configuration sequence between clocks, MSTOP bits, and the PWRRDY bit on probe/resume and remove/suspend. At the same time, changes are kept minimal by avoiding modifications to the USB PHY driver to also handle the PWRRDY itself. Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 2025-01-15T13:58:22+00:00 Arnd Bergmann arnd@arndb.de 2025-01-15T13:58:00+00:00 urn:sha1:bc6a958d76f29d238c12a85c1886f68651d0093b Reset controller fixes for v6.13 * Fix rzg2l-usb-vbus-regulator lookup by assigning the proper of node to the allocated platform device in the rzg2l-usbphy-ctrl driver. * tag 'reset-fixes-for-v6.13' of git://git.pengutronix.de/pza/linux: reset: rzg2l-usbphy-ctrl: Assign proper of node to the allocated device Link: https://lore.kernel.org/r/20250113163642.1757160-1-p.zabel@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de> 2024-12-06T15:51:28+00:00 Claudiu Beznea claudiu.beznea.uj@bp.renesas.com 2024-11-19T08:55:54+00:00 urn:sha1:1f8af9712413f456849fdf3f3a782cbe099476d7 The platform device named "rzg2l-usb-vbus-regulator", allocated by the rzg2l-usbphy-ctrl driver, is used to instantiate a regulator driver. This regulator driver is associated with a device tree (DT) node, which is a child of the rzg2l-usbphy-ctrl DT node. The regulator's DT node allows consumer nodes to reference the regulator and configure the regulator as needed. Starting with commit cd7a38c40b23 ("regulator: core: do not silently ignore provided init_data") the struct regulator_dev::dev::of_node is no longer populated using of_node_get(config->of_node) if the regulator does not provide init_data. Since the rzg2l-usb-vbus-regulator does not provide init_data, this behaviour causes the of_find_regulator_by_node() function to fails, resulting in errors when attempting to request the regulator. To fix this issue, call device_set_of_node_from_dev() for the "rzg2l-usb-vbus-regulator" platform device. Fixes: 84fbd6198766 ("regulator: Add Renesas RZ/G2L USB VBUS regulator driver") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20241119085554.1035881-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>