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2026-07-15arm64: dts: qcom: sm8250: correct frequencies in the Iris OPP tableDmitry Baryshkov
The OPP table for the Iris core is wrong, it copies the VDD table from the downstream kernel, but that table is written for the video_cc_mvs0_clk_src, while the upstream uses video_cc_mvs0_clk for OPP rate setting (which is clk_src divided by 3). Specify correct frequencies in the OPP table. Fixes: fa245b3f06cd ("arm64: dts: qcom: sm8250: Add venus DT node") Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260604-iris-venus-fix-sm8250-v7-2-7bd2f0e5bae8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sm8250: sort out Iris power domainsDmitry Baryshkov
On SM8250 Iris core requires two power rails to function, MX (for PLLs) and MMCX (for everything else). The commit fa245b3f06cd ("arm64: dts: qcom: sm8250: Add venus DT node") added only MX power rail, but omitted MMCX voltage levels. Add MMCX domain to the Iris device node. Fixes: fa245b3f06cd ("arm64: dts: qcom: sm8250: Add venus DT node") Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260604-iris-venus-fix-sm8250-v7-1-7bd2f0e5bae8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: qcom: ipq5018: Add GEPHY RX and TX clocksGeorge Moussalem
Add RX and TX clocks for the IPQ5018 GEPHY to enable the datapath. Fixes: f5f2b835e316 ("arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20260608-ipq5018-gephy-clocks-v4-3-fb2ccd56894b@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15dt-bindings: arm: qcom: Add Sony Xperia M2Erikas Bitovtas
Document the Sony Xperia M2, which is a smartphone based on the Qualcomm MSM8926 SoC. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Erikas Bitovtas <xerikasxx@gmail.com> Link: https://lore.kernel.org/r/20260610-yukon-eagle-v4-1-763d5698bd2c@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rateGeorge Moussalem
The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz. The CMN PLL driver did not account for the ref clock divider which is 2 for IPQ5018. Therefore, the computed rate was twice the actual output. With the driver now accounting for the CMN PLL reference clock divider (commit: 88c543fff756), set the correct reference clock rate. Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node") Signed-off-by: George Moussalem <george.moussalem@outlook.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260521-ipq5018-cmn-pll-rate-fix-v2-1-04b28a92e0f2@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Fix pm4125 vbus regulator compatible and constraintsRakesh Kota
Remove pm8150b fallback compatible from pm4125_vbus and fix regulator constraints in qrb2210 DTS files to use microvolt instead of microamp. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-add_pm4125-vbus-reg-v3-4-999d78a87b81@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sm8450: Add missing PCM_OUT portEsteban Urrutia
An error in dmesg shows there is a mismatch between controller and DT dout-ports. Add PCM_OUT port to fix this. Signed-off-by: Esteban Urrutia <esteuwu@proton.me> Link: https://lore.kernel.org/r/20260622-sm8450-qol-v1-4-37e2ee8df9da@proton.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sm8750: enable ETR and CTCU devicesJie Gan
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device and the CTCU device serves as the control unit for the ETR device. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20260204-enable-ctcu-and-etr-v3-3-0bb95c590ae1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: hamoa: enable ETR and CTCU devicesJie Gan
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device. The CTCU serves as the control unit for the ETR device, managing its behavior to determine how trace data is collected. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20260204-enable-ctcu-and-etr-v3-2-0bb95c590ae1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15dt-binding: document QCOM platforms for CTCU deviceJie Gan
Document the platforms that fallback to using the qcom,sa8775p-ctcu compatible for probing. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20260204-enable-ctcu-and-etr-v3-1-0bb95c590ae1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: glymur-crd: merge duplicate &pmh0101_gpios node extensionsGopikrishna Garmidi
The &pmh0101_gpios node is extended twice in glymur-crd.dtsi. The first extension defines the nvme_reg_en pinctrl state for the NVMe regulator enable GPIO (gpio14), and the second adds key_vol_up_default for the volume-up key (gpio6). Merge both pinctrl states into a single &pmh0101_gpios block to avoid the duplicate node extension. No functional change intended. Fixes: a5ad8a8e473c ("arm64: dts: qcom: Commonize Glymur CRD DTSI") Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260602-merge-duplicate-pmh0101-gpios-node-v2-1-251107b3d9fe@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: glymur: Add camera clock controller supportJagadeesh Kona
Add support for camera clock controller for camera clients to be able to request for camera clocks on Glymur SoC's. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260624-glymur_camcc-v5-3-a321df74b1a1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15Merge branch '20260624-glymur_camcc-v5-1-a321df74b1a1@oss.qualcomm.com' into ↵Bjorn Andersson
HEAD Merge Glymur clock controller binding from topic branch to get access to constants.
2026-07-15arm64: dts: qcom: qcs6490: Add Vicharak Axon MiniAjit Singh
Add DTS for the Vicharak Axon Mini board based on the Qualcomm QCS6490 SoC. This adds debug UART, eMMC, UFS, SDIO WLAN, USB 2.0 host, PCIe support along with regulators. The UFS ICE block is kept disabled because enabling it currently causes an SError during qcom_ice_create() on this board. UFS works without ICE. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Ajit Singh <blfizzyy@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260624125443.18729-4-blfizzyy@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15dt-bindings: arm: qcom: Add Vicharak Axon MiniAjit Singh
The Vicharak Axon Mini is a single-board computer based on the Qualcomm QCM6490 platform. Add the top-level compatible string for this board. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Ajit Singh <blfizzyy@gmail.com> Link: https://lore.kernel.org/r/20260624125443.18729-3-blfizzyy@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15dt-bindings: vendor-prefixes: Add prefix for VicharakAjit Singh
Vicharak develops computing platforms and manufactures single-board computers, including FPGA-integrated SBCs. Add a vendor prefix for them. Link: https://vicharak.in/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Ajit Singh <blfizzyy@gmail.com> Link: https://lore.kernel.org/r/20260624125443.18729-2-blfizzyy@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: eliza: Enable first QUPv3 wrapper by defaultAbel Vesa
Since each serial engine will be enabled as needed in each board dts, there is no point of disabling the first QUPv3 wrapper in SoC dtsi. So enable it by default. This is also now in line with the other SoCs, and also with the second QUPv3 wrapper. Fixes: 844807e1f89d ("arm64: dts: qcom: eliza: Add QUPv3, GPI DMA, SDHCI and LLCC nodes") Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260709-dts-qcom-eliza-enable-qupv3-1st-v1-1-e9a6904d0dea@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: eliza: Add CPU and LLCC BWMONsAbel Vesa
Describe the CPU and LLCC bandwidth monitor nodes for Eliza, together with the corresponding OPP tables. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260708-dts-qcom-eliza-add-bwmon-v1-1-602a409f550f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Correct whitespace around '='Krzysztof Kozlowski
Coding convention asks that equal character '=' in property assignment is preceded and followed by a space. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-4-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Use lowercase hex for unit addresses and valuesKrzysztof Kozlowski
DTS coding style prefers lowercase hex. No functional change. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-3-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Use tab for indentationKrzysztof Kozlowski
Correct mix of tabs+spaces into proper tab indented lines. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-2-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Use hyphen in node namesKrzysztof Kozlowski
DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-1-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Add Shikra EVK boardsKomal Bajaj
Add device trees for the Shikra EVK platform, which combines each of Shikra SoM variant with a common carrier board. Three EVK boards are introduced: - shikra-cqm-evk.dts: pairs with CQ2390M SoM (retail, with modem) - shikra-cqs-evk.dts: pairs with CQ2390S SoM (retail, without modem) - shikra-iqs-evk.dts: pairs with IQ2390S SoM (industrial, without modem) Also add shikra-evk.dtsi, it represents the common carrier-board and daughter-card configuration shared across all Shikra EVK variants. Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Co-developed-by: Monish Chunara <quic_mchunara@quicinc.com> Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com> Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Co-developed-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Co-developed-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-5-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Add Shikra IQ2390S SoM platformKomal Bajaj
Add device tree include for the IQ2390S variant of the Shikra System-on-Module, an industrial compute module integrating the Shikra SoC and PMIC for industrial IoT applications, designed to mount on carrier boards. - shikra-iqs-som.dtsi: Industrial SoM without modem (PM8150 PMIC) The DTSI includes the common shikra.dtsi and adds PM8150 PMIC regulator definitions specific to this variant. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-4-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Add Shikra CQ2390M SoM platformKomal Bajaj
Add device tree include for the CQ2390M variant of the Shikra System-on-Module, a compact compute module integrating the Shikra SoC and PMIC for IoT applications, designed to mount on carrier boards. - shikra-cqm-som.dtsi: Retail SoM with modem (PM4125 and PM8005 PMIC) The DTSI includes the common shikra.dtsi, adds PM4125 and PM8005 PMIC peripheral definitions specific to this variant. Since PM8005 regulators are controlled by rpmpd, so disabling the pm8005 regulators. Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-3-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: Introduce Shikra SoC base dtsiKomal Bajaj
Add initial device tree support for the Qualcomm Shikra SoC, an IoT-focused platform built around a heterogeneous CPU cluster (Cortex-A55 + Cortex-A78C) with RPM-based power and clock management. Enable support for the following peripherals: - CPU nodes - Global Clock Controller (GCC) - RPM-based clock controller (RPMCC) and power domains (RPMPD) - Interrupt controller - Top Level Mode Multiplexer (TLMM) - Debug UART - eMMC host controller - System timer and watchdog Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Co-developed-by: Monish Chunara <quic_mchunara@quicinc.com> Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com> Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Co-developed-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Co-developed-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-2-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15dt-bindings: arm: qcom: Document Shikra and its EVK boardsKomal Bajaj
Shikra is a Qualcomm IoT SoC available in a System-on-Module (SoM) form factor. The SoM integrates the Shikra SoC, PMICs, and essential passives, and is designed to be mounted on carrier boards. Three eSoM variant are introduced: - CQM: retail variant with integrated modem (PM4125 and PM8005 PMIC) - CQS: retail variant without modem (PM4125 and PM8005 PMIC) - IQS: industrial-grade variant without modem (PM8150 PMIC) Each SoM variant pairs with a common EVK carrier board provides debug UART, USB, and other peripheral interfaces. Add compatible strings for the CQ2390M, CQ2390S, IQ2390S SoM variant and its corresponding EVK boards. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-1-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15Merge branch ↵Bjorn Andersson
'20260608-shikra-gcc-rpmcc-clks-v5-2-94cefe092ee3@oss.qualcomm.com' into HEAD Merge Shikra RPM and global clock controller bindings from topic branch to get access to the various constants.
2026-07-15arm64: dts: qcom: Add HONOR MagicBook Art 14 device treeKonstantin Shabanov
Introduce support for the HONOR MagicBook Art 14 laptop. This version is based on the initial work by Kirill A. Korinsky [1] and Valentin Manea [2]. Supported: - Sound (with alsa-ucm-conf config [3]) - Speakers - Headphone jack - Bluetooth - Battery - HDMI - Touchpad - Keyboard (with backlight) - Touchscreen - WiFi - USB-C ports - USB-A port - UFS - H/W accel - DP over USB-C Untested: - Camera - Fingerprint reader - Sleep/Suspend Broken: - eDP [1]: https://lore.kernel.org/all/871px910m1.wl-kirill@korins.ky/ [2]: https://github.com/vamanea/linux-magicbook/blob/x1e80100-magicbook-6.19/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts [3]: https://github.com/alsa-project/alsa-ucm-conf/pull/755 Signed-off-by: Konstantin Shabanov <mail@etehtsea.me> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/all/871px910m1.wl-kirill@korins.ky/ Link: https://github.com/vamanea/linux-magicbook/blob/x1e80100-magicbook-6.19/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts Link: https://github.com/alsa-project/alsa-ucm-conf/pull/755 Link: https://lore.kernel.org/r/20260629154812.9066-4-mail@etehtsea.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15dt-bindings: arm: qcom: Add HONOR MagicBook Art 14Konstantin Shabanov
Document the X1E-80-100 variant of the HONOR MagicBook Art 14. Signed-off-by: Konstantin Shabanov <mail@etehtsea.me> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260629154812.9066-3-mail@etehtsea.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15dt-bindings: vendor-prefixes: Add HONORKonstantin Shabanov
Add vendor prefix for Honor Device Co., Ltd. Link: https://www.honor.com/ Signed-off-by: Konstantin Shabanov <mail@etehtsea.me> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260629154812.9066-2-mail@etehtsea.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: eliza: Add PMIC nodes for CQS SoM and MTPAbel Vesa
Both the CQS SoM and the MTP have the following array of PMICs: PMK8550, PM7550, 2x PM8550VS, PMIV0102 and PMR735D. Since on Eliza there is already support for SPMI multi-master, it is necessary to duplicate the devicetree description for each of these PMICs, due to the SPMI bus index and address. So add a new Elize specific dtsi for each of these PMICs and include all of them in both the CQS SoM and MTP board dts. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260630-dts-qcom-eliza-mtp-evk-add-pmics-v1-1-f4f320f7c88b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: eliza: Add Eliza CQS EVK boardAbel Vesa
The Eliza CQS EVK board combines the CQ7790S-based (Eliza) SoM with the common Eliza EVK base board, which provides connectors for different peripherals. Add a common Eliza EVK dtsi for the base board bits that can be reused alongside other Eliza SoM variants. Then, add the final Eliza CQS EVK dts, including the CQS SoM and common EVK dtsi. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260630-eliza-dts-qcs-evk-v4-3-18cbbdba6e7e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: eliza: Add Eliza CQS SoM platformAbel Vesa
The Eliza CQS (CQ7790S) System-on-Module is designed to be connected to an Eliza EVK base board. The SoM provides the SoC, PMICs, LPDDR and eMMC, while the EVK base board provides connectors for a multitude of peripherals. Add the Eliza CQS SoM DTSI so it can be included by the EVK board DTS. Describe the regulators and board clocks, enable eMMC support through SDHC1, specify the ADSP firmware and enable the ADSP remoteproc. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260630-eliza-dts-qcs-evk-v4-2-18cbbdba6e7e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15dt-bindings: arm: qcom: Document Eliza CQS SoM and its EVK boardAbel Vesa
Document the compatible strings for the Qualcomm Eliza CQS System-on-Module (SoM) and its EVK board. The SoM is populated with a CQ7790S Eliza variant, PMICs, LPDDR and eMMC. The SoM is then connected to the EVK base board, which provides a multitude of connectors for peripherals. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260630-eliza-dts-qcs-evk-v4-1-18cbbdba6e7e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sc8280xp-x13s: Use predefined MCLK pinctrlPengyu Luo
Now that the predefined MCLK pinctrl configuration is available in the sc8280xp SoC DTSI, switch the ThinkPad X13s to use it. Drop the local, duplicate MCLK pin definition from the camera pinctrl node. Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260629065905.15651-4-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sc8280xp: Add camera MCLK pinctrlPengyu Luo
Define pinctrl definitions to enable camera master clocks on sc8280xp. Suggested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Link: https://lore.kernel.org/r/20260629065905.15651-3-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sc8280xp-x13s: Fix the drive-strength of mclk pinPengyu Luo
The value can be retrieve via windbg on Windows. lkd> !dd f111000 L8 ctl_reg => 0x284 in drivers/pinctrl/qcom/pinctrl-msm.c function msm_gpio_dbg_show_one() ... drive = (ctl_reg >> g->drv_bit) & 7; // (0x284 >> 6) & 7 == 2 ... seq_printf(s, " %dmA", msm_regval_to_drive(drive)); // (drive + 1) * 2 == 6; ... So the value is 6, not 16, it matches Windows now. Fixes: 21927e94caa5 ("arm64: dts: qcom: sc8280xp-x13s: Enable RGB sensor") Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260629065905.15651-2-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: talos: Add memory-region for audio PDEkansh Gupta
Reserve memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260629-talos-remoteheap-v3-1-4e23366c9196@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: glymur: Add label properties to CoreSight devicesJie Gan
Add label properties to TPDM and CTI nodes in the glymur device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260624-add-label-node-for-glymur-v2-1-e8420fd7025f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: msm8996-xiaomi-gemini: Fix up ti,drv2604 enable GPIOKonrad Dybcio
Update the 'enable-gpio' property name to 'enable-gpios' to conform to the bindings for the TI DRV2604 haptics module. While at it, use the GPIO_ACTIVE_HIGH define instead of the raw literal. Fixes: 4ac46b3682c5 ("arm64: dts: qcom: msm8996: xiaomi-gemini: Add support for Xiaomi Mi 5") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260625-topic-ti_drv2604_dtwarn-v1-1-76e91fcafbe8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: lemans-evk: Describe the PCIe M.2 Key E connectorWei Deng
The lemans EVK has the PCIe M.2 Mechanical Key E connector to connect wireless connectivity cards over PCIe and UART interfaces. Hence, describe the connector node and link it with the PCIe 0 Root Port and UART17 nodes through graph port/endpoint. The M.2 Key E connector is powered by a 3.3V fixed regulator (vreg_wcn_3p3) which is sourced from the board's 12V DC input rail (vreg_dcin_12v). Both regulators are always-on and are required by the pcie-m2-e-connector binding. Also add the serial1 = &uart17 alias, which is required for the Bluetooth serdev device to be enumerated on the UART17 interface. Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260622-v3-lemans-split-v3-2-d26bb22594e3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: lemans: Add compatible to the PCIe Root PortWei Deng
Add 'compatible = "pciclass,0604"' to the pcieport0 node in lemans.dtsi to allow the PCI subsystem to associate the DT node with the PCI-to-PCI bridge device. This is required for downstream DT nodes (such as M.2 connectors described as graph endpoints of the Root Port) to be matched to PCI devices. Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260622-v3-lemans-split-v3-1-d26bb22594e3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15x86/mm/pat: Take cpa_lock around large-page collapseDenis V. Lunev
Loading and unloading modules concurrently on several CPUs on a KASAN build, with a short delay injected at the CPA page-table lookup to widen the window, faults within minutes: BUG: KASAN: use-after-free in __change_page_attr+0x7cc/0x7e0 Write of size 8 at addr ffff888181139718 by task modprobe ... The buggy address belongs to the physical page: pfn:0x181139 ... page_type: f2(table) cpa_collapse_large_pages() rebuilds a leaf PMD from its 4K PTEs and frees the old PTE-table pages, while __change_page_attr() fetches a PTE pointer from a lockless lookup_address_in_pgd_attr() and writes it with set_pte_atomic() only later. When module text is served from a shared large ROX mapping the two run on the same PMD: CPU A (module load) CPU B (module finalize) ------------------- ----------------------- execmem_make_temp_rw set_memory_nx __change_page_attr split 2M -> 4K table P kpte = &P[i] (lockless) execmem_restore_rox set_memory_rox (CPA_COLLAPSE) cpa_collapse_large_pages rebuild leaf PMD flush_tlb_all pagetable_free(P) set_pte_atomic(kpte, ...) -> writes into freed P P is a page-table page (page_type: table), reused at once, so the write corrupts whatever got the page next: a bad-pte or bad-page splat, or a fatal fault once P has been turned into read-only text. The flush_tlb_all() before the free does not close this: its IPI only serializes against page-table walkers that run with interrupts off (e.g. GUP-fast); the walk in __change_page_attr() runs with interrupts on, so nothing stops it from holding a stale pointer into P. Serialize the collapse - the PMD rebuild, TLB flush and PTE-table free - under cpa_lock, the same lock __change_page_attr() now takes unconditionally since commit ("x86/mm/pat: stop gating cpa_lock on debug_pagealloc_enabled()"), so a concurrent walker can no longer hold a pointer into a table the collapse is about to free. Fixes: 41d88484c71c ("x86/mm/pat: restore large ROX pages after fragmentation") Signed-off-by: Denis V. Lunev <den@openvz.org> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Kiryl Shutsemau (Meta) <kas@kernel.org> Link: https://patch.msgid.link/20260715183453.2381141-1-den@openvz.org
2026-07-15drm/bridge: tc358767: clamp the reported AUX read size to the requestMaoyi Xie
tc_aux_transfer() clamps an AUX read to the payload limit: size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size); After the transfer it replaces size with the byte count the controller reports in AUX_BYTES: if (size) size = FIELD_GET(AUX_BYTES, auxstatus); AUX_BYTES is GENMASK(15, 8), so it can be up to 255. Nothing clamps it back to the request. tc_aux_read_data() reads that many bytes into the 16-byte auxrdata stack buffer, then copies them into the caller buffer. A reported count of 255 makes the read run to 256 bytes and overruns both. The controller should never report more than it was asked to transfer, so this is defense in depth rather than a live hole. The reported count is only lightly trusted, and the check is cheap. Clamp it back to the request, the same way ti-sn65dsi86 does in commit aca58eac52b8 ("drm/bridge: ti-sn65dsi86: Never store more than msg->size bytes in AUX xfer"). Fixes: 12dfe7c4d9c5 ("drm/bridge: tc358767: Use reported AUX transfer size") Co-developed-by: Kaixuan Li <kaixuan.li@ntu.edu.sg> Signed-off-by: Kaixuan Li <kaixuan.li@ntu.edu.sg> Signed-off-by: Maoyi Xie <maoyixie.tju@gmail.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patch.msgid.link/20260701064440.1541418-1-maoyixie.tju@gmail.com
2026-07-15perf vendor events intel: Update emeraldrapids metricsChun-Tse Shao
The updated events were published in: https://github.com/intel/perfmon/commit/240735b7d8e0b50fe8f4a64e08399df13cb87ae6 Signed-off-by: Chun-Tse Shao <ctshao@google.com> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
2026-07-15perf vendor events intel: Update sierraforest events from 1.17 to 1.18Chun-Tse Shao
The updated events were published in: https://github.com/intel/perfmon/commit/d1bc6c1e8b32e7a75c70cc939295c11ba9aabc96 Signed-off-by: Chun-Tse Shao <ctshao@google.com> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
2026-07-15perf vendor events intel: Update pantherlake events from 1.06 to 1.07Chun-Tse Shao
The updated events were published in: https://github.com/intel/perfmon/commit/ce70546e9ccca4181d142057171c5bd820c8756d Signed-off-by: Chun-Tse Shao <ctshao@google.com> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
2026-07-15perf vendor events intel: Add novalake v1.00 eventsChun-Tse Shao
The updated events were published in: https://github.com/intel/perfmon/commit/3aa49b06346e3a3ff40c7beabe63585591200c58 Signed-off-by: Chun-Tse Shao <ctshao@google.com> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
2026-07-15perf vendor events intel: Update meteorlake events from 1.21 to 1.22Chun-Tse Shao
The updated events were published in: https://github.com/intel/perfmon/commit/704ef43e4c0738065a0575622cf7d31867b8d48b Signed-off-by: Chun-Tse Shao <ctshao@google.com> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-31 04:51:18 +0000