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2026-02-24spi: dt-bindings: snps,dw-abp-ssi: Remove unused bindingsAndy Shevchenko
As stated in the da0a672268b3 ("spi: dw: Remove not-going-to-be-supported code for Baikal SoC") the Baikal platforms are not supported and the respective driver code was removed. Remove the currently unused bindings. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260224115218.3499222-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-02-24nfsd: report the requested maximum number of threads instead of number runningJeff Layton
The current netlink and /proc interfaces deviate from their traditional values when dynamic threading is enabled, and there is currently no way to know what the current setting is. This patch brings the reporting back in line with traditional behavior. Make these interfaces report the requested maximum number of threads instead of the number currently running. Also, update documentation and comments to reflect that this value represents a maximum and not the number currently running. Fixes: d8316b837c2c ("nfsd: add controls to set the minimum number of threads per pool") Signed-off-by: Jeff Layton <jlayton@kernel.org> Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
2026-02-24Revert "hwmon: add SMARC-sAM67 support"Michael Walle
This reverts commit 443b39c82c322c9f3c38bea0389fe927ba00b3b4. I was just informed that this product is discontinued (without being ever released to the market). Pull the plug and let's not waste any more maintainers time. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20260223100459.844967-4-mwalle@kernel.org Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2026-02-24ata: ahci-dwc: Remove not-going-to-be-supported code for Baikal SoCAndy Shevchenko
As noticed in the discussion [1] the Baikal SoC and platforms are not going to be finalized, hence remove stale code. Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2026-02-24dt-bindings: arm: axis: Add ARTPEC-9 alfred boardRavi Patel
Document the Axis ARTPEC-9 SoC binding and the alfred board which uses ARTPEC-9 SoC. Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251119131302.79088-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-02-24dt-bindings: clock: Add ARTPEC-9 clock controllerGyoungBo Min
Add dt-schema for Axis ARTPEC-9 SoC clock controller. The Clock Management Unit (CMU) has a top-level block CMU_CMU which generates clocks for other blocks. Add device-tree binding definitions for following CMU blocks: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS0 - CMU_FSYS1 - CMU_IMEM - CMU_PERI Signed-off-by: GyoungBo Min <mingyoungbo@coasia.com> Reviewed-by: Kyunghwan Kim <kenkim@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251029130731.51305-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-02-24dt-bindings: mmc: rockchip-dw-mshc: Add RV1103B compatibleFabio Estevam
The RV1103B uses the DesignWare MSHC controller compatible with the existing Rockchip RK3288 variant. Add the rockchip,rv1103b-dw-mshc compatible string. Signed-off-by: Fabio Estevam <festevam@nabladev.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-24dt-bindings: mmc: arasan,sdhci: Add Axiado AX3000 SoCSriNavmani A
Add compatible strings for Axiado AX3000 SoC eMMC controller which is based on Arasan eMMC controller. Signed-off-by: SriNavmani A <srinavmani@axiado.com> Signed-off-by: Tzu-Hao Wei <twei@axiado.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-24dt-bindings: pinctrl: imx35: add compatible string fsl,imx25-iomuxcFrank Li
Add compatible string fsl,imx25-iomuxc. Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-02-24dt-bindings: pinctrl: convert fsl,imx27-pinctrl.txt to YAMLFrank Li
Convert fsl,imx27-pinctrl.txt to YAML format. Additional changes: - Add the compatible string "fsl,imx1-iomuxc". - Add gpio@... child nodes. - Add ranges property. - Remove the redundant intermediate node between pinmux and group nodes. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-02-24dt-bindings: pinctrl: document the Eliza Top Level Mode MultiplexerAbel Vesa
Document the Top Level Mode Multiplexer on the Eliza Platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-02-23doc: early_userspace_support.rst: trivial fix: directory -> fileAskar Safin
Trivial fix. Signed-off-by: Askar Safin <safinaskar@gmail.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20260220165238.4162735-1-safinaskar@gmail.com>
2026-02-23docs/zh_TW: remove trailing spaceHaowen Hu
Remove one trailing space character. Signed-off-by: Haowen Hu <srcres258@furdevs.cn> Message-ID: <20260220160201.41149-2-srcres258@furdevs.cn> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2026-02-23documentation: update arch featuresMiquel Sabaté Solà
PA-RISC has perf-event support since commit 610cb23bcc75 ("parisc: Add initial kernel-side perf_event support"); and s390 has stackprotector support since commit f5730d44e05e ("s390: Add stackprotector support"). Signed-off-by: Miquel Sabaté Solà <mssola@mssola.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20260219234040.3260616-1-mssola@mssola.com>
2026-02-23docs: admin-guide: update tiny script for number of taint flagsRandy Dunlap
Account for 2 new taint flags being added by increasing the number of bits handled by the tiny show-tainted-flags example script. Fixes: 8eea4e744758 ("taint: Add TAINT_FWCTL") Fixes: 2852ca7fba9f ("panic: Taint kernel if tests are run") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: David Gow <davidgow@google.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20260216063729.2832770-1-rdunlap@infradead.org>
2026-02-23linux-next: update maintainer info.Randy Dunlap
Update the MAINTAINERS file and Documentation/process/2.Process.rst with the current linux-next maintainer information. Translations of 2.Process.rst should also be updated. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20260216060739.2791462-1-rdunlap@infradead.org>
2026-02-23Documentation/rtla: Add hwnoise to main pageCosta Shulyupin
Add hwnoise to the command list and SEE ALSO section. The command list is ordered from low level to high level. Signed-off-by: Costa Shulyupin <costa.shul@redhat.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20260215131249.33437-1-costa.shul@redhat.com>
2026-02-23docs: Fix an erroneous reference to sphinx.rstJonathan Corbet
Just give the name of the file and let the automarkup stuff do its thing. Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2026-02-23docs: pt_BR: Add initial Portuguese translationDaniel Pereira
Introduce the initial Portuguese (Brazilian) translation for the Linux kernel documentation (HOWTO document). It establishes the directory structure for the pt_BR locale and adds the official entry for the pt_BR maintainer in the MAINTAINERS file. Additionally, this version adds pt_BR support to the documentation build script (Documentation/sphinx/translations.py) to ensure proper rendering and fixes the documentation hierarchy to avoid orphan file warnings. Signed-off-by: Daniel Pereira <danielmaraboo@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> [jc: fix duplicate process_howto label] Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20260204113210.185221-1-danielmaraboo@gmail.com>
2026-02-23Merge branch 'ib-iio-thermal-qcom-pmic5' into togregJonathan Cameron
Immutable branch to allow this base work to be merged into thermal.
2026-02-23dt-bindings: iio: amplifiers: Add AD8366 supportRodrigo Alencar
Add device tree binding documentation for amplifiers and digital attenuators. This covers different device variants with similar SPI control. Each device has its own gain range and step, hence no fallback compatibles are used. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2026-02-23dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADCJishnu Prakash
For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs going through PBS(Programmable Boot Sequence) firmware through a single register interface. This interface is implemented on SDAM (Shared Direct Access Memory) peripherals on the master PMIC PMK8550 rather than a dedicated ADC peripheral. Add documentation for PMIC5 Gen3 ADC and update SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode. Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2026-02-23dt-bindings: iio: adc: Split out QCOM VADC channel propertiesJishnu Prakash
Split out the common channel properties for QCOM VADC devices into a separate file so that it can be included as a reference for devices using them. This will be needed for the upcoming ADC5 Gen3 binding support patch, as ADC5 Gen3 also uses all of these common properties. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2026-02-23sched_ext: Fix ops.dequeue() semanticsAndrea Righi
Currently, ops.dequeue() is only invoked when the sched_ext core knows that a task resides in BPF-managed data structures, which causes it to miss scheduling property change events. In addition, ops.dequeue() callbacks are completely skipped when tasks are dispatched to non-local DSQs from ops.select_cpu(). As a result, BPF schedulers cannot reliably track task state. Fix this by guaranteeing that each task entering the BPF scheduler's custody triggers exactly one ops.dequeue() call when it leaves that custody, whether the exit is due to a dispatch (regular or via a core scheduling pick) or to a scheduling property change (e.g. sched_setaffinity(), sched_setscheduler(), set_user_nice(), NUMA balancing, etc.). BPF scheduler custody concept: a task is considered to be in the BPF scheduler's custody when the scheduler is responsible for managing its lifecycle. This includes tasks dispatched to user-created DSQs or stored in the BPF scheduler's internal data structures from ops.enqueue(). Custody ends when the task is dispatched to a terminal DSQ (such as the local DSQ or %SCX_DSQ_GLOBAL), selected by core scheduling, or removed due to a property change. Tasks directly dispatched to terminal DSQs bypass the BPF scheduler entirely and are never in its custody. Terminal DSQs include: - Local DSQs (%SCX_DSQ_LOCAL or %SCX_DSQ_LOCAL_ON): per-CPU queues where tasks go directly to execution. - Global DSQ (%SCX_DSQ_GLOBAL): the built-in fallback queue where the BPF scheduler is considered "done" with the task. As a result, ops.dequeue() is not invoked for tasks directly dispatched to terminal DSQs. To identify dequeues triggered by scheduling property changes, introduce the new ops.dequeue() flag %SCX_DEQ_SCHED_CHANGE: when this flag is set, the dequeue was caused by a scheduling property change. New ops.dequeue() semantics: - ops.dequeue() is invoked exactly once when the task leaves the BPF scheduler's custody, in one of the following cases: a) regular dispatch: a task dispatched to a user DSQ or stored in internal BPF data structures is moved to a terminal DSQ (ops.dequeue() called without any special flags set), b) core scheduling dispatch: core-sched picks task before dispatch (ops.dequeue() called with %SCX_DEQ_CORE_SCHED_EXEC flag set), c) property change: task properties modified before dispatch, (ops.dequeue() called with %SCX_DEQ_SCHED_CHANGE flag set). This allows BPF schedulers to: - reliably track task ownership and lifecycle, - maintain accurate accounting of managed tasks, - update internal state when tasks change properties. Cc: Tejun Heo <tj@kernel.org> Cc: Emil Tsalapatis <emil@etsalapatis.com> Cc: Kuba Piecuch <jpiecuch@google.com> Signed-off-by: Andrea Righi <arighi@nvidia.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2026-02-23dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8940Barnabás Czémán
Add the compatible for MSS as found on the MSM8940 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20260107-mss-v4-8-9f4780345b6f@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8937Barnabás Czémán
Add the compatible for MSS as found on the MSM8937 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20260107-mss-v4-6-9f4780345b6f@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8917Barnabás Czémán
Add the compatible for MSS as found on the MSM8917 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20260107-mss-v4-4-9f4780345b6f@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MDM9607Barnabás Czémán
Add the compatible for MSS as found on the MDM9607 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20260107-mss-v4-2-9f4780345b6f@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: fsl: add compatible string fsl,imx25-aipsFrank Li
Add compatible string fsl,imx25-aips to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb: /soc/bus@43f00000/bridge@43f00000: failed to match any schema with compatible: ['fsl,imx25-aips'] Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://patch.msgid.link/20260211221529.3745404-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-02-23dt-bindings: clock: qcom: Add video clock controller on Glymur SoCTaniya Das
Add compatible string for Glymur video clock controller and the bindings for Glymur Qualcomm SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-2-8f7d8b4d8edd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: clock: qcom: document the Glymur GPU Clock ControllerTaniya Das
Glymur SoC has Qualcomm GX(graphics) clock controller and also the Graphics clock controller. The GX graphics clock controller helps in the recovery of the Graphics subsystem. Add bindings documentation for the Glymur Graphics Clock and Graphics power domain Controller for Glymur SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260127-glymur_gpucc-v1-1-547334c81ba2@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: soc: qcom: qcom,pmic-glink: Add Glymur and Kaanapali compatiblesAnjelique Melendez
Glymur (a recent compute platform) and Kaanapali (a recent mobile platform) have the charger FW running on a new subsystem SOCCP (SOC Control Processor) instead of on ADSP like in previous platforms. Because of this, pmic_glink interface on Glymur and Kaanapali platforms are not compatible with previous platforms. Hence, add new compatible strings for Glymur and Kaanapali. Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260209204915.1983997-2-anjelique.melendez@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: clock: qcom,glymur-dispcc: De-acronymize SoC nameKrzysztof Kozlowski
Glymur is a codename of Qualcomm SoC, not an acronym. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260217130047.281813-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: arm: qcom: Document Glymur SoC and boardPankaj Patil
Document Glymur SoC bindings and Compute Reference Device (CRD) board id Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260219-upstream_v3_glymur_introduction-v8-1-8ce4e489ebb6@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23platform/x86: uniwill-laptop: Rename FN lock and super key lock attrsArmin Wolf
It turns out that both sysfs attributes actually directly control the FN lock status/super key enable status, rather than the triggering of the associated events. This behavior was first observed on a Tuxedo notebook and was belived to be a hardware quirk. However, it seems that i simply misunderstood the manual of the OEM software for Intel NUC devices. The correct behavior is: - fn_lock_toggle_enable enables/disables FN lock mode - super_key_toggle_enable enables/disables the super key Rename both sysfs attributes to avoid confusing users. Fixes: d050479693bb ("platform/x86: Add Uniwill laptop driver") Signed-off-by: Armin Wolf <W_Armin@gmx.de> Link: https://patch.msgid.link/20260218005101.73680-2-W_Armin@gmx.de Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
2026-02-23PCI/MSI: Clarify pci_free_irq_vectors() usage for managed devicesShawn Lin
Update pci_free_irq_vectors() documentation to clarify that drivers using pcim_enable_device() must not call pci_free_irq_vectors(). For legacy reasons, pcim_enable_device() switches several normally un-managed functions into managed mode. Currently, the only function affected in this way is pcim_setup_msi_release(), which results in automatic IRQ vector management. This behavior is dangerous and confusing. Drivers using pcim_enable_device() should rely on the automatic IRQ vector management and avoid calling pci_free_irq_vectors() manually. Suggested-by: Philipp Stanner <phasta@kernel.org> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: squash both updates to pci_free_irq_vectors() documentation] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/1770798299-202288-2-git-send-email-shawn.lin@rock-chips.com Link: https://patch.msgid.link/1770798299-202288-3-git-send-email-shawn.lin@rock-chips.com
2026-02-23spi: dt-bindings: renesas,rzv2h-rspi: allow multiple DMAsCosmin Tanislav
All supported SoCs have multiple DMA controllers that can be used with the RSPI peripheral. The current bindings only allow a single pair of RX and TX DMAs. The DMA core allows specifying multiple DMAs with the same name, and it will pick the first available one. There is an exception in the base dt-schema rules specifically for allowing this behavior (dtschema/schemas/dma/dma.yaml). dma-names: anyOf: - uniqueItems: true - items: # Hack around Renesas bindings which repeat entries to support # multiple possible DMA providers enum: [rx, tx] Allow multiple DMAs to have the same name and only restrict the possible names of the DMA channels, not their count. For RZ/T2H and RZ/N2H SoCs, limit the number of DMA channels to 6, as they have 3 DMA controllers. For RZ/V2H and RZ/V2N SoCs, limit the number of DMA channels to 10, as they have 5 DMA controllers. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-02-23dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controllerAlbert Yang
Add device tree bindings for the Black Sesame Technologies DWCMSHC SDHCI controller used in C1200 SoC. The binding describes a Synopsys DesignWare Cores Mobile Storage Host Controller with BST-specific extensions including: - Two register regions (core SDHCI and CRM registers) - Optional memory-region for bounce buffer support - Fixed clock input Signed-off-by: Ge Gordon <gordon.ge@bst.ai> Signed-off-by: Albert Yang <yangzh0906@thundersoft.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: spacemit,sdhci: add support for K3 SoCYixun Lan
The SDHCI controller found on SpacemiT K3 SoC share the same IP with K1 generation, while fixed the broken 64BIT DMA issue. Introduce a compatible string to enable support for it. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Yixun Lan <dlan@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: arm,pl18x: Do not use plural form of a proper noun PrimeCellVladimir Zapolskiy
As a proper noun PrimeCell is a single entity and it can not have a plural form, fix the typo. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: spacemit,sdhci: add reset supportYixun Lan
The SpacemiT SDHCI controller has two reset lines, one connect to AXI bus which shared by all controllers, while another one connect to individual controller separately. Signed-off-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: arasan,sdhci: Allow "dma-coherent" propertyRob Herring (Arm)
The Arasan SDHCI controller is DMA coherent on the APM merlin SoC, so allow the dma-coherent property. No reason implementations can't also be coherent and there's not an SoC specific compatible, so allow it on any platform. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: brcm,iproc-sdhci: Allow "dma-coherent" and "iommus" propertiesRob Herring (Arm)
The Broadcom iProc SDHCI controller is DMA coherent and/or behind an IOMMU on some Broadcom SoCs, so allow the dma-coherent and iommus properties. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: cdns,sdhci: Drop required "resets" on AMD Pensando ELBARob Herring (Arm)
The AMD Pensando ELBA DT defines no reset for the SDHCI, so it is obviously not required. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: mtk-sd: Add support for MT8189 SoCLouis-Alexis Eyraud
Add a new compatible for MMC IP in MT8189 SoC. Even though this is partially compatible with the one found in MT8196 SoC, the MT8189 SoC register layout has some slight differences and additional features. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: power: Add MediaTek MT8189 power domainIrving-CH Lin
Add dt schema and IDs for the power domain of MediaTek MT8189 SoC. The MT8189 power domain IP provide power domains control function for subsys (eg. MFG, audio, venc/vdec ...). Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: power: mt8196-gpufreq: Describe nvmem provider abilityNicolas Frattaroli
On the MediaTek MT8196 SoC, the Mali GPU's "shader_present" hardware register may also include a non-functional shader core, along with the present shader cores. An efuse elsewhere in the SoC provides the shader_present mask with the fused off core omitted. However, the efuse address is not publicly disclosed. What is known though is that the GPUEB MCU reads this efuse, and exposes its contents in the memory it shares with the application processor. We can therefore describe the mediatek,mt8196-gpufreq device as being an nvmem provider for this purpose, as it does provide nvmem access in an indirect way. The shader-present child node is left out of the list of required properties as we may one day be able to describe the actual efuse region this value comes from, so the gpufreq device isn't necessarily the only device that can provide this cell, and implementations shouldn't need to implement this functionality once this is the case. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23Merge drm/drm-next into drm-misc-nextMaxime Ripard
Let's merge 7.0-rc1 to start the new drm-misc-next window Signed-off-by: Maxime Ripard <mripard@kernel.org>
2026-02-23dt-bindings: pinctrl: qcom,sm8450-lpass-lpi-pinctrl: Add SA8775P and QCS8300 ↵Mohammad Rafi Shaik
pinctrl Document compatible for Qualcomm SA8775P and QCS8300 SoC LPASS TLMM pin controller, fully compatible with previous SM8450 generation (same amount of pins and functions). Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-02-23dt-bindings: pinctrl: rockchip: Add RV1103B compatibleFabio Estevam
Document the compatible string for the RV1103B SoC. Signed-off-by: Fabio Estevam <festevam@nabladev.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-22 08:10:37 +0000