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2026-05-27KVM: TDX: Wrap mapping of leaf and non-leaf S-EPT entries into helpersSean Christopherson
Add a helper, tdx_sept_map_leaf_spte(), to wrap and isolate PAGE.ADD and PAGE.AUG operations. Rename tdx_sept_link_private_spt() to tdx_sept_map_nonleaf_spte() to wrap SEPT.ADD for symmetry. Thus, transition tdx_sept_set_private_spte() into a "dispatch" routine for setting/writing S-EPT entries. No functional change intended. Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com> Signed-off-by: Yan Zhao <yan.y.zhao@intel.com> Link: https://patch.msgid.link/20260509075500.4157-1-yan.y.zhao@intel.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-05-27KVM: TDX: Drop kvm_x86_ops.link_external_spt()Sean Christopherson
Drop the dedicated .link_external_spt() for linking S-EPT pages, and instead funnel everything through .set_external_spte() for mapping S-EPT entries. Using separate hooks doesn't help prevent TDP MMU details from bleeding into TDX, and vice versa; to the contrary, dedicated callbacks will result in _more_ pollution when hugepage support is added, e.g. will require the TDP MMU to know details about the splitting rules for TDX that aren't all that relevant to the TDP MMU. Ideally, KVM would provide a single pair of hooks to set S-EPT entries, one hook for setting SPTEs under write-lock and another for setting SPTEs under read-lock (e.g. to ensure the entire operation is "atomic", to allow for failure, etc.). Sadly, TDX's requirement that all child S-EPT entries are removed before the parent makes that impractical: the TDP MMU deliberately prunes non-leaf SPTEs and _then_ processes its children, thus making it quite important for the TDP MMU to differentiate between zapping leaf and non-leaf S-EPT entries. However, that's the _only_ case that's truly special, and even that case could be shoehorned into a single hook; it just wouldn't be a net positive. Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com> Signed-off-by: Yan Zhao <yan.y.zhao@intel.com> Link: https://patch.msgid.link/20260509075357.4113-1-yan.y.zhao@intel.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-05-27x86/ftrace: Relocate %rip-relative percpu refs in dynamic trampolinesAlexis Lothoré (eBPF Foundation)
With CONFIG_CALL_DEPTH_TRACKING enabled on an x86 retbleed-affected platform (eg: Skylake), with retbleed=stuff, registering a dynamic ftrace trampoline crashes on the first call into the traced function: BUG: unable to handle page fault for address: ffff88817ae18880 #PF: supervisor write access in kernel mode #PF: error_code(0x0002) - not-present page PGD 4b53067 P4D 4b53067 PUD 0 Oops: Oops: 0002 [#1] SMP PTI CPU: 3 UID: 0 PID: 187 Comm: usleep Not tainted 7.0.10 #243 PREEMPT(full) Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Arch Linux 1.17.0-2-2 04/01/2014 Code: 24 78 00 00 00 00 48 89 ea 48 89 54 24 20 48 8b b4 24 b8 00 00 00 48 8b bc 24 b0 00 00 00 48 89 bc 24 80 00 00 00 48 83 ef 05 <65> 48 c1 3d 1f a8 b6 02 05 48 8b 15 f6 00 00 00 4c 89 3c 24 4c 89 Call Trace: <TASK> ? find_held_lock ? exc_page_fault ? lock_release ? __x64_sys_clock_nanosleep ? lockdep_hardirqs_on_prepare ? trace_hardirqs_on __x64_sys_clock_nanosleep do_syscall_64 ? exc_page_fault ? call_depth_return_thunk entry_SYSCALL_64_after_hwframe ... Kernel panic - not syncing: Fatal exception This small reproducer allows to easily trigger the crash: # echo 'p __x64_sys_clock_nanosleep' > /sys/kernel/tracing/kprobe_events # echo 1 > /sys/kernel/tracing/events/kprobes/p___x64_sys_clock_nanosleep_0/enable # usleep 1 Monitoring the crash under GDB points to the exact instruction in charge of incrementing the call depth: sarq $5, %gs:__x86_call_depth(%rip) This instruction matches the one inserted by the ftrace_regs_caller from ftrace_64.S. This emitted code was likely working fine until the introduction of 59bec00ace28 ("x86/percpu: Introduce %rip-relative addressing to PER_CPU_VAR()"): it has made the call depth accounting addressing relative to $rip, instead of being based on an absolute address. As this code exact location depends on where the trampoline lives in memory, the corresponding displacement needs to be adjusted at runtime to actually correctly find the per-cpu __x86_call_depth value, otherwise the targeted address is wrong, leading to the page fault seen above. Fix the %rip-relative displacement of the copied CALL_DEPTH_ACCOUNT instruction (from ftrace_regs_caller) by calling text_poke_apply_relocation(), as it is done for example by the x86 BPF JIT compiler through x86_call_depth_emit_accounting(). This corrects both CALL_DEPTH_ACCOUNT slots, in ftrace_caller and ftrace_regs_caller. [ bp: Massage. ] Fixes: 59bec00ace28 ("x86/percpu: Introduce %rip-relative addressing to PER_CPU_VAR()") Signed-off-by: Alexis Lothoré (eBPF Foundation) <alexis.lothore@bootlin.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Steven Rostedt <rostedt@goodmis.org> Cc: <stable@kernel.org> Link: https://patch.msgid.link/20260527-fix_call_depth_in_trampoline-v1-1-1c1abc8ae310@bootlin.com
2026-05-27x86/entry/vdso32: Remove conditional omission of '.cfi_offset eflags'Nathan Chancellor
Now that the minimum supported version of LLVM for building the kernel has been raised to 17.0.1, the inclusion condition added by 3e30278e0c71 ("x86/entry/vdso32: Omit '.cfi_offset eflags' for LLVM < 16") will always be true. Revert the change to clean up the source code. Acked-by: H. Peter Anvin (Intel) <hpa@zytor.com> Link: https://patch.msgid.link/20260517-bump-minimum-supported-llvm-version-to-17-v2-13-b3b8cda46bdd@kernel.org Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2026-05-27x86/module: Revert "Deal with GOT based stack cookie load on Clang < 17"Nathan Chancellor
Now that the minimum supported version of LLVM for building the kernel has been raised to 17.0.1, the workaround added by 78c4374ef8b8 ("x86/module: Deal with GOT based stack cookie load on Clang < 17") will never be included, as the final clause in the preprocessor conditional is always false. Revert the change to clean up the dead code. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://patch.msgid.link/20260517-bump-minimum-supported-llvm-version-to-17-v2-12-b3b8cda46bdd@kernel.org Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2026-05-27x86/build: Drop unnecessary '-ffreestanding' addition to KBUILD_CFLAGSNathan Chancellor
Now that the minimum supported version of LLVM for building the kernel has been raised to 17.0.1, the addition of '-ffreestanding' to KBUILD_CFLAGS for 32-bit x86 is unnecessary, as the linked LLVM bug is resolved in all supported LLVM versions. 16cb16e0d285 ("x86/build: Remove -ffreestanding on i386 with GCC") intended to make the addition of '-ffreestanding' clang only but due to a bug in the adjusted check from d70da12453ac ("hardening: Enable i386 FORTIFY_SOURCE on Clang 16+") it has been applied for all versions of GCC and clang < 16.0.0. There are no known problems with removing this for GCC but if one surfaces, it can be restored under a CONFIG_CC_IS_GCC block. Link: https://patch.msgid.link/20260517-bump-minimum-supported-llvm-version-to-17-v2-11-b3b8cda46bdd@kernel.org Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2026-05-27riscv: Drop tautological condition from TOOLCHAIN_NEEDS_OLD_ISA_SPECNathan Chancellor
Now that the minimum supported version of LLVM for building the kernel has been raised to 17.0.1, the Clang dependency part of CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC is always false, so it can be removed. Adjust the help text to remove mention of Clang < 17, as it is irrelevant for the kernel after the minimum supported bump. Acked-by: Paul Walmsley <pjw@kernel.org> # arch/riscv Link: https://patch.msgid.link/20260517-bump-minimum-supported-llvm-version-to-17-v2-9-b3b8cda46bdd@kernel.org Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2026-05-27riscv: Remove tautological condition from selection of ARCH_SUPPORTS_CFINathan Chancellor
Now that the minimum supported version of LLVM for building the kernel has been raised to 17.0.1, the condition of the selection of CONFIG_ARCH_SUPPORTS_CFI is always true, so it can be removed. Acked-by: Paul Walmsley <pjw@kernel.org> # arch/riscv Link: https://patch.msgid.link/20260517-bump-minimum-supported-llvm-version-to-17-v2-8-b3b8cda46bdd@kernel.org Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2026-05-27ARM: Drop tautological ld.lld conditions from ARCH_MULTI_V4{,T}Nathan Chancellor
Now that the minimum supported version of LLVM for building the kernel has been raised to 17.0.1, the '!ld.lld || ld.lld >= 16' dependency of CONFIG_ARCH_MULTI_V4{,T} is always true, so it can be removed from both symbols. Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20260517-bump-minimum-supported-llvm-version-to-17-v2-7-b3b8cda46bdd@kernel.org Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2026-05-27arch/Kconfig: Remove tautological condition from AUTOFDO_CLANGNathan Chancellor
Now that the minimum supported version of LLVM for building the kernel has been raised to 17.0.1, the clang version check in CONFIG_AUTOFDO_CLANG can be removed because it is always true. Reviewed-by: Rong Xu <xur@google.com> Link: https://patch.msgid.link/20260517-bump-minimum-supported-llvm-version-to-17-v2-6-b3b8cda46bdd@kernel.org Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2026-05-27arch/Kconfig: Remove tautological conditions from HAS_LTO_CLANGNathan Chancellor
Now that the minimum supported version of LLVM for building the kernel has been raised to 17.0.1, two dependency lines in CONFIG_HAS_LTO_CLANG are always true because Clang will always be newer than 17.0.0, so they can be removed. Reviewed-by: Nicolas Schier <nsc@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20260517-bump-minimum-supported-llvm-version-to-17-v2-5-b3b8cda46bdd@kernel.org Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2026-05-27x86/mm: Fix freeing of PMD-sized vmemmap pagesDavid Hildenbrand (Arm)
Commit bf9e4e30f353 ("x86/mm: use pagetable_free()"), switched from freeing non-boot page tables through __free_pages() to pagetable_free(). However, the function is also called to free vmemmap pages. Given that vmemmap pages are not page tables, already the page_ptdesc(page) is wrong. But worse, pagetable_free() calls: __free_pages(page, compound_order(page)); Since vmemmap pages are not compound pages (see vmemmap_alloc_block()) -- except for HVO, which doesn't apply here -- only first page of a PMD-sized vmemmap page is freed, leaking the other ones. Fix it by properly decoupling pagetable and vmemmap freeing. free_pagetable() no longer has to mess with SECTION_INFO, as only the vmemmap is marked like that in register_page_bootmem_memmap(). The indentation in remove_pmd_table() is messed up. Fix that while touching it. Bootmem info handling will soon be fixed up. For now, handle it similar to free_pagetable(), just avoiding the ifdef. [ dhansen: changelog munging. More imperative voice ] Fixes: bf9e4e30f353 ("x86/mm: use pagetable_free()") Signed-off-by: David Hildenbrand (Arm) <david@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Mike Rapoport (Microsoft) <rppt@kernel.org> Tested-by: Lance Yang <lance.yang@linux.dev> Link: https://lore.kernel.org/20260429-vmemmap-v2-1-8dfcacffd877@kernel.org Link: https://patch.msgid.link/20260429-vmemmap-v2-1-8dfcacffd877@kernel.org Cc: stable@vger.kernel.org
2026-05-27KVM: x86: Virtualize AMD CPUID faultingJim Mattson
On AMD CPUs, CPUID faulting support is advertised via CPUID.80000021H:EAX.CpuidUserDis[bit 17] and enabled by setting HWCR.CpuidUserDis[bit 35]. Advertise the feature to userspace regardless of host CPU support. Allow writes to HWCR to set bit 35 when the guest CPUID advertises CpuidUserDis. Update cpuid_fault_enabled() to check HWCR.CpuidUserDis as well as MSR_FEATURE_ENABLES.CPUID_GP_ON_CPL_GT_0. Unlike VMX, SVM prioritizes the CPUID intercept over the #GP induced by CPUID faulting.[1] This behavior has been confirmed on a Turin CPU (F/M/S 1AH/2/1). Link: https://lore.kernel.org/r/DS7PR12MB82011943131DF5415365E19E940B2@DS7PR12MB8201.namprd12.prod.outlook.com [1] Signed-off-by: Jim Mattson <jmattson@google.com> Link: https://patch.msgid.link/20260527174347.2356165-5-jmattson@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-05-27KVM: x86: Remove supports_cpuid_fault() helperJim Mattson
The function, supports_cpuid_fault(), tests specifically for guest support of Intel's CPUID faulting feature. It does not test for guest support of AMD's CPUID faulting feature. To avoid confusion, remove the helper. Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Jim Mattson <jmattson@google.com> Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com> Link: https://patch.msgid.link/20260527174347.2356165-4-jmattson@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-05-27KVM: x86: Prioritize CPUID faulting over CPUID VM-exits in nested VMXJim Mattson
Per the Intel SDM, "Certain exceptions have priority over VM exits. These include invalid-opcode exceptions, faults based on privilege level, and general-protection exceptions that are based on checking I/O permission bits in the task-state segment (TSS)." Ensure that when L2 executes CPUID at CPL > 0 while L1 has enabled CPUID faulting, KVM intercepts the exit in L0 and queues #GP rather than forwarding the CPUID VM-exit to L1. Empirical testing confirms that this #GP has higher precedence than a CPUID VM-exit on Granite Rapids (F/M/S 6/0xad/1). Fixes: db2336a80489 ("KVM: x86: virtualize cpuid faulting") Reported-by: Sashiko <sashiko-bot@kernel.org> Closes: https://sashiko.dev/#/patchset/20260513224608.1859737-1-jmattson%40google.com?part=3 Signed-off-by: Jim Mattson <jmattson@google.com> Link: https://patch.msgid.link/20260527174347.2356165-3-jmattson@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-05-27KVM: x86: Consolidate CPUID fault handling for emulator and interception logicSean Christopherson
Extract the logic for emulating CPUID faulting (where CPUID #GPs at CPL>0 outside of SMM) into a dedicated helper and use the helper for both the full emulator and the intercepted-CPUID paths. Opportunistically drop kvm_require_cpl(), as kvm_emulate_cpuid() was the one and only user. No functional change intended. [jim: Add EXPORT_STATIC_CALL_GPL(kvm_x86_get_cpl) so that KVM vendor modules can call kvm_is_cpuid_allowed(). Fix typo in commit message.] Signed-off-by: Jim Mattson <jmattson@google.com> Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com> Link: https://patch.msgid.link/20260527174347.2356165-2-jmattson@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-05-27KVM: arm64: Don't populate TPIDR_EL2 in finalise_el2()Will Deacon
Currently, it is not necessary for __finalise_el2() to configure TPIDR_EL2: * The hyp stub code does not consume the value of TPIDR_EL2. * On the boot cpu, TPIDR_EL1 is used for the percpu offset until the ARM64_HAS_VIRT_HOST_EXTN cpucap is detected and boot alternatives are patched. Before boot alternatives are patched, cpu_copy_el2regs() will copy TPIDR_EL1 into TPIDR_EL2. It is not necessary for __finalise_el2() to initialise TPIDR_EL2 before this. * Secondary CPUs are brought up after boot alternatives have been patched, and __secondary_switched() will initialize TPIDR_EL2 in 'init_cpu_task', after finalise_el2() calls __finalise_el2() * KVM hyp code which may consume TPIDR_EL2 is brought up after all secondaries have been booted, once TPIDR_El2 has been configured on all CPUs. Remove the redundant initialisation from __finalise_el2(). Cc: Oliver Upton <oupton@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will@kernel.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://patch.msgid.link/20260518153127.6078-1-will@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-27arm64: dts: rockchip: add rga3 dt nodes to rk3588Sven Püschel
Add devicetree nodes for the RGA3 (Raster Graphics Acceleration 3) peripheral in the RK3588. The existing rga node refers to the RGA2-Enhanced peripheral. The RK3588 contains one RGA2-Enhanced core and two RGA3 cores. Both feature a similar functionality of scaling, cropping and rotating of up to two input images into one output image. Key differences of the RGA3 are: - supports 10bit YUV output formats - supports 8x8 tiles and FBCD as inputs and outputs - supports BT2020 color space conversion - max output resolution of (8192-64)x(8192-64) - MMU can map up to 32G DDR RAM - fully planar formats (3 planes) are not supported - max scale up/down factor of 8 (RGA2 allows up to 16) Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de> Link: https://patch.msgid.link/20260521-spu-rga3-v7-28-3f33e8c7145f@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-05-27KVM: arm64: Pre-check vcpu memcache for host->guest donateFuad Tabba
__pkvm_host_donate_guest() flips the host stage-2 PTE for the donated page to a non-valid annotation via host_stage2_set_owner_metadata_locked() and then calls kvm_pgtable_stage2_map() to install the matching guest stage-2 mapping. The map's return value is wrapped in WARN_ON() and otherwise discarded, asserting that the call cannot fail. WARN_ON() at nVHE EL2 panics, so this assertion is only correct if the call genuinely cannot fail. kvm_pgtable_stage2_map() can fail with -ENOMEM even at PAGE_SIZE granularity: the donate path verifies PKVM_NOPAGE for the guest IPA before the map, so the walker must allocate fresh page-table pages from the vcpu memcache, and the host controls the vcpu memcache via the topup interface. An under-provisioned donation request would otherwise turn a recoverable -ENOMEM into a fatal hyp panic. Bound the worst-case walker allocation alongside the existing __host_check_page_state_range() / __guest_check_page_state_range() pre-checks, using the helper introduced for host->guest share. If the vcpu memcache holds fewer pages than kvm_mmu_cache_min_pages(), return -ENOMEM before any state mutation. Fixes: 1e579adca177 ("KVM: arm64: Introduce __pkvm_host_donate_guest()") Assisted-by: Gemini:gemini-3.1-pro review-prompts Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://patch.msgid.link/20260501112149.2824881-7-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-27KVM: arm64: Pre-check vcpu memcache for host->guest shareFuad Tabba
__pkvm_host_share_guest() ends with kvm_pgtable_stage2_map() to install the guest stage-2 mapping, after a forward pass that mutates the host vmemmap (sets PKVM_PAGE_SHARED_OWNED and increments host_share_guest_count) for every page in the range. The map's return value is wrapped in WARN_ON() and otherwise discarded, asserting that the call cannot fail. WARN_ON() at nVHE EL2 panics, so this assertion is only correct if the call genuinely cannot fail. kvm_pgtable_stage2_map() can fail with -ENOMEM when the stage-2 walker exhausts the caller's memcache, and the host controls the vcpu memcache via the topup interface, so an under-provisioned share request would otherwise turn a recoverable -ENOMEM into a fatal hyp panic. Bound the worst-case walker allocation in the existing pre-check pass so that kvm_pgtable_stage2_map() cannot fail at the call site, using kvm_mmu_cache_min_pages() -- the same bound host EL1 uses for its own stage-2 maps. If the vcpu memcache holds fewer pages, return -ENOMEM before any state mutation. Fixes: d0bd3e6570ae ("KVM: arm64: Introduce __pkvm_host_share_guest()") Assisted-by: Gemini:gemini-3.1-pro review-prompts Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://patch.msgid.link/20260501112149.2824881-6-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-27KVM: arm64: Seed pkvm_ownership_selftest vcpu memcacheFuad Tabba
The hypercall handlers call pkvm_refill_memcache() to top up the hyp_vcpu memcache before invoking __pkvm_host_{share,donate}_guest(). pkvm_ownership_selftest invokes those functions directly with a static selftest_vcpu that has an empty memcache. Seed selftest_vcpu's memcache from the prepopulated selftest pages, leaving the remainder for selftest_vm.pool. Required by the memcache-sufficiency pre-check added in the following patches. Assisted-by: Gemini:gemini-3.1-pro review-prompts Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://patch.msgid.link/20260501112149.2824881-5-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-27KVM: arm64: Fix __deactivate_fgt macro parameter typoFuad Tabba
__deactivate_fgt() declares its first parameter as "htcxt" but the body references "hctxt". The parameter is unused; the macro silently captures "hctxt" from the enclosing scope. Both existing callers (__deactivate_traps_hfgxtr() and __deactivate_traps_ich_hfgxtr()) happen to define a local "struct kvm_cpu_context *hctxt", so the macro works by coincidence. A future caller without an "hctxt" local in scope, or naming it differently, would compile but bind to the wrong context. Align the parameter name with the sibling __activate_fgt() macro. The "vcpu" parameter remains unused in the body, kept for API symmetry with __activate_fgt() (which uses it). Fixes: f5a5a406b4b8 ("KVM: arm64: Propagate and handle Fine-Grained UNDEF bits") Assisted-by: Gemini:gemini-3.1-pro review-prompts Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://patch.msgid.link/20260501112149.2824881-4-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-27KVM: arm64: Guard against NULL vcpu on VHE hyp panic pathFuad Tabba
On VHE, __hyp_call_panic() unconditionally calls __deactivate_traps(vcpu) on the vcpu pointer read from host_ctxt->__hyp_running_vcpu. That pointer is cleared after every guest exit (and is never set when no guest is running), so an unexpected EL2 exception landing in _guest_exit_panic, e.g. via the el2t*_invalid / el2h_irq_invalid vectors - reaches this function with vcpu == NULL. __deactivate_traps() then dereferences vcpu via ___deactivate_traps() -> vserror_state_is_nested() -> vcpu_has_nv() -> vcpu->arch.features, faulting inside the panic handler and obscuring the original failure. The nVHE counterpart (hyp_panic() in arch/arm64/kvm/hyp/nvhe/switch.c) already guards its vcpu-using cleanup with "if (vcpu)"; mirror that here. sysreg_restore_host_state_vhe() does not depend on vcpu and continues to run unconditionally, preserving panic forensics. The trailing panic("...VCPU:%p", vcpu) prints "(null)" safely via printk's %p handling. Fixes: 6a0259ed29bb ("KVM: arm64: Remove hyp_panic arguments") Assisted-by: Gemini:gemini-3.1-pro review-prompts Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://patch.msgid.link/20260501112149.2824881-3-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-27KVM: arm64: Fix memory leak in hyp_trace_unload()Vincent Donnefort
During trace remote loading, hyp_trace_load() allocates the descriptor pages but fails to store the allocated size in trace_buffer->desc_size. As a result, when unloading the trace buffer, hyp_trace_unload() calls free_pages_exact() with a size of 0 which fails to free the memory. Fix this by updating the descriptor size in trace_buffer->desc_size. Fixes: 3aed038aac8d ("KVM: arm64: Add trace remote for the nVHE/pKVM hyp") Reported-by: Sashiko <sashiko-bot@kernel.org> Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260521124613.911067-4-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-27KVM: arm64: Fix rollback in hyp_trace_buffer_share_hyp()Vincent Donnefort
When sharing the trace buffer with the hypervisor, if sharing a page fails, the rollback path in hyp_trace_buffer_share_hyp() misses unsharing the metadata page (meta_va) which was successfully shared before entering the page sharing loop. Additionally, if a failure occurs, the cleanup calls hyp_trace_buffer_unshare_hyp() with an incorrect CPU index. Since that CPU's pages were already rolled back locally in the loop, this leads to duplicate unsharing attempts. Fix both issues affecting the rollback. Fixes: 3aed038aac8d ("KVM: arm64: Add trace remote for the nVHE/pKVM hyp") Reported-by: Sashiko <sashiko-bot@kernel.org> Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260521124613.911067-3-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-27KVM: arm64: Fix meta-page unsharing in pKVM hyp tracingVincent Donnefort
As the hyp_trace_buffer_unshare_hyp() function name suggests we should unshare all the previously shared pages, otherwise we leak hyp-shared pages which won't be reusable for hyp memory. Fix the typo by calling __unshare_page() on the meta-page, ensuring all previously shared pages are correctly unshared. Fixes: 3aed038aac8d ("KVM: arm64: Add trace remote for the nVHE/pKVM hyp") Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260521124613.911067-2-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-27KVM: arm64: PMU: Preserve AArch32 counter low bitsQiang Ma
AArch32 writes to PMU event counters cannot update the top 32 bits, even when PMUv3p5 makes the counters 64-bit. KVM therefore needs to preserve the existing high half and only update the low half written by the guest, unless the caller explicitly forces a full reset through PMCR.P. The current code masks @val down to the old high half before taking lower_32_bits(val), which means the low half is always zero. As a result, AArch32 writes to event counters discard the guest-provided low 32 bits instead of storing them. Build the new value from the old high 32 bits and the low 32 bits of the value supplied by the guest. Fixes: 26d2d0594d70 ("KVM: arm64: PMU: Do not let AArch32 change the counters' top 32 bits") Signed-off-by: Qiang Ma <maqianga@uniontech.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://patch.msgid.link/20260526074640.791991-1-maqianga@uniontech.com Cc: stable@vger.kernel.org
2026-05-27ARM: omap1: enable real software node lookup of GPIOs on Nokia 770Bartosz Golaszewski
Currently the board file for Nokia 770 creates dummy software nodes not attached in any way to the actual GPIO controller devices and uses the fact that GPIOLIB matching swnode's name to the GPIO chip's label during software node lookup. This behavior is wrong and we want to remove it. To that end, we need to first convert all existing users to creating actual fwnode links. Create real software nodes for GPIO controllers on OMAP16xx and reference them from the software nodes in the nokia board file. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi> Link: https://patch.msgid.link/20260430-nokia770-gpio-swnodes-v7-3-c88f74c90dd6@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-05-27ARM: omap1: use platform_device_register_full() for GPIO devices on OMAP 16xxBartosz Golaszewski
Ahead of changes attaching GPIO controller's software nodes referenced from the Nokia 770 board files to their target devices, switch the method for registering the platform devices to the platform_device_register_full() variant. This is done to leverage the new swnode field of struct platform_device_info which automate the software node's registration and assignment. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi> Link: https://patch.msgid.link/20260430-nokia770-gpio-swnodes-v7-2-c88f74c90dd6@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-05-27ARM: omap1: drop unused variable from omap16xx_gpio_init()Bartosz Golaszewski
The pdata variable is set but not used. Remove it. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi> Link: https://patch.msgid.link/20260430-nokia770-gpio-swnodes-v7-1-c88f74c90dd6@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-05-27MIPS: alchemy: db1300: switch to static device propertiesDmitry Torokhov
Convert "5way switch" gpio-keys device and smsc911x ethernet controller to use static device properties instead of bespoke platform data structures for configuration. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> [Bartosz: use platform_device_info::swnode] Tested-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-05-27MIPS: alchemy: gpr: switch to static device propertiesDmitry Torokhov
Convert I2C-gpio device and GPIO-connected LEDs on GPR board to software nodes/properties, so that support for platform data can be removed from gpio-leds driver (which will rely purely on generic device properties for configuration). Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> [Bartosz: use platform_device_info::swnode] Tested-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-05-27MIPS: alchemy: db1000: use nodes attached to GPIO chips in propertiesDmitry Torokhov
GPIO subsystem is switching the way it locates GPIO chip instances for GPIO references in software nodes by doing identity matching instead of matching on node names. Switch to using software nodes attached to gpio chips instead of using freestanding software nodes. Also stop supplying platform data for the spi-gpio controller since spi-gpio driver can derive number of chipselect lines from device properties. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Tested-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-05-27MIPS: alchemy: mtx1: attach software nodes to GPIO chipsDmitry Torokhov
GPIO subsystem is switching the way it locates GPIO chip instances for GPIO references in software nodes from matching on node names to identity matching, which necessitates assigning firmware nodes (software nodes) to GPIO chips. Move the node definitions for alchemy-gpio1 and alchemy-gpio2 to arch/misp/alchemy/common/gpiolib.c, register them there, and attach them to gpio_chip instances. Adjust MTX1 board file to use these nodes. Note that because nodes need to be registered before they can be used in PROPERTY_ENTRY_GPIO() we have to do the registration at postcore_initcall level, otherwise (due to the link order) MTX1 board initialization code will run first. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> [Bartosz: use platform_device_info::swnode] Tested-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-05-27MIPS: alchemy: provide visible function prototypes to board filesBartosz Golaszewski
Board files under arch/mips/alchemy/ define functions called from db1xxx.c but their prototypes are only in that .c file instead of being declared in a common header. This causes several build warnings about missing prototypes. Provide these prototypes in a new header and include it where necessary. Tested-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-05-27MIPS: alchemy: platform: add missing includeBartosz Golaszewski
Pull in the platform.h header into platform.c to fix the following warning: arch/mips/alchemy/devboards/platform.c:68:12: warning: no previous prototype for ‘db1x_register_pcmcia_socket’ [-Wmissing-prototypes] 68 | int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/alchemy/devboards/platform.c:152:12: warning: no previous prototype for ‘db1x_register_norflash’ [-Wmissing-prototypes] 152 | int __init db1x_register_norflash(unsigned long size, int width, | ^~~~~~~~~~~~~~~~~~~~~~ Tested-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-05-27MIPS: ip22-gio: do not export device release functionJohan Hovold
There is no need to export the gio device release function as the devices are reference counted. Drop the export along with the unused inline wrapper. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-05-27MIPS: ip22-gio: switch to dynamic root deviceJohan Hovold
Driver core expects devices to be dynamically allocated and will, for example, complain loudly when no release function has been provided. Use root_device_register() to allocate and register the root device instead of open coding using a static device. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-05-27MIPS: ip22-gio: fix device reference leak in probeJohan Hovold
The gio probe function needlessly takes a device reference which is never released and therefore prevents unbound gio devices from being freed. Fixes: e84de0c61905 ("MIPS: GIO bus support for SGI IP22/28") Cc: stable@vger.kernel.org # 3.3 Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-05-27MIPS: ip22-gio: fix gio device memory leakJohan Hovold
The gio device release callback was never wired up so gio devices are not freed when the last reference is dropped. Fixes: e84de0c61905 ("MIPS: GIO bus support for SGI IP22/28") Cc: stable@vger.kernel.org # 3.3 Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-05-27MIPS: ip22-gio: fix kfree() of static objectJohan Hovold
The gio bus root device is a statically allocated object which must not be freed by kfree() on failure to register the device or bus. Fixes: 82242d28ff8b ("MIPS: IP22: Add missing put_device call") Cc: stable@vger.kernel.org # 3.17 Cc: Levente Kurusa <levex@linux.com> Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-05-27ARM: dts: aspeed: sanmiguel: Fix the CPU_CHIPTHROT linenamePotin Lai
Fix the GPIO linenames for CPU_CHIPTHROT signals. The signals were incorrectly marked as output ("-O") while they are actually input signals ("-I"). [arj: Drop list of changed names] Signed-off-by: Potin Lai <potin.lai@quantatw.com> Link: https://patch.msgid.link/20260523-potin-update-sanmiguel-dts-20260522-v1-2-169f5fceb5f9@quantatw.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-05-27ARM: dts: aspeed: sanmiguel: Add IOEXP interrupt pin settingsPotin Lai
Kernel dmesg reports IRQ #44 being disabled due to unhandled interrupts from multiple PCA953x IO expanders: [ 447.047861] irq 44: nobody cared (try booting with the "irqpoll" option) [ 447.063124] handlers: [ 447.068176] [<2ab869ad>] irq_default_primary_handler threaded [<b8adc310>] pca953x_irq_handler [ 447.087268] [<2ab869ad>] irq_default_primary_handler threaded [<b8adc310>] pca953x_irq_handler [ 447.106344] [<2ab869ad>] irq_default_primary_handler threaded [<b8adc310>] pca953x_irq_handler [ 447.125421] [<2ab869ad>] irq_default_primary_handler threaded [<b8adc310>] pca953x_irq_handler [ 447.144513] [<2ab869ad>] irq_default_primary_handler threaded [<b8adc310>] pca953x_irq_handler [ 447.163587] [<2ab869ad>] irq_default_primary_handler threaded [<b8adc310>] pca953x_irq_handler [ 447.182663] [<2ab869ad>] irq_default_primary_handler threaded [<b8adc310>] pca953x_irq_handler [ 447.201756] [<2ab869ad>] irq_default_primary_handler threaded [<b8adc310>] pca953x_irq_handler [ 447.220837] Disabling IRQ #44 The affected IOEXP nodes are missing interrupt pin configuration in the device tree, causing the interrupt line to remain asserted and resulting in repeated unhandled IRQ events. Add the required interrupt-related properties for the affected IOEXP devices to ensure proper interrupt handling and prevent the IRQ from being disabled. [arj: Drop markdown code-block fence, favour indentation] Signed-off-by: Potin Lai <potin.lai@quantatw.com> Link: https://patch.msgid.link/20260523-potin-update-sanmiguel-dts-20260522-v1-1-169f5fceb5f9@quantatw.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-05-27ARM: dts: aspeed: clemente: Remove IOB NIC TMP421 nodesMike Hsieh
Remove the TMP421 sensor entry from the DTS, as it is no longer the primary telemetry source. Accessing the CX8 NIC via I2C while it is powered off causes voltage leakage on the bus, leading to EEPROM corruption on shared I2C devices. Removing this node prevents the BMC from initiating traffic to the NIC during initialization, protecting the integrity of the shared bus. Signed-off-by: Mike Hsieh <mike.quanta.115@gmail.com> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-05-27ARM: dts: aspeed: Enable networking for Asus Kommando IPMI CardAnirudh Srinivasan
Adds the DT nodes needed for ethernet support for Asus Kommando, with phy mode set to rgmii-id. When this DT was originally added, the phy mode was set to rgmii (which was incorrect). It was suggested to remove networking support from the DT till the Aspeed networking driver was patched so that the correct phy mode could be used. The discussion in [1] mentions that u-boot was inserting clk delays that weren't needed, which resulted in needing to set the phy mode in linux to rgmii incorrectly. The solution suggested there was to patch u-boot to no longer insert these clk delays and use rgmii-id as the phy mode for any future DTs added to linux. This DT was tested (on the OpenBMC u-boot fork [2]) with a u-boot DT modified to insert clk delays of 0 (instead of patching u-boot itself). [3] adds a u-boot DT for this device (without networking) and describes how to patch it to add networking support. If this patched DT is used, then networking works with rgmii-id phy mode in both u-boot and linux. [1] https://lore.kernel.org/linux-aspeed/ef88bb50-9f2c-458d-a7e5-dc5ecb9c777a@lunn.ch/ [2] https://github.com/openbmc/u-boot/tree/v2019.04-aspeed-openbmc [3] https://lore.kernel.org/openbmc/20260328-asus-kommando-v2-1-2a656f8cd314@gmail.com/ Signed-off-by: Anirudh Srinivasan <anirudhsriniv@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20260331-asus-kommando-networking-v2-1-f7d72ae5d40d@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-05-27ARM: dts: aspeed: rainiera6: Add Meta Rainiera6 BMCNeil Cheng
Add device tree for the Meta (Facebook) Rainiera6 compute node, based on AST2600 BMC. Signed-off-by: Neil Cheng <neilcheng0417@gmail.com> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-05-26KVM: x86: Treat KVM's virtual PMU as disabled for TDX VMsVishal Annapurve
Introduce a "protected PMU" concept, and use it to disable KVM's virtual PMU for TDX VMs, as the PMU state for TDX VMs is virtualized by the TDX Module[1], i.e. _can't_ emulated/virtualized by KVM, and KVM doesn't yet support enabling/exposing PMU functionality for/to TDX VMs. For now, simply treat the PMU as disabled, as it's not clear what all needs to be changed, e.g. KVM needs to do at least: 1) Configure TD_PARAMS to allow guests to use performance monitoring. 2) Restrict the TD to a subset of the PEBS counters if supported. 3) Limit the TD to setup a certain perfmon events using basic/enhanced event filtering. Explicitly disallow enabling the PMU via KVM_CAP_PMU_CAPABILITY for VMs with a protected PMU to prevent userspace from circumventing KVM's protections. Link: https://cdrdv2.intel.com/v1/dl/getContent/733575 Section 15.2[1] Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Vishal Annapurve <vannapurve@google.com> Link: https://patch.msgid.link/20260522151534.652522-1-vannapurve@google.com [sean: massage shortlog and changelog] Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-05-26KVM: VMX: Synthesize nested EPT violation GVA_IS_VALID/GVA_TRANSLATED bitsKevin Cheng
When injecting an EPT Violation into L2 in response to a fault detected while emulating an L2 GVA access, synthesize the GVA_IS_VALID and GVA_TRANSLATED bits using information provided by the walker, instead of pulling the bits from vmcs02.EXIT_QUALIFICATION. The information in vmcs02.EXIT_QUALIFICATION is valid/correct if and only if the fault being injected into L1 is the direct result of an EPT Violation VM-Exit from L2. E.g. if KVM is emulating an I/O instruction and the memory operand's translation through L1's EPT fails, using vmcs02.EXIT_QUALIFICATION is wrong as the semantics for EXIT_QUALIFICATION would be for an I/O exit, not an EPT Violation exit. Opportunistically clean up the formatting for creating the mask of bits to pull from vmcs02.EXIT_QUALIFICATION. Signed-off-by: Kevin Cheng <chengkev@google.com> [sean: use plumbed in @access bits, massage changelog] Link: https://patch.msgid.link/20260522232701.3671446-5-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-05-26KVM: SVM: Fix nested NPF injection of PFERR_GUEST_{PAGE,FINAL}_MASK bitsKevin Cheng
Fix KVM's generation of PFERR_GUEST_{PAGE,FINAL}_MASK bits when injecting a Nested Page Fault into L1. Currently, KVM blindly stuffs GUEST_FINAL into L1, which is blatantly wrong given that KVM obviously generates NPFs for page table accesses. There are two paths that trigger NPF injection: hardware NPF exits (from L2) and emulation-triggered faults, i.e. when KVM detects a NPF as part of emulating an L2 GVA access. For the hardware case, use the bits verbatim from the VMCB, as KVM is simply forwarding a NPF to L1. For the emulation case, propagate the GUEST_{PAGE,FINAL} bits from the access field (which were recently added for MBEC+GMET support). To differentiate between the two cases, add "hardware_nested_page_fault" to "struct x86_exception", and set it when injecting a NPF in response to an NPF exit from L2. To help guard against future goofs, assert that exactly one of GUEST_PAGE or GUEST_FINAL is set when injecting a NPF. Unlike VMX, there are no (known) cases where hardware doesn't set either bit, and KVM should always set one or the other when emulating a GVA access. Signed-off-by: Kevin Cheng <chengkev@google.com> [sean: use plumbed in @access bits, massage changelog] Link: https://patch.msgid.link/20260522232701.3671446-4-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-05-26KVM: x86: Tell ->inject_page_fault() whether or a fault came from hardwareSean Christopherson
When injecting a page fault (including nested TDP faults into L1), tell the injection routine whether or not the fault originated in hardware, i.e. if KVM is effectively forwarding a fault it intercept. For nested TDP fault injection, KVM needs to grab PAGE_WALK vs. GUEST_FINAL information from the VMCB/VMCS, _if_ the fault originated in hardware. Note, simply checking whether or not the original exit was due a #NPF or EPT Violation isn't sufficient/correct, as the fault being synthesized for L1 may or may not be the "same" fault that triggered a VM-Exit from L2. E.g. if access to emulated MMIO in L2 hits a !PRESENT fault (EPT Violation or #NPF), e.g. because MMIO caching is disabled or it's the first time the GPA has been accessed by L2, then KVM will enter the emulator. If emulating the MMIO instruction then hits a nested TDP fault, e.g. because L2 was accessing MMIO with a MOVSQ (memory-to-memory move), or because L1 has since unmapped the code stream, then the TDP fault synthesized to L1 will not be the same emulated fault the triggered the VM-Exit. No functional change intended (nothing uses the new param, yet...). Link: https://patch.msgid.link/20260522232701.3671446-3-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>