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2026-05-21KVM: arm64: Fix CONFIG_PKVM_DISABLE_STAGE2_ON_PANICVincent Donnefort
A typo in the config guard in __hyp_do_panic broke the stage-2 disabling and made backtraces for pKVM quite unreliable. Fix that typo. Fixes: 9019e82c7e46 ("KVM: arm64: Add PKVM_DISABLE_STAGE2_ON_PANIC") Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://patch.msgid.link/20260520220830.273289-1-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-21LoongArch: Remove unused code to avoid build warningHuacai Chen
After commit feee6b2989165631b1 ("mm/memory_hotplug: shrink zones when offlining memory"), __remove_pages() doesn't need the "zone" parameter so the "page" variable is also unused. Remove the unused code to avoid such build warning: arch/loongarch/mm/init.c: In function 'arch_remove_memory': arch/loongarch/mm/init.c:134:22: warning: variable 'page' set but not used [-Wunused-but-set-variable=] 134 | struct page *page = pfn_to_page(start_pfn); Cc: <stable@vger.kernel.org> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2026-05-21LoongArch: Avoid initrd overlap during kernel relocationWANG Rui
Validate the relocation address against the initrd region specified via "initrd=" or "initrdmem=" on the command line. Reject relocation targets that overlap the initrd to prevent memory corruption during early boot. Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: WANG Rui <wangrui@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2026-05-21LoongArch: Skip relocation-time KASLR if already appliedWANG Rui
When the kernel is relocated during early boot (efistub or kexec_file), a randomized load address may has already been selected and applied. In this case, performing KASLR again in relocate.c is unnecessary. Note: strictly-defined KASLR means the kernel's final runtime address has a random offset from the kernel's load address, which is implemented in relocate.c; broadly-defined KALSR means the kernel's final runtime address has a random offset from the kernel's link address (a.k.a. VMLINUX_LOAD_ADDRESS), which also include the efistlub implementation, kexec_file implementation and QEMU direct kernel boot. kaslr_disabled() return true only means strictly-defined KASLR is disabled. Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: WANG Rui <wangrui@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2026-05-21efi/loongarch: Randomize kernel preferred address for KASLRWANG Rui
Introduce efi_get_kimg_kaslr_address() helper to compute the preferred kernel image load address dynamically when CONFIG_RANDOMIZE_BASE is enabled. The function derives a random offset by using the EFI-provided randomness combined with the timer tick value, and constrains it within CONFIG_RANDOMIZE_BASE_MAX_OFFSET. Update EFI_KIMG_PREFERRED_ADDRESS to call this helper so that the EFI stub can select a randomized load address when KASLR is active, while preserving the original base address behavior when KASLR is disabled or "nokaslr" is specified. Note: LoongArch can't KASLR for hibernation, so set efi_nokaslr to true if "resume=<devname>" is explicitly specified in cmdline. Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: WANG Rui <wangrui@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2026-05-21ring-buffer: Flush and stop persistent ring buffer on panicMasami Hiramatsu (Google)
On real hardware, panic and machine reboot may not flush hardware cache to memory. This means the persistent ring buffer, which relies on a coherent state of memory, may not have its events written to the buffer and they may be lost. Moreover, there may be inconsistency with the counters which are used for validation of the integrity of the persistent ring buffer which may cause all data to be discarded. To avoid this issue, stop recording of the ring buffer on panic and flush the cache of the ring buffer's memory. Fixes: e645535a954a ("tracing: Add option to use memmapped memory for trace boot instance") Cc: stable@vger.kernel.org Cc: Will Deacon <will@kernel.org> Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Cc: Ian Rogers <irogers@google.com> Link: https://patch.msgid.link/177751969602.2136606.12031934362587643488.stgit@mhiramat.tok.corp.google.com Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
2026-05-21openat2: introduce EFTYPE error codeDorjoy Chowdhury
Introduce a new error code EFTYPE for wrong file type operations. EFTYPE is already used in BSD systems like FreeBSD and macOS. This will be used by the upcoming OPENAT2_REGULAR flag support to return a specific error when a path doesn't refer to a regular file. Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Link: https://patch.msgid.link/20260328172314.45807-2-dorjoychy111@gmail.com Reviewed-by: Jeff Layton <jlayton@kernel.org> Reviewed-by: Aleksa Sarai <aleksa@amutable.com> Signed-off-by: Christian Brauner (Amutable) <brauner@kernel.org>
2026-05-21KVM: arm64: vgic-v2: Don't init the vgic on in-kernel interrupt injectionMarc Zyngier
We now have the lazy init on three paths: - on first run of a vcpu - on first injection of an interrupt from userspace and irqfd - on first injection of an interrupt from kernel space as part of the device emulation (timers, PMU, vgic MI) Given that we recompute the state of each in-kernel interrupt every time we are about to enter the guest, we can drop the lazy init from the kernel injection path. This solves a bunch of issues related to vgic_lazy_init() being called in non-preemptible context, such as vcpu reset. Reviewed-by: Oliver Upton <oupton@kernel.org> Link: https://patch.msgid.link/20260520100200.543845-7-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-21KVM: arm64: vgic-v2: Force vgic init on injection outside the run loopMarc Zyngier
Make sure that any attempt to inject an interrupt from userspace or an irqfd results in the GICv2 lazy init to take place. This is not currently necessary as the init is also performed on *any* interrupt injection. But as we're about to remove that, let's introduce it here. Reviewed-by: Oliver Upton <oupton@kernel.org> Link: https://patch.msgid.link/20260520100200.543845-6-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-21KVM: arm64: pmu: Kill the PMU interrupt level cacheMarc Zyngier
Just like the timer, the PMU has an interrupt cache that serves little purpose. Drop it. Reviewed-by: Oliver Upton <oupton@kernel.org> Link: https://patch.msgid.link/20260520100200.543845-5-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-21KVM: arm64: timer: Kill the per-timer irq level cacheMarc Zyngier
The timer code makes use of a per-timer irq level cache, which looks like a very minor optimisation to avoid taking a lock upon updating the GIC view of the interrupt when it is unchanged from the previous state. This is coming in the way of more important correctness issues, so get rid of the cache, which simplifies a couple of minor things. Reviewed-by: Oliver Upton <oupton@kernel.org> Link: https://patch.msgid.link/20260520100200.543845-4-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-21KVM: arm64: Simplify userspace notification of interrupt stateMarc Zyngier
The userspace notification of interrupts is has a few problems: - it is utterly pointless - it is annoyingly split between detecting the need for notification and the population of the interrupts in the run structure We can't do anything about the former (yet), but the latter can be addressed. If we detect that we must notify userspace, we know that we are going to exit, as we populate the exit status. Which means we can also populate the interrupt state at this stage and be done with it. This simplifies the structure of the code. Reviewed-by: Oliver Upton <oupton@kernel.org> Link: https://patch.msgid.link/20260520100200.543845-3-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-21KVM: arm64: timer: Repaint kvm_timer_{should,irq_can}_fire() to ↵Marc Zyngier
kvm_timer_{pending,enabled}() kvm_timer_should_fire() seems to date back to a time where the author of the timer code didn't seem to have made the word "pending" part of their vocabulary. Having since slightly improved on that front, let's rename this predicate to kvm_timer_pending(), which clearly indicates whether the timer interrupt is pending or not. Similarly, kvm_timer_irq_can_fire() is renamed to kvm_timer_enabled(). Reviewed-by: Joey Gouly <joey.gouly@arm.com> Reviewed-by: Oliver Upton <oupton@kernel.org> Link: https://patch.msgid.link/20260520100200.543845-2-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-21KVM: arm64: nv: Don't save/restore FP register during a nested ERET or exceptionMarc Zyngier
When switching between L1 and L2, we save the old state using kvm_arch_vcpu_put(), mutate the state in memory, then load the new state using kvm_arch_vcpu_load(). Any live FPSIMD/SVE state is saved and unbound, such that it can be lazily restored on a subsequent trap. The FPSIMD/SVE state is shared by exception levels, and only a handful of related control registers need to be changed when transitioning between L1 and L2. The save/restore of the common state is needless overhead, especially as trapping becomes exponentially more expensive with nesting. Avoid this overhead by leaving the common FPSIMD/SVE state live on the CPU, and only switching the state that is distinct for L1 and L2: - the trap controls: the effective values are recomputed on each entry into the guest to take the EL into account and merge the L0 and L1 configuration if in a nested context, or directly use the L0 configuration in non-nested context (see __activate_traps()). - the VL settings: the effective values are are also recomputed on each entry into the guest (see fpsimd_lazy_switch_to_guest()). Since we appear to cover all bases, use the vcpu flags indicating the handling of a nested ERET or exception delivery to avoid the whole FP save/restore shenanigans. SME will have to be similarly dealt with when it eventually gets supported. For an EL1 L3 guest where L1 and L2 have this optimisation, this results in at least a 10% wall clock reduction when running an I/O heavy workload, generating a high rate of nested exceptions. Reviewed-by: Joey Gouly <joey.gouly@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://patch.msgid.link/20260520085036.541666-3-maz@kernel.org
2026-05-21KVM: arm64: nv: Track L2 to L1 exception emulationMarc Zyngier
While we currently track that we are emulating a nested ERET from L1 to L2, we currently don't track the reverse direction (an exception going from L2 to L1). Add a new vcpu state flag for this purpose, which will see some use shortly. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://patch.msgid.link/20260520085036.541666-2-maz@kernel.org
2026-05-20ARM: dts: BCM5301X: EA6500v2: fix USB3Rosen Penev
USB3 needs to have a GPIO pulled HIGH in order to function. Add vcc-gpio to do so. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://lore.kernel.org/r/20260406220528.101340-1-rosenp@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-05-20ARM: dts: BCM5301X: R6300v2: fix USB3Rosen Penev
USB3 needs GPIO to be pulled HIGH in order to function. Add vcc-gpio to do so. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://lore.kernel.org/r/20260406220453.101185-1-rosenp@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-05-20ARM: dts: NSP: Move MX6X pinctrl config to PWM nodeRosen Penev
On boot there is this warning: /axi@18000000/pinctrl@3f1c0: Fixed dependency cycle(s) with /axi@18000000/pinctrl@3f1c0/pwm_leds Fix by moving the pinctrl configuration to pwm, which is the actual consumer. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://lore.kernel.org/r/20260430051612.700050-1-rosenp@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-05-20x86/mm: Disable broadcast TLB flush when PCID is disabledTom Lendacky
Booting with "nopcid" clears X86_FEATURE_PCID and keeps CR4.PCIDE from being set to one. On AMD CPUs that support INVLPGB, broadcast TLB flushing remains enabled. There are two checks that decide whether the global ASID code runs, mm_global_asid() and consider_global_asid(), that key off of the X86_FEATURE_INVLPGB feature. Once an mm becomes active on more than three CPUs, consider_global_asid() assigns it a global ASID, after which flush_tlb_mm_range() takes the broadcast_tlb_flush() path using a non-zero PCID. Issuing an INVLPGB with a non-zero PCID while CR4.PCIDE is not set results in a #GP: Oops: general protection fault, kernel NULL pointer dereference 0x1: 0000 [#1] SMP NOPTI CPU: 158 UID: 0 PID: 3119 Comm: snap Not tainted 7.1.0-rc3 #1 PREEMPT(full) Hardware name: ... RIP: 0010:broadcast_tlb_flush Code: ... 89 da 48 83 c8 07 <0f> 01 fe eb 08 cc cc cc ... Call Trace: <TASK> flush_tlb_mm_range ptep_clear_flush wp_page_copy ? _raw_spin_unlock __handle_mm_fault handle_mm_fault do_user_addr_fault exc_page_fault asm_exc_page_fault All processors that support broadcast TLB invalidation also have PCID support, so it is only the "nopcid" scenario that is of concern. In this situation just disable the broadcast TLB support using the CPUID dependency support by making X86_FEATURE_INVLPGB dependent on X86_FEATURE_PCID. [ bp: Massage commit message. ] Fixes: 4afeb0ed1753 ("x86/mm: Enable broadcast TLB invalidation for multi-threaded processes") Suggested-by: Dave Hansen <dave.hansen@intel.com> Assisted-by: Claude:claude-opus-4.7 Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Rik van Riel <riel@surriel.com> Cc: <stable@kernel.org> Link: https://patch.msgid.link/b915acfd63e8b2a094fdeb8dc608738072518764.1779296450.git.thomas.lendacky@amd.com
2026-05-20Merge tag 'zx29-plat-for-7.2' of ↵Arnd Bergmann
https://gitlab.com/stefandoesinger/zx297520-kernel into soc/arm ARM: zte: Add zx297520v3 platform support This SoC is used in low end LTE-to-WiFi routers, for example some D-Link DWR 932 revisions, ZTE K10, ZLT S10 4G, but also models that are branded and sold by ISPs themselves. They are widespread in Africa, China, Russia and Eastern Europe. This SoC is a relative of the zx296702 and zx296718 that had some upstream support until commit 89d4f98ae90d ("ARM: remove zte zx platform"). * tag 'zx29-plat-for-7.2' of https://gitlab.com/stefandoesinger/zx297520-kernel: ARM: zte: Add zx297520v3 platform support Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-05-20Merge tag 'zx29-dts-for-7.2' of ↵Arnd Bergmann
https://gitlab.com/stefandoesinger/zx297520-kernel into soc/dt ARM: dts: zte: zx297520v3 device tree for 7.2 This pull request adds board bindings and DTS files for ZTE zx297520v3 boards as well as one initial device (D-Link DWR 932M) based on this board. * tag 'zx29-dts-for-7.2' of https://gitlab.com/stefandoesinger/zx297520-kernel: ARM: dts: zte: Add D-Link DWR-932M support dt-bindings: arm: zte: Add D-Link DWR932M board based on zx297520v3 SoC Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-05-20Merge tag 'soc-pxa-gpio-for-v7.2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into soc/arm ARM: pxa: software node oriented GPIO rework for v7.2 - attach software nodes to their target GPIO controllers on PXA platforms * tag 'soc-pxa-gpio-for-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: ARM: pxa: pxa27x: attach software node to its target GPIO controller ARM: pxa: pxa25x: attach software node to its target GPIO controller ARM: pxa: spitz: attach software nodes to their target GPIO controllers ARM: pxa: statify platform device definitions in spitz board file Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-05-20console: mdacon: remove this obsolete driverEthan Nelson-Moore
The mdacon driver supports using ISA MDA or Hercules-compatible display adapters as a secondary text console. This was commonly used in the 1990s and earlier for debugging software which took over the primary display. It is highly unlikely anyone is doing so nowadays because serial consoles and much better methods of debugging exist. The driver is not enabled by any defconfig, nor any of the dozens of distro configs collected at [1]. It has been relegated to VTs 13-16 since commit 0b9cf3aa6b1e ("mdacon messing up default vc's - set default to vc13-16 again") in Linux 2.6.27 (and before Linux 2.5.53 - see the link in the message of the above commit). The change in 2.6.27 was done because it was incorrectly detecting non-MDA adapters as MDA and taking over all VTs, rendering them unusable. Furthermore, vgacon supports using MDA/Hercules-compatible adapters as the primary text console, so any systems with only one of these adapters were already using vgacon and will not experience any loss in functionality from the removal of this driver. Given all of these factors, the mdacon driver is likely entirely unused. Remove it. [1] https://github.com/nyrahul/linux-kernel-configs/tree/f0bee86a135a0406ea427855f52702dd00d770f9 Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com> Signed-off-by: Helge Deller <deller@gmx.de>
2026-05-20x86/extable: switch to using FIELD_GET_SIGNED()Yury Norov
The EX_DATA register is laid out such that EX_DATA_IMM occupied MSB. It's done to make sure that FIELD_GET() will sign-extend the IMM field during extraction. To enforce that, all EX_DATA masks are made signed integers. This works, but relies on the particular implementation of FIELD_GET(), i.e. masking then shifting, not vice versa; and the particular placement of the fields in the register. Switch to using the dedicated FIELD_GET_SIGNED(), and relax those limitations. Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Yury Norov <ynorov@nvidia.com>
2026-05-20arm64: defconfig: Enable PCI M.2 power sequencing driverManivannan Sadhasivam
POWER_SEQUENCING_PCIE_M2 driver handles power supply to the PCIe M.2 connectors and is required on wide variety of ARM64 platforms such as Qcom Snapdragon X Elite laptops and Mediatek Dojo Chromebooks. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260514065017.11305-1-manivannan.sadhasivam@oss.qualcomm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-05-20Merge tag 'renesas-dts-for-v7.2-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v7.2 - Add GPU support for R-Car M3-W(+)-based ULCB and Salvator-X(S) development boards, - Add Ethernet, OPP table, interrupt, pin control, and watchdog support for the RZ/G3L SoC and the RZ/G3L SMARC SoM board, - Add Coresight support for the R-Mobile A1 and APE6 SoCs, and the Armadillo-800 EVA and APE6EVM development boards, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v7.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (40 commits) ARM: dts: renesas: r8a73a4: Describe coresight on R-Mobile APE6 ARM: dts: renesas: r8a73a4: Add ZT/ZTR trace clock on R-Mobile APE6 dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6 arm64: dts: renesas: rzg3l-smarc-som: Enable watchdog arm64: dts: renesas: r9a08g046: Add wdt device node arm64: dts: renesas: salvator-common: Sort sound node arm64: dts: renesas: ebisu: Sort sound node arm64: dts: renesas: gray-hawk-single: Fix AVB0 PHY node alignment arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface arm64: dts: renesas: rzg3l-smarc-som: Add pinctrl configuration for ETH0 arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol arm64: dts: renesas: r9a08g046: Add pincontrol node arm64: dts: renesas: r9a08g046: Add ICU node arm64: dts: renesas: r9a08g046: Add OPP table arm64: dts: renesas: Add pinctrl reset-names for RZ/G2L and RZ/V2H family SoCs ARM: dts: renesas: r8a7740: Describe coresight ARM: dts: renesas: r8a7740: Add ZT/ZTR trace clocks arm64: dts: renesas: rzg3l-smarc-som: Enable eth0 (GBETH0) interface arm64: dts: renesas: r9a08g046: Add GBETH nodes arm64: dts: renesas: r8a77961-salvator-xs: Enable GPU support ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-05-20arm64: Kconfig: drop unneeded dependency on OF_GPIO for ARCH_MVEBUBartosz Golaszewski
OF_GPIO is selected automatically on all OF systems. Any symbols it controls also provide stubs so there's really no reason to select it explicitly. ARCH_MVEBU already selects GPIOLIB, drop the redundant OF_GPIO dependency. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-05-20ARM: dts: omap2: add stlc4560 spi-wireless nodeArnd Bergmann
Converted from the platform_device creation in board-n8x0.c. Link: https://lore.kernel.org/all/20230314163201.955689-1-arnd@kernel.org/ Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20260507212451.3333185-4-arnd@kernel.org Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2026-05-20p54spi: convert to devicetreeArnd Bergmann
The Prism54 SPI driver hardcodes GPIO numbers and expects users to pass them as module parameters, apparently a relic from its life as a staging driver. This works because there is only one user, the Nokia N8x0 tablet. Convert this to the gpio descriptor interface and DT based probing to improve this and simplify the code at the same time. Acked-by: Christian Lamparter <chunkeey@gmail.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://patch.msgid.link/20260507212451.3333185-3-arnd@kernel.org Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2026-05-20riscv: dts: spacemit: fix uboot partition offset on Milk-V JupiterAurelien Jarno
Correct the uboot partition node name to match its actual offset. Fixes: 2829823956f0 ("riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter") Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260519041458.3287843-6-aurelien@aurel32.net Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-05-20riscv: dts: spacemit: enable SD card support on Milk-V JupiterAurelien Jarno
Add complete SD card controller support with UHS high-speed modes. - Enable sdhci0 controller with 4-bit bus width - Configure card detect GPIO with pull-up - Connect vmmc-supply to buck4 for 3.3V card power - Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching - Add dual pinctrl states for voltage-dependent pin configuration - Support UHS-I SDR25, SDR50, and SDR104 modes - Alias it as mmc1 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260519041458.3287843-5-aurelien@aurel32.net Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-05-20riscv: dts: spacemit: enable eMMC on Milk-V JupiterAurelien Jarno
The Milk-V Jupiter board has a connector for an eMMC module. Add an entry for it in the device tree and alias it mmc0. Mark the device as non-removable as eMMC modules have no CD pin and are not supposed to be inserted or removed while the system is running. On systems without an eMMC module installed, the kernel emits the following informational message during boot: mmc0: SDHCI controller on d4281000.mmc [d4281000.mmc] using ADMA mmc0: Failed to initialize a non-removable card Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260519041458.3287843-4-aurelien@aurel32.net Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-05-20riscv: dts: spacemit: sort aliases on Milk-V JupiterAurelien Jarno
Before adding more aliases, just sort them. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260519041458.3287843-3-aurelien@aurel32.net Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-05-20riscv: dts: spacemit: set console baud rate on Milk-V JupiterAurelien Jarno
Because the default console's baud rate is not set, defconfig kernels do not have any serial output on this platform. Set the baud rate to 115200, matching what is used by U-Boot etc on this platform. See-also: 24c12ca43b12c ("dts: spacemit: set console baud rate on bpif3") Fixes: 5b90a3d6092d9 ("riscv: dts: spacemit: Add Milk-V Jupiter board device tree") Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260519041458.3287843-2-aurelien@aurel32.net Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-05-20riscv: dts: spacemit: enable USB3 on OrangePi R2SChukun Pan
Enable the DWC3 USB3.0 controller and its associated PHY on the OrangePi R2S. The USB regulator provides VBUS for USB2 and USB3 ports, but the USB2 ports are handled by a separate controller. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260518100030.2354606-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-05-20riscv: dts: spacemit: Add thermal sensor for K1 SoCShuwei Wu
Include the Thermal Sensor node in the SpacemiT K1 dtsi with definitions for registers, clocks, and interrupts. Additionally, configure thermal zones for the soc, package, gpu, and clusters to enable temperature monitoring via the thermal framework. Tested-by: Vincent Legoll <legoll@online.fr> # OrangePi-RV2 Tested-by: Gong Shuai <gsh517025@gmail.com> Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260427-k1-thermal-v5-3-df39187480ed@mailbox.org Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-05-20riscv: dts: spacemit: Add PDMA controller node for K3 SoCTroy Mitchell
Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. The PDMA controller provides general-purpose DMA capabilities for various peripheral devices across the system to offload CPU data transfers. Unlike the previous K1 SoC, where some DMA masters had memory addressing limitations (e.g. restricted to the 0-4GB space) requiring a dedicated dma-bus with dma-ranges to restrict memory allocations, the K3 DMA masters have full memory addressing capabilities. Therefore, the PDMA node is now instantiated directly under the main soc bus. Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://patch.msgid.link/20260518-k3-pdma-v6-4-67fdf319a8f8@linux.spacemit.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-05-20s390/processor: Implement cpu_relax() with cpu serializationHeiko Carstens
There are many loops in the form of while (READ_ONCE(*somelocation)) cpu_relax(); Strictly speaking the architecture requires serialization instead of only a compiler barrier in the loop so the READ_ONCE() will see an updated value. However real hardware does not require this (see IBM z Systems Processor Optimization Primer - FAQ [1]), but it is still recommended to add serialization. Given that cpu_relax() is doing nothing useful, it does not hurt to add the single and fast instruction which makes sure that serialization happens, and such loops may be left a bit faster. [1] https://community.ibm.com/community/user/viewdocument/microprocessor-optimization-primer Reviewed-by: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2026-05-20s390/processor: Remove duplicated cpu_relax() defineHeiko Carstens
cpu_relax() is defined identically at two different locations. Just like most other architectures remove the implementation at asm/processor.h and only use the one at asm/vdso/processor.h, avoiding code duplication. Reviewed-by: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2026-05-20s390/barrier: Use alternative instead of ifdef for bcr_serialize()Heiko Carstens
Use an alternative to implement bcr_serialize() and use alternative patching to select between serialization and fast-serialization depending on the corresponding facility bit. Reviewed-by: Jan Polensky <japo@linux.ibm.com> Reviewed-by: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2026-05-20s390/mm: Map empty zero pages read-onlyHeiko Carstens
On arm64 the empty zero page is going to be mapped read-only [1]. Do the same for s390 with an explicit set_memory_ro() call. [1] https://lore.kernel.org/all/20260427153416.2103979-19-ardb+git@google.com/ Suggested-by: Christian Borntraeger <borntraeger@linux.ibm.com> Acked-by: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2026-05-20s390/topology: Use zero-based numbering for containing entitiesAlexandra Winter
Start the numbering scheme for higher-level topology structures (like socket, book, drawer) at zero, matching the convention for other hardware identifiers like e.g. CPU numbers. Hardware documentation, the Hardware Management Console and other tools like zmemtopo also use zero-based numbering for these containing entities. Aligning the numbering in sysfs, procfs, and tools like lscpu improves user experience by making it easier to correlate topology information across different interfaces. If available, Linux on s390 derives this physical topology information from the stsi function code 15 store_topology instruction, which is defined to start at 1 for the lowest numbered container id. Subtract one, so drawer_id, book_id and socket_id in cpu_topology[] start with 0 for the lowest numbered entity; and /proc/cpuinfo and tools like 'lscpu -ye' display the expected values. Display only, no functional change intended. Example: In a partition with 3 cores in a system with 8 cores per socket; 2 sockets per book; 4 books per dawer; and 4 drawers: Before this fix: $ lscpu -ye CPU NODE DRAWER BOOK SOCKET CORE L1d:L1i:L2 ONLINE CONFIGURED POLARIZATION ADDRESS 0 0 2 4 1 0 0:0:0 yes yes vert-high 0 1 0 2 4 1 0 1:1:1 yes yes vert-high 1 2 0 2 4 1 1 2:2:2 yes yes vert-medium 2 3 0 2 4 1 1 3:3:3 yes yes vert-medium 3 4 0 2 4 2 3 4:4:4 yes yes vert-low 4 5 0 2 4 2 3 5:5:5 yes yes vert-low 5 After this fix: $ lscpu -ye CPU NODE DRAWER BOOK SOCKET CORE L1d:L1i:L2 ONLINE CONFIGURED POLARIZATION ADDRESS 0 0 1 3 0 0 0:0:0 yes yes vert-high 0 1 0 1 3 0 0 1:1:1 yes yes vert-high 1 2 0 1 3 0 1 2:2:2 yes yes vert-medium 2 3 0 1 3 0 1 3:3:3 yes yes vert-medium 3 4 0 1 3 1 3 4:4:4 yes yes vert-low 4 5 0 1 3 1 3 5:5:5 yes yes vert-low 5 For KVM guests, qemu emulates the stsi FC15 store_topology instruction. This emulation currently erroneously starts id numbering at 0. A qemu fix is proposed that makes this emulation compliant to the stsi architecture. In case a guest with this patch is running on a qemu without the other fix, it can happen that ids of 255 are displayed erroneously. z/VM currently does not provide or emulate physical topology information to its guests. So this patch does not change anything for z/VM guests. Fixes: 10d385895055 ("[S390] topology: expose core identifier") Signed-off-by: Alexandra Winter <wintera@linux.ibm.com> Acked-by: Heiko Carstens <hca@linux.ibm.com> Acked-by: Christian Borntraeger <borntraeger@linux.ibm.com> Acked-by: Hendrik Brueckner <brueckner@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2026-05-20KVM: arm64: Fix nVHE/pKVM hyp tracing error on invalid descVincent Donnefort
pKVM must validate the host-provided tracing buffer descriptor. However, if an error is found, the hypervisor would just return 0 to the host. Fix the return value on validation failure. While at it, rename the function to hyp_trace_desc_is_valid() and skip validation for the nVHE mode as we trust host-provided data in that case. Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Fixes: 680a04c333fa ("KVM: arm64: Add tracing capability for the nVHE/pKVM hyp") Link: https://lore.kernel.org/r/20260514162624.3477857-1-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-20KVM: arm64: vgic: Free private_irqs when init fails after allocationMichael Bommarito
Companion to commit 250f25367b58 ("KVM: arm64: Tear down vGIC on failed vCPU creation"), which added the missing kvm_vgic_vcpu_destroy() call to the kvm_share_hyp() failure path in kvm_arch_vcpu_create(). The kvm_vgic_vcpu_init() failure path immediately above it has the same shape and still needs the same cleanup. Call kvm_vgic_vcpu_destroy() when kvm_vgic_vcpu_init() fails so private IRQs allocated before a redistributor iodev registration failure are released before the failed vCPU is freed. Fixes: 03b3d00a70b5 ("KVM: arm64: vgic: Allocate private interrupts on demand") Cc: stable@vger.kernel.org Cc: Will Deacon <will@kernel.org> Reviewed-by: Yuan Yao <yaoyuan@linux.alibaba.com> Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Michael Bommarito <michael.bommarito@gmail.com> Link: https://lore.kernel.org/r/20260519135042.2219239-1-michael.bommarito@gmail.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-05-20KVM: arm64: vgic-its: Reject restored DTE with out-of-range num_eventid_bitsMichael Bommarito
Userspace can restore an ITS Device Table Entry whose Size field encodes more EventID bits than the virtual ITS supports. The live MAPD path rejects that state, but vgic_its_restore_dte() accepts it and stores the out-of-range value in dev->num_eventid_bits. Reject restored DTEs with num_eventid_bits > VITS_TYPER_IDBITS before allocating the device. This mirrors the MAPD check and prevents the restored state from reaching vgic_its_restore_itt(), where the unchecked value can be converted into an oversized scan_its_table() range. Fixes: 57a9a117154c ("KVM: arm64: vgic-its: Device table save/restore") Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Michael Bommarito <michael.bommarito@gmail.com> Link: https://lore.kernel.org/r/20260519132519.2142458-1-michael.bommarito@gmail.com Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org
2026-05-20powerpc: Remove unused functionsMukesh Kumar Chaurasiya
After enabling GENERIC_ENTRY some functions are left unused. Cleanup all those functions which includes: - do_syscall_trace_enter - do_syscall_trace_leave - do_notify_resume - do_seccomp Signed-off-by: Mukesh Kumar Chaurasiya <mkchauras@linux.ibm.com> Tested-by: Samir M <samir@linux.ibm.com> Tested-by: David Gow <davidgow@google.com> Tested-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com> Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260427122742.210074-9-mkchauras@gmail.com
2026-05-20powerpc: Enable GENERIC_ENTRY featureMukesh Kumar Chaurasiya
Enable the generic IRQ entry/exit infrastructure on PowerPC by selecting GENERIC_ENTRY and integrating the architecture-specific interrupt and syscall handlers with the generic entry/exit APIs. This change replaces PowerPC’s local interrupt entry/exit handling with calls to the generic irqentry_* helpers, aligning the architecture with the common kernel entry model. The macros that define interrupt, async, and NMI handlers are updated to use irqentry_enter()/irqentry_exit() and irqentry_nmi_enter()/irqentry_nmi_exit() where applicable also convert the PowerPC syscall entry and exit paths to use the generic entry/exit framework and integrating with the common syscall handling routines. Key updates include: - The architecture now selects GENERIC_ENTRY in Kconfig. - Replace interrupt_enter/exit_prepare() with arch_interrupt_* helpers. - Integrate irqentry_enter()/exit() in standard and async interrupt paths. - Integrate irqentry_nmi_enter()/exit() in NMI handlers. - Remove redundant irq_enter()/irq_exit() calls now handled generically. - Use irqentry_exit_cond_resched() for preemption checks. - interrupt.c and syscall.c are simplified to delegate context management and user exit handling to the generic entry path. - The new pt_regs field `exit_flags` introduced earlier is now used to carry per-syscall exit state flags (e.g. _TIF_RESTOREALL). - Remove unused code. This change establishes the necessary wiring for PowerPC to use the generic IRQ entry/exit framework while maintaining existing semantics. This aligns PowerPC with the common entry code used by other architectures and reduces duplicated logic around syscall tracing, context tracking, and signal handling. The performance benchmarks from perf bench basic syscall are below: perf bench syscall usec/op (-ve is improvement) | Syscall | Base | test | change % | | ------- | ----------- | ----------- | -------- | | basic | 0.093543 | 0.093023 | -0.56 | | execve | 446.557781 | 450.107172 | +0.79 | | fork | 1142.204391 | 1156.377214 | +1.24 | | getpgid | 0.097666 | 0.092677 | -5.11 | perf bench syscall ops/sec (+ve is improvement) | Syscall | Base | New | change % | | ------- | -------- | -------- | -------- | | basic | 10690548 | 10750140 | +0.56 | | execve | 2239 | 2221 | -0.80 | | fork | 875 | 864 | -1.26 | | getpgid | 10239026 | 10790324 | +5.38 | IPI latency benchmark (-ve is improvement) | Metric | Base (ns) | New (ns) | % Change | | -------------- | ------------- | ------------- | -------- | | Dry run | 583136.56 | 584136.35 | 0.17% | | Self IPI | 4167393.42 | 4149093.90 | -0.44% | | Normal IPI | 61769347.82 | 61753728.39 | -0.03% | | Broadcast IPI | 2235584825.02 | 2227521401.45 | -0.36% | | Broadcast lock | 2164964433.31 | 2125658641.76 | -1.82% | Thats very close to performance earlier with arch specific handling. Signed-off-by: Mukesh Kumar Chaurasiya <mkchauras@linux.ibm.com> Tested-by: Samir M <samir@linux.ibm.com> Tested-by: David Gow <davidgow@google.com> Tested-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com> Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260427122742.210074-8-mkchauras@gmail.com
2026-05-20powerpc: Prepare for IRQ entry exitMukesh Kumar Chaurasiya
Move interrupt entry and exit helper routines from interrupt.h into the PowerPC-specific entry-common.h header as a preparatory step for enabling the generic entry/exit framework. This consolidation places all PowerPC interrupt entry/exit handling in a single common header, aligning with the generic entry infrastructure. The helpers provide architecture-specific handling for interrupt and NMI entry/exit sequences, including: - arch_interrupt_enter/exit_prepare() - arch_interrupt_async_enter/exit_prepare() - arch_interrupt_nmi_enter/exit_prepare() - Supporting helpers such as nap_adjust_return(), check_return_regs_valid(), debug register maintenance, and soft mask handling. The functions are copied verbatim from interrupt.h.Subsequent patches will integrate these routines into the generic entry/exit flow. No functional change intended. Signed-off-by: Mukesh Kumar Chaurasiya <mchauras@linux.ibm.com> Tested-by: Samir M <samir@linux.ibm.com> Tested-by: David Gow <davidgow@google.com> Tested-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com> Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260427122742.210074-7-mkchauras@gmail.com
2026-05-20powerpc: add exit_flags field in pt_regsMukesh Kumar Chaurasiya
Add a new field `exit_flags` in the pt_regs structure. This field will hold the flags set during interrupt or syscall execution that are required during exit to user mode. Specifically, the `TIF_RESTOREALL` flag, stored in this field, helps the exit routine determine if any NVGPRs were modified and need to be restored before returning to userspace. This addition ensures a clean and architecture-specific mechanism to track per-syscall or per-interrupt state transitions related to register restore. Changes: - Add `exit_flags` and `__pt_regs_pad` to maintain 16-byte stack alignment - Update asm-offsets.c and ptrace.c for offset and validation - Update PT_* constants in uapi header to reflect the new layout Signed-off-by: Mukesh Kumar Chaurasiya <mchauras@linux.ibm.com> Tested-by: Samir M <samir@linux.ibm.com> Tested-by: David Gow <davidgow@google.com> Tested-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com> Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260427122742.210074-6-mkchauras@gmail.com
2026-05-20powerpc: Introduce syscall exit arch functionsMukesh Kumar Chaurasiya
Add PowerPC-specific implementations of the generic syscall exit hooks used by the generic entry/exit framework: - arch_exit_to_user_mode_work_prepare() - arch_exit_to_user_mode_work() These helpers handle user state restoration when returning from the kernel to userspace, including FPU/VMX/VSX state, transactional memory, KUAP restore, and per-CPU accounting. Additionally, move check_return_regs_valid() from interrupt.c to interrupt.h so it can be shared by the new entry/exit logic. No functional change is intended with this patch. Signed-off-by: Mukesh Kumar Chaurasiya <mchauras@linux.ibm.com> Tested-by: Samir M <samir@linux.ibm.com> Tested-by: David Gow <davidgow@google.com> Tested-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com> Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260427122742.210074-5-mkchauras@gmail.com
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-19 02:37:43 +0000