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2026-05-10KVM: x86/mmu: split XS/XU bits for EPTPaolo Bonzini
When EPT is in use, replace ACC_USER_MASK with ACC_USER_EXEC_MASK, so that supervisor and user-mode execution can be controlled independently (ACC_USER_MASK would not allow a setting similar to XU=0 XS=1 W=1 R=1). Replace shadow_x_mask with shadow_xs_mask/shadow_xu_mask, to allow setting XS and XU bits separately in EPT entries. In fact, ACC_USER_EXEC_MASK is already set through ACC_ALL in the kvm_mmu_page roles and propagates to the XU bit of sPTEs even if MBEC is not (yet) enabled in the execution controls. This is fine, because the XU bit is ignored by the processor, and even once KVM supports MBEC this mode will remain for processors that lack the feature. Tested-by: David Riley <d.riley@proxmox.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-05-10KVM: x86: make translate_nested_gpa vendor-specificPaolo Bonzini
EPT and NPT have different rules for passing PFERR_USER_MASK to the nested page table walk. In particular, for final addresses EPT uses the U bit of the guest (nGVA->nGPA) walk. While at it, remove PFERR_USER_MASK from the VMX version of the function, since it is actually ignored by the tables that update_permission_bitmask() generates for EPT. Tested-by: David Riley <d.riley@proxmox.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-05-10KVM: x86/mmu: pass pte_access for final nGPA->GPA walkPaolo Bonzini
The XS/XU bit for EPT are only applied to final accesses, and use the U bit from the page walk itself. This is available in the page walker as pte_access & ACC_USER_MASK but not available to translate_nested_gpa, so pass it down. Tested-by: David Riley <d.riley@proxmox.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-05-10KVM: x86/mmu: pass PFERR_GUEST_PAGE/FINAL_MASK to kvm_translate_gpaPaolo Bonzini
The XS/XU bit for EPT are only applied to final accesses, and use the U bit from the page walk itself. While strictly speaking not necessary (any value of PFERR_USER_MASK would be the same for page table accesses, because they're reads and writes only), it is clearer and less hackish to only apply MBEC to PFERR_GUEST_FINAL_MASK. Allow kvm-intel.ko to distinguish the two cases. Tested-by: David Riley <d.riley@proxmox.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-05-10KVM: x86/mmu: introduce ACC_READ_MASKPaolo Bonzini
Read permissions so far were only needed for EPT, which does not need ACC_USER_MASK. Therefore, for EPT page tables ACC_USER_MASK was repurposed as a read permission bit. In order to implement nested MBEC, EPT will genuinely have four kinds of accesses, and there will be no room for such hacks; bite the bullet at last, enlarging ACC_ALL to four bits and permissions[] to 2^4 bits (u16). The new code does not enforce that the XWR bits on non-execonly processors have their R bit set, even when running nested: none of the shadow_*_mask values have bit 0 set, and make_spte() genuinely relies on ACC_READ_MASK being requested! This works because, if execonly is not supported by the processor, shadow EPT will generate an EPT misconfig vmexit if the XWR bits represent a non-readable page, and therefore the pte_access argument to make_spte() will also always have ACC_READ_MASK set. Tested-by: David Riley <d.riley@proxmox.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-05-10KVM: x86/mmu: separate more EPT/non-EPT permission_fault()Paolo Bonzini
Move more of EPT handling entirely in the existing "if (!ept)" conditional. Use a new "rf" variable instead of uf for read permissions for clarity. Merge smepf and ff into a single variable because EPT's "SMEP" (actually MBEC) is defined differently and does not need smepf. Tested-by: David Riley <d.riley@proxmox.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-05-09arm64: dts: qcom: glymur: Enable cpufreq cooling devicesHaritha S K
Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Haritha S K <haritha.k@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-glymur_cpu_freq-v1-1-d566cc1d32c3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: glymur-crd: Enable LID sensorAbel Vesa
The Glymur CRD has a Hall-effect sensor used for detecting when the lid is opened or closed. Describe it as an SW_LID gpio-key switch. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260428-glymur-dts-add-lid-sensor-v1-1-470cc168e70a@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: defconfig: Enable LPASS LPI pin controller for SM6350Luca Weiss
Build the LPASS LPI pin controller driver for SM6350 as module, which is required for audio functionality on boards such as the Fairphone 4. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20260430-sm6350-lpi-tlmm-v2-5-81d068025b97@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: sm6350: add LPASS LPI pin controllerLuca Weiss
Add LPASS LPI pinctrl node required for audio functionality on SM6350. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20260430-sm6350-lpi-tlmm-v2-4-81d068025b97@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: purwa: Add EL2 overlay for purwa-iot-evkXin Liu
Add support for building an EL2 combined DTB for the purwa-iot-evk in the Qualcomm DTS Makefile. The new purwa-iot-evk-el2.dtb is generated by combining the base purwa-iot-evk.dtb with the x1-el2.dtbo overlay, enabling EL2-specific configurations required by the platform. Signed-off-by: Xin Liu <xin.liu@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260417054200.2402281-1-xin.liu@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: sdm845-lg: Enable qcom,snoc-host-cap-skip-quirkPaul Sajna
The WCN3990 firmware for judyln does not respond to the request for host capabilities. Add the devicetree quirk to skip this request. Signed-off-by: Paul Sajna <sajattack@postmarketos.org> Reviewed-by: David Heidelberg <david@ixit.cz> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-4-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: sdm845-lg-{judyln, judyp}: Reference memory region in fbPaul Sajna
To prevent duplicating the framebuffer address and size point out the existing framebuffer memory region instead of specifying the address manually. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Paul Sajna <sajattack@postmarketos.org> Reviewed-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-3-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: sdm845-lg-common: Change ipa gsi-loader to 'self', add ↵Paul Sajna
memory-region The modem firmware for this device doesn't preload the IPA firmware and requires the OS handles that instead. Set qcom,gsi-loader = "self" to reflect that. Ensure the ipa uses the correct memory. ipa 1e40000.ipa: channel 4 limited to 256 TREs ipa 1e40000.ipa: IPA driver initialized ipa 1e40000.ipa: received modem starting event ipa 1e40000.ipa: received modem running event Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Paul Sajna <sajattack@postmarketos.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-2-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: sdm845-lg-common: Add camera flashPaul Sajna
Camera doesn't work yet (imx351), but we can use the flash as a flashlight. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Paul Sajna <sajattack@postmarketos.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260408-judyln-followup-v1-1-823467519b59@postmarketos.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: lemans: Move PCIe devices into soc nodeShawn Guo
These PCIe devices with MMIO address should be inside soc node rather than outside. Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260331090147.18522-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: talos-evk: Add sound card support with DA7212 codecLe Qi
Add the sound card node for QCS615 Talos EVK with DA7212 codec connected over the Primary MI2S interface. The configuration enables headphone playback and headset microphone capture, both of which have been tested to work. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Le Qi <le.qi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260409030156.155455-3-le.qi@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: talos: Add GPR node, audio services, and MI2S1 TLMM pinsLe Qi
This patch adds the Generic Pack Router (GPR) node together with Audio Process Manager (APM) and Proxy Resource Manager (PRM) audio service nodes to the Talos device tree description. It also introduces MI2S1 pinctrl states for data0, data1, sck, and ws lines, grouped into a single entry at the SoC-level DTSI for better reuse and clarity. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Le Qi <le.qi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260409030156.155455-2-le.qi@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: Use GIC_SPI macro for interrupt-mapKrzysztof Kozlowski
Make the complicated interrupt-map property (with multiple '0' entries) a bit more readable by using known define for GIC_SPI. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260407201839.25759-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: sdm845-xiaomi-beryllium: Enable ath10k host-cap skip quirkAmit Pundir
The Wi-Fi firmware used on Xiaomi Poco F1 (beryllium) phone doesn't support the host-capability QMI request, so add a quirk to skip it on this device. Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20260407-skip-host-cam-qmi-req-v5-3-dfa8a05c6538@ixit.cz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09Merge tag 'powerpc-7.1-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Madhavan Srinivasan: - Fix KASAN sanitization flag for core_$(BITS).o - Fixes for handling offset values in pseries htmdump - Fix interrupt mask in cpm1_gpiochip_add16() - ps3/pasemi fixes to drop redundant result assignment - Fixes in papr-hvpipe code path - powerpc/perf: Update check for PERF_SAMPLE_DATA_SRC marked events Thanks to Aboorva Devarajan, Athira Rajeev, Christophe Leroy (CS GROUP), Geert Uytterhoeven, Haren Myneni, Krzysztof Kozlowski, Mukesh Kumar Chaurasiya (IBM), Nathan Chancellor, Ritesh Harjani (IBM), Shivani Nittor, Sourabh Jain, Thomas Zimmermann, and Venkat Rao Bagalkote. * tag 'powerpc-7.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (21 commits) powerpc/pasemi: Drop redundant res assignment powerpc/ps3: Drop redundant result assignment powerpc/vdso: Drop -DCC_USING_PATCHABLE_FUNCTION_ENTRY from 32-bit flags with clang arch/powerpc: Drop CONFIG_FIRMWARE_EDID from defconfig files powerpc/perf: Update check for PERF_SAMPLE_DATA_SRC marked events powerpc/8xx: Fix interrupt mask in cpm1_gpiochip_add16() powerpc/vmx: avoid KASAN instrumentation in enter_vmx_ops() for kexec powerpc/kdump: fix KASAN sanitization flag for core_$(BITS).o pseries/papr-hvpipe: Fix style and checkpatch issues in enable_hvpipe_IRQ() pseries/papr-hvpipe: Refactor and simplify hvpipe_rtas_recv_msg() pseries/papr-hvpipe: Kill task_struct pointer from struct hvpipe_source_info pseries/papr-hvpipe: Simplify spin unlock usage in papr_hvpipe_handle_release() pseries/papr-hvpipe: Fix the usage of copy_to_user() pseries/papr-hvpipe: Fix & simplify error handling in papr_hvpipe_init() pseries/papr-hvpipe: Fix null ptr deref in papr_hvpipe_dev_create_handle() pseries/papr-hvpipe: Prevent kernel stack memory leak to userspace pseries/papr-hvpipe: Fix race with interrupt handler powerpc/pseries/htmdump: Add memory configuration dump support to htmdump module powerpc/pseries/htmdump: Fix the offset value used in htm status dump powerpc/pseries/htmdump: Fix the offset value used in processor configuration dump ...
2026-05-09arm64: dts: qcom: sdm630: assign adsp_mem region to ADSP FastRPC nodeNickolay Goppen
Downstream [1] ADSP FastRPC node has the adsp_mem region assigned, so assign it to the ADSP FastRPC node. [1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/arch/arm/boot/dts/qcom/sdm660.dtsi#L1693 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Nickolay Goppen <setotau@mainlining.org> Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-5-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: sdm630: describe adsp_mem region properlyNickolay Goppen
Downstream [1] this region is marked as shared, reusable and dynamic so describe it that way. [1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/arch/arm/boot/dts/qcom/sdm660.dtsi#L448 Fixes: b190fb010664 ("arm64: dts: qcom: sdm630: Add sdm630 dts file") Cc: stable@vger.kernel.org Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Nickolay Goppen <setotau@mainlining.org> Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-4-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: sdm630: set adsp compute-cbs' regs properlyNickolay Goppen
Changing FastRPC compute-cbs' reg values to matching iommu streams solves SMMU translation errors when trying to use FastRPC on ADSP so change FastRPC compute-cbs' reg values that way Fixes: af2ce7296643 ("arm64: dts: qcom: sdm630: Add FastRPC nodes to ADSP") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Signed-off-by: Nickolay Goppen <setotau@mainlining.org> Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-3-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09arm64: dts: qcom: sdm660: set cdsp compute-cbs' regs properlyNickolay Goppen
Changing FastRPC compute-cbs' reg values to matching iommu streams solves SMMU translation errors when trying to use FastRPC on CDSP so change FastRPC compute-cbs' reg values that way Fixes: c0c32a9e3493 ("arm64: dts: qcom: sdm630/660: Add CDSP-related nodes") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Signed-off-by: Nickolay Goppen <setotau@mainlining.org> Link: https://lore.kernel.org/r/20260429-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v5-2-16bc82e622ad@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09riscv: dts: spacemit: enable eMMC for OrangePi RV2Chukun Pan
The OrangePi RV2 board has one eMMC slot, so enable eMMC. Tested using a 16 GiB AJTD4R eMMC module. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260509100000.3315109-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-05-09dts: riscv: spacemit: correct 32k clock frequencyYixun Lan
The 32k oscillator's clock frequency is actually 32768Hz, so correct it. Fixes: 67072c8cd48c ("riscv: dts: spacemit: k3: add clock tree") Fixes: a6fafa64b03a ("riscv: dts: spacemit: Add clock tree for SpacemiT K1") Link: https://patch.msgid.link/20260428-06-k3-clk-osc32k-v1-1-e2378da7cb9b@kernel.org Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-05-09arm64: defconfig: Enable CIX Sky1 pinctrl, PCIe host, and Cadence GPIOPeter Chen
Enable the CIX Sky1 pinctrl driver (PINCTRL_SKY1), CIX Sky1 PCIe host controller (PCI_SKY1_HOST), and Cadence GPIO controller (GPIO_CADENCE) for the Radxa Orion O6 board which uses the CIX Sky1 SoC. The pinctrl driver is a dependency for other on-SoC peripherals. The Cadence-based PCIe host controller enables use of PCIe peripherals on the board. The Cadence GPIO controller provides GPIO support for the SoC. Cc: Yunseong Kim <ysk@kzalloc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Peter Chen <peter.chen@cixtech.com> Link: https://lore.kernel.org/r/20260327114628.3800886-1-peter.chen@cixtech.com
2026-05-08Merge tag 'x86-urgent-2026-05-09' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Ingo Molnar: - Fix memory map enumeration bug in the Xen e820 parsing code (Juergen Gross) - Re-enable e820 BIOS fallback if e820 table is empty (David Gow) * tag 'x86-urgent-2026-05-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/boot/e820: Re-enable BIOS fallback if e820 table is empty x86/xen: Fix a potential problem in xen_e820_resolve_conflicts()
2026-05-08Merge tag 'perf-urgent-2026-05-09' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull perf events fixes from Ingo Molnar: - Fix deadlock in the perf_mmap() failure path (Peter Zijlstra) - Intel ACR (Auto Counter Reload) fixes (Dapeng Mi): - Fix validation and configuration of ACR masks - Fix ACR rescheduling bug causing stale masks - Disable the PMI on ACR-enabled hardware - Enable ACR on Panther Cover uarch too * tag 'perf-urgent-2026-05-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/intel: Enable auto counter reload for DMR perf/x86/intel: Disable PMI for self-reloaded ACR events perf/x86/intel: Always reprogram ACR events to prevent stale masks perf/x86/intel: Improve validation and configuration of ACR masks perf/core: Fix deadlock in perf_mmap() failure path
2026-05-08Merge tag 'arm64-fixes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fix from Catalin Marinas: - ptrace(PTRACE_SETREGSET) fix to zero the target's fpsimd_state rather than the tracer's * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64/fpsimd: ptrace: zero target's fpsimd_state, not the tracer's
2026-05-08x86/cpuid: Introduce <asm/cpuid/leaf_types.h>Ahmed S. Darwish
To centralize all CPUID access across the x86 subsystem, introduce <asm/cpuid/leaf_types.h>. It is generated by the x86-cpuid-db project¹ and provides C99 bitfield listings for all publicly known CPUID leaves. ¹ https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.0/CHANGELOG.rst Suggested-by: Thomas Gleixner <tglx@kernel.org> Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/20260327021645.555257-1-darwi@linutronix.de
2026-05-08x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIsAhmed S. Darwish
A new CPUID model will be added where its APIs will be designated as the official CPUID API. Free the cpuid_leaf() and cpuid_subleaf() function names for that API. Rename them accordingly to cpuid_read() and cpuid_read_subleaf(). For kernel/cpuid.c, rename its local file operations read function from cpuid_read() to cpuid_read_f() so that it does not conflict with the new API. No functional change. Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/20260327021645.555257-1-darwi@linutronix.de
2026-05-08x86/cpu: Do not include the CPUID API header in asm/processor.hAhmed S. Darwish
asm/processor.h includes asm/cpuid/api.h but it does not need it. Remove the include. This allows the CPUID APIs header to include <asm/processor.h> at a later step without introducing a circular dependency. Note, all call sites which implicitly included the CPUID API through <asm/processor.h> have been modified to explicitly include the CPUID APIs instead. Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/20260327021645.555257-1-darwi@linutronix.de
2026-05-08Revert "ACPI: CPPC: Adjust debug messages in amd_set_max_freq_ratio() to warn"Mario Limonciello
Some older systems don't support CPPC in the firmware and this just makes noise for them when booting. Drop back to debug. This reverts commit 21fb59ab4b9767085f4fe1edbdbe3177fbb9ec97. Fixes: 21fb59ab4b976 ("ACPI: CPPC: Adjust debug messages in amd_set_max_freq_ratio() to warn") Suggested-by: Kim Phillips <kim.phillips@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Tested-by: Kim Phillips <kim.phillips@amd.com> Cc: All applicable <stable@vger.kernel.org> Link: https://patch.msgid.link/20260504230141.484743-2-mario.limonciello@amd.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2026-05-08x86/sev: Do not initialize SNP if missing CPUsTycho Andersen (AMD)
The SEV firmware checks that the SNP enable bit is set on each CPU during SNP initialization, and will fail if not. If there are some CPUs offline, they will not run the setup functions, so SNP initialization will always fail. Skip the IPIs in this case and return an error so that the CCP driver can skip the SNP_INIT that will fail. Also print the CPU masks in order to leave breadcrumbs so people can figure out what happened. [ bp: Massage commit message. ] Suggested-by: Borislav Petkov (AMD) <bp@alien8.de> Signed-off-by: Tycho Andersen (AMD) <tycho@kernel.org> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Nikunj A Dadhania <nikunj@amd.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://20260429155636.540040-1-tycho@kernel.org
2026-05-08arm64/entry: Fix arm64-specific rseq brokennessMark Rutland
Mathias Stearn reports that since v6.19, there are two big issues affecting rseq: (1) On arm64 specifically, rseq critical sections aren't aborted when they should be. (2) The 'cpu_id_start' field is no longer written by the kernel in all cases it used to be, including some cases where TCMalloc depends on the kernel clobbering the field. This patch fixes issue #1. This patch DOES NOT fix issue #2, which will need to be addressed by other patches. The arm64-specific brokenness is a result of commits: 2fc0e4b4126c ("rseq: Record interrupt from user space") 39a167560a61 ("rseq: Optimize event setting") The first commit failed to add a call to rseq_note_user_irq_entry() on arm64. Thus arm64 never sets rseq_event::user_irq to record that it may be necessary to abort an active rseq critical section upon return to userspace. On its own, this commit had no functional impact as the value of rseq_event::user_irq was not consumed. The second commit relied upon rseq_event::user_irq to determine whether or not to bother to perform rseq work when returning to userspace. As rseq_event::user_irq wasn't set on arm64, this work would be skipped, and consequently an active rseq critical section would not be aborted. Fix this by giving arm64 syscall-specific entry/exit paths, and performing the relevant logic in syscall and non-syscall paths, including calling rseq_note_user_irq_entry() for non-syscall entry. Currently arm64 cannot use syscall_enter_from_user_mode(), syscall_exit_to_user_mode(), and irqentry_exit_to_user_mode(), due to ordering constraints with exception masking, and risk of ABI breakage for syscall tracing/audit/etc. For the moment the entry/exit logic is left as arm64-specific, directly using enter_from_user_mode() and exit_to_user_mode(), but mirroring the generic code. I intend to follow up with refactoring/cleanup, as we did for kernel mode entry paths in commit: 041aa7a85390 ("entry: Split preemption from irqentry_exit_to_kernel_mode()") ... which will allow arm64 to use the GENERIC_IRQ_ENTRY functions directly. Fixes: 39a167560a61 ("rseq: Optimize event setting") Reported-by: Mathias Stearn <mathias@mongodb.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/regressions/CAHnCjA25b+nO2n5CeifknSKHssJpPrjnf+dtr7UgzRw4Zgu=oA@mail.gmail.com/ Link: https://patch.msgid.link/20260508142023.3268622-1-mark.rutland@arm.com
2026-05-08x86/kexec: Push kjump return address even for non-kjump kexecDavid Woodhouse
The version of purgatory code shipped by kexec-tools attempts to look above the top of its stack to find a return address for a kjump, even in a non-kjump kexec. After the commit in Fixes: the word above the stack might not be there, leading to a fault (which is at least now caught by my exception-handling code in kexec). That commit fixed things for the actual kjump path, but no longer "gratuitously" pushes the unused return address to the stack in the non-kjump path. Put that *back* in the non-kjump path, to prevent purgatory from crashing when trying to access it. Fixes: 2cacf7f23a02 ("x86/kexec: Fix stack and handling of re-entry point for ::preserve_context") Reported-by: Rohan Kakulawaram <rohanka@google.com> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> Tested-by: Rohan Kakulawaram <rohanka@google.com> Cc: <stable@kernel.org> Link: https://patch.msgid.link/32d627134143ffd957891cb697138e839c623211.camel@infradead.org
2026-05-08Merge tag 'riscv-dt-fixes-for-v7.1-rc3' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes RISC-V devicetrees fixes for v7.1-rc3 Microchip: Fix a pinctrl misconfiguration caused by a erratum fixed between engineering sample and production silicon, that causes settings for one to not apply to the other. Starfive: Remove nodes relating to the "camss" video device that has been deleted entirely from staging. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-fixes-for-v7.1-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: microchip: fix icicle i2c pinctrl configuration riscv: dts: starfive: jh7110: Drop CAMSS node Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-05-08x86/cpu, cpufreq: Remove AMD ELAN supportIngo Molnar
Now that i486 and CONFIG_MELAN support has been removed upstream: 8b793a92d862c ("x86/cpu: Remove M486/M486SX/ELAN support") the CONFIG_ELAN_CPUFREQ and CONFIG_SC520_CPUFREQ cpufreq drivers can be removed as well, as they depend on CONFIG_MELAN. Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: "Rafael J. Wysocki" <rafael@kernel.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: linux-pm@vger.kernel.org (open list:CPU FREQUENCY SCALING FRAMEWORK) Link: https://lore.kernel.org/r/20250425084216.3913608-8-mingo@kernel.org
2026-05-08x86/fpu: Remove the math-emu/ FPU emulation libraryIngo Molnar
Now that all enabling code is gone, remove the FPU emulation library as well. Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: Ahmed S. Darwish <darwi@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/20250425084216.3913608-11-mingo@kernel.org
2026-05-08x86/fpu: Remove the 'no387' boot optionIngo Molnar
Without math emulation there's no point to this option. Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: Ahmed S. Darwish <darwi@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/20250425084216.3913608-10-mingo@kernel.org
2026-05-08x86/fpu: Remove MATH_EMULATION and related glue codeIngo Molnar
Now that support for 486 CPUs is gone upstream, remove the x86 mathemu code integration. Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/20250425084216.3913608-9-mingo@kernel.org
2026-05-07riscv: cpufeature: Use pre-defined ISA ext macros to index isa2hwcapHui Wang
We have pre-defined ISA extension macros, here use those macros to replace a magic number for isa2hwcap definition and some array indexing for isa2hwcap access. This doesn't change the original functionality, just improve the code maintainability and readability. Signed-off-by: Hui Wang <hui.wang@canonical.com> Link: https://patch.msgid.link/20260506132152.53239-1-hui.wang@canonical.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-05-07arm64: dts: qcom: sc7180: Add QSPI memory interconnect pathViken Dadhaniya
Add the missing QSPI-to-memory interconnect path alongside the existing configuration path. Without this path, the interconnect framework cannot correctly vote for the bandwidth required by QSPI DMA data transfers. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260429-spi-nor-v5-7-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-07arm64: dts: qcom: kodiak: Add QSPI memory interconnect pathViken Dadhaniya
Add the missing QSPI-to-memory interconnect path alongside the existing configuration path. Without it, the interconnect framework cannot vote for the bandwidth required by QSPI DMA data transfers. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260429-spi-nor-v5-6-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-07arm64: dts: qcom: qcs615-ride: Enable QSPI and NOR flashViken Dadhaniya
The QCS615 Ride board has a SPI-NOR flash connected to the QSPI controller on CS0. Enable the QSPI controller and add the corresponding SPI-NOR flash node to allow the system to access it. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260429-spi-nor-v5-5-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-07arm64: dts: qcom: talos: Add QSPI supportViken Dadhaniya
The Talos (QCS615) platform includes a QSPI controller used for accessing external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and the QSPI controller node to enable support for this hardware. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260429-spi-nor-v5-4-993016c9711e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-07arm64: dts: qcom: glymur: Add crypto engine and BAMHarshal Dev
On almost all Qualcomm platforms, including Glymur, there is a Crypto engine IP block to which the CPU can off-load cryptographic computations for achieving acceleration. The engine is also DMA capable due to the presence of an associated Bus Access Manager (BAM) module. Describe the Crypto engine and its BAM. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260505-glymur_crypto_enablement-v2-2-bf115aeb1459@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-07arm64: dts: qcom: milos: Add QCrypto nodesAlexander Koskovich
Add the QCE and Crypto BAM DMA nodes. Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260405-milos-qce-v1-2-6996fb0b8a9c@pm.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-20 02:10:36 +0000