summaryrefslogtreecommitdiff
path: root/drivers/gpu
AgeCommit message (Collapse)Author
2026-08-25drm/amdgpu: add ext_umc_mask to RAS TA initCandice Li
Add ext_umc_mask for the upper half of adev->umc.active_mask and fill both fields when building RAS TA init message. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: update UMC active_mask to u64Candice Li
amdgpu_umc.active_mask is widened to u64 to match 64-bit harvest masks and avoid LP32 unsigned long width limits. Fix UMC harvest bitmask (drop le16 on u8, use 1ULL shift). Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: load TA firmware for psp v15_0_8Candice Li
Register psp_15_0_8_ta.bin with MODULE_FIRMWARE and load TA for psp v15_0_8. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: load standalone RL firmware on psp v15_0_8Candice Li
Add psp_init_rl_microcode() to request amdgpu/%s_rl.bin and populate psp->rl using the existing v1.0 PSP firmware header parsing. Wire it up for psp v15_0_8. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: factor PSP v1.0 firmware bin descriptor parsingCandice Li
Add parse_psp_v1_bin_descriptor to populate struct psp_bin_desc from psp_firmware_header_v1_0, shared by ASD, TOC and CAP standalone firmware loads. Use psp-> fields directly instead of adev->psp. v2: code rebase v3: Rename v1 header helper to parse_psp_v1_bin_descriptor, have it return an error code with explicit NULL checks. Rename sos v2 helper to parse_psp_v2_bin_descriptor for symmetry. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Remove unused function interfacesYiPeng Chai
Remove unused function interfaces. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Support obtaining ras capabilitiesYiPeng Chai
Support obtaining ras capabilities. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Handle ras interrupts using unified interfaceYiPeng Chai
Handle ras interrupts using unified interface. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Support poison consumption handling for A + A sriov guestYiPeng Chai
Support poison consumption handling for A + A sriov guest. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Add ras command to obtain ras capabilitiesYiPeng Chai
Add ras command to obtain ras capabilities. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Support querying RAS driver capabilitiesYiPeng Chai
Support querying RAS driver capabilities: 1. Generate ras block bitmask for HW. -- Read ras hw capabilities from registers. -- Convert hw ras block bitmask to driver ras block bitmask. 2. Generate ras block bitmask for SW. 3. Add interfaces to query RAS capabilities. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Add ras block id mappingYiPeng Chai
Some ASICs have different hw ras block IDs. In order to be compatible with these ASICs, it is necessary to map these hw RAS block IDs to unified RAS block IDs. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Add ras_psp v15_0 for A + AYiPeng Chai
Add ras_psp v15_0 for A + A. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Add ras ip configuration for A + AYiPeng Chai
Add ras ip configuration for A + A. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Handling ras mce notification eventYiPeng Chai
Handling ras mce notification event. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Add mce ras error typeYiPeng Chai
Add new ras error type so that ACA parser can parse ras data from mce. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Add fifo to cache ras data from mce notificationYiPeng Chai
Add fifo to cache ras data from mce notification. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Add aca parser v5_0YiPeng Chai
Add aca parser v5_0. V2: Support new mappings for hwip and hwid. V3: Change aca ip version. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: add common interface to query ras subunit versionYiPeng Chai
Add common interface to query ras subunit version. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Change variable name to avoid confusionYiPeng Chai
Change variable name to avoid confusion. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Improve function interface to record different types of dataYiPeng Chai
Improve function interface to record different types of data. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Supports recording data source timestamps to EEPROMYiPeng Chai
Supports recording data source timestamps to EEPROM. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Optimize and remove redundant codeYiPeng Chai
Optimize and remove redundant code. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: support separate logging of gfx aid and xcd errorsYiPeng Chai
Support separate logging of gfx aid and xcd errors. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: optimize mp1 dump bank interfaceYiPeng Chai
Optimize mp1 dump bank interface. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Add dedicated interface to obtain cper infoYiPeng Chai
Add dedicated interface to obtain cper info. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Add interface to get ras eeprom table versionYiPeng Chai
Add interface to get ras eeprom table version. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Introduce BOOT CPER encoding functionXiang Liu
Introduce new fields for BOOT CPER encoding, only important fields are introduced here due to the cache size limit. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Parse error type of MCE and encode CPERYiPeng Chai
Introduce MCE type ras log event. Parse error type of MCE and encode to corresponding CPER. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: add interface to support parsing aca bank ecc infoYiPeng Chai
Add interface to support parsing aca bank ecc info. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: register mce notifier to obtain ras error infoXiang Liu
Register mce notifier to obtain ras error info for A + A. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Replace deprecated strcpy with strscpyAmin Gattout
strcpy() has been deprecated because it performs no bounds checking on the destination buffer, which can lead to buffer overflows. Replace it with the safer strscpy(). No functional changes. Signed-off-by: Amin Gattout <amin.gattout@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Remove is_idleDr. David Alan Gilbert
Remove the actual is_idle member, since it's never read/called and the previous patches have remove all the assignments. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Remove is_idle (non trivial functions)Dr. David Alan Gilbert
The is_idle method on amd_ip_funcs is never called. Remove the implementations that actually do something. In most cases the same code has been duplicated in the wait_for_idle method implementations that is still used. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Remove is_idle (trivial cases)Dr. David Alan Gilbert
The is_idle method on amd_ip_funcs is never called. Remove the trivial cases where either: a) It's just a return true function that can be deleted together with the .is_init = b) The function is called somewhere else, so we just remove the assignment. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Remove is_idle test caseDr. David Alan Gilbert
Remove the kunit test case for the is_idle call we're about to remove. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Fix spelling mistake "optmization" -> "optimization"Colin Ian King
There is a spelling mistake in a DML_ASSERT_MSG message. Fix it. v2: squash in additional spelling mistake (resul -> result) Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Rename CPER section descriptor structXiang Liu
Rename CPER section descriptor struct to avoid conflicting with UEFI definition. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: Add ras notification eventYiPeng Chai
Add ras notification event. v2: Change event id name. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Promote DC to 3.2.394Taimur Hassan
This DC patchset brings improvements in multiple areas. In summary, we have: * Reworked per-DPM derate handling: refactor the per-DPM derate logic, update derates with default per-DPM values, and move the soc_and_ip_translator onto the new per-DPM organization * DCN6 mode-support and UTM work: opt-out for the OutstandingRequests check, a utm_support capability flag, and a guard against an empty DCN6 UTM QoS table * More DMU/DMUB offload: send DPM0 clock values for Z8 retention, allow DCHVM<->rIOMMU SDP port disconnection on DCN42, and add the DC_BLS command * HWSS block-sequence cleanups: move periodic interrupt calculations to HWSS, drop pipe_ctx from HUBP_WAIT_FOR_DCC_META_PROP, use mpcc_id instead of the hubp instance, and add a wait stream regen event * DML updates: unify CalculateFlipSchedule logic and relax the frame size limit for the dcn5/6 core funcs files * clk_mgr refactor renaming carried DCE clock manager functions for dcn10, plus a missing-prototype build fix and a static DCN42 SOC BB struct * Expanded IGT/KUnit validation: CACP ACE curve area debugfs and cursor mode tests on disabled CRTCs * eDP fix to skip teardown while a forced PSR is active Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: [FW Promotion] Release 0.1.71.0Taimur Hassan
[why & how] update DMUB_CMD__DC_BLS_DCHVM_INIT definitions Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Update soc_and_ip_translator To Use Updated Per-DPM Derate ↵Austin Zheng
Organization [Why/How] Transitioning to use the new per-DPM fields so the old ones can be deprecated. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Skip eDP teardown while forced PSR is activeKarthi Kandasamy
[Why & How] During the HDR<->SDR toggle when the eDP link is held in a forced PSR (freeze) state, the normal stream/link teardown re-programming the panel would blank the frozen frame and disrupt the freeze; to prevent this, gate the eDP teardown path, keeping the link and PSR/Replay state intact for the duration of the forced PSR hold. The blank_stream and disable_link_output gates already exist. Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Unify CalculateFlipSchedule LogicAustin Zheng
[Why] CalculateFlipSchedule has slightly different calculations depending on if it was called by mode support or mode programming. Mode support calculates the lower bound of the required bandwidth for immediate flips. This takes into the account of the register limits to ensure it is still programmable. Mode programming uses the required bandwidth for immediate flips on a per-plane basis to calculate the number of dst_y lines needed to achieve this bandwidth. Usually the immediate flip bandwidth per plane determined by mode programming is above the lower bound calculated by mode support. However, mode programming can fail if that isn't the case since a bandwidth lower than the lower bound will end up exceeding the register limit used by hardware. e.g. The proportion of a single plane's flip bandwidth w.r.t to the total bandwidth available for all planes can result in one of the planes having a lower BW than the lower bound calculated in mode support [How] Update function to always use the use_lb_flip_bw path. Add calculations for dst_y_per_vm/row_flip lines. Consolidate calculation of lb_flip_bw by having it consider register limits: Instead of doing two steps of: 1. Taking the max of the bandwidths without considering register limits. 2. Taking the max of itself with the bandwidths with register limits accounted for. Do it in one step as it is easy to miss either step 1 or 2. Also add some local variables for intermediate values and remove no longer referenced inputs to improve readability. Also increase DCN401 max_flip_time_lines by 2 lines to ensure previously supported configs remain supported as worst-case bandwidth can increase compared to before. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Update Derates And Set Default Per-DPM DeratesAustin Zheng
[Why/How] Adjusted derates to allow DPM0 to be used on certain display configs. For DCN42, MALL derates are not relevant so they can be modified to prevent DPMM from rounding up to the next DPM level. Also set the default DPM0 derates that can be used. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Refactor Per-DPM Derate LogicAustin Zheng
[Why/How] 1. DPMM also needs to consider the per-DPM derate when calculating the clocks that will be used by mode programming. Otherwise DPMM calculations can result in rounding up to the next DPM anyways. clk index value used by mode support is not reliable when trying to determine the actual per-dpm derate. 2. Also update how per-dpm derates are stored so each derate applies until an upper bound. Upperbound of 0 signifies this derate is used for the remaining DPMs. To simplify logic, all derates for all clocks should have the same number of entries and the last entry should have an upperbound of 0. 3. Deprecate system_active_average derates from the derate table and move them to the per-DPM structure The remaining derates (urgent, dcn_mall, system idle) are unchanged Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Make Struct In DCN42 SOC BB Header StaticAustin Zheng
[Why/How] Make dcn42_ddr5_power_management_parameters struct static to avoid having multiple declarations of the structure Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Add opt-out for DCN6 OutstandingRequests mode-support checkJun Lei
The OutstandingRequestsSupport check fails a mode when the outstanding-request buffer window (max_outstanding_reqs * request_size / (DCFCLK * return_bus_width)) is shorter than the average urgent request latency. Because DCFCLK is derived from the SOP's bandwidth, a higher-bandwidth SOP raises DCFCLK, shrinks that window, and perversely makes the mode unsupported - so "too much bandwidth" becomes a failure reason, which defies common sense. When the ROB size / request limit is not yet fixed, the SOP bandwidth/latency values are tuned to a family maximum and the check mis-fires. Add a per-display-config override outstanding_requests_check_disable (overrides.hw, matching the existing *_check_disable idiom) that early-outs the dcn6 check with both flags left supported. Default off, so existing behavior is unchanged. Also wire the flag through the DML JSON translation. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Jun Lei <Jun.Lei@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Use mpcc_id instead of hubp instanceTomasz Siemek
[why] Hubp pointer is not initialized for older asics. [how] Use mpcc_id field from plane resources instead of instance number by dereferencing hupb pointer. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: add wait stream regen eventPeichen Huang
[WHY & HOW] Add event to wait stream regen flag. Reviewed-by: Leon Huang <leon.huang1@amd.com> Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-20 23:52:52 +0000