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2026-06-09drm/amd/display: Remove unnecessary SIGNAL_TYPE_HDMI_TYPE_A checkWerner Sembach
Remove unnecessary SIGNAL_TYPE_HDMI_TYPE_A check that was performed in the drm_mode_is_420_only() case, but not in the drm_mode_is_420_also() && force_yuv420_output case. Without further knowledge if YCbCr 4:2:0 is supported outside of HDMI, there is no reason to use RGB when the display reports drm_mode_is_420_only() even on a non HDMI connection. This patch also moves both checks in the same if-case. This eliminates an extra else-if-case. Signed-off-by: Werner Sembach <wse@tuxedocomputers.com> Signed-off-by: Andri Yngvason <andri@yngvason.is> Tested-by: Andri Yngvason <andri@yngvason.is> Reviewed-by: Daniel Stone <daniel@fooishbar.org> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://patch.msgid.link/20260609-color-format-v17-1-35739b5782cc@collabora.com Signed-off-by: Daniel Stone <daniels@collabora.com>
2026-06-09drm/vc4: fix krealloc() memory leakAlexander A. Klimov
Don't just overwrite the original pointer passed to krealloc() with its return value without checking latter: MEM = krealloc(MEM, SZ, GFP); If krealloc() returns NULL, that erases the pointer to the still allocated memory, hence leaks this memory. Instead, use a temporary variable, check it's not NULL and only then assign it to the original pointer: TMP = krealloc(MEM, SZ, GFP); if (!TMP) return; MEM = TMP; While on it, use krealloc_array(). Fixes: 6d45c81d229d ("drm/vc4: Add support for branching in shader validation.") Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Maíra Canal <mcanal@igalia.com> Link: https://patch.msgid.link/20260606123817.37222-1-grandmaster@al2klimov.de
2026-06-09drm/xe: drop unused xe_exec_queue_ops::active callbackTangudu Tilak Tirumalesh
send_tlb_inval_ctx_ppgtt() was the only caller of q->ops->active(q). The per-VM exec_queue list is now walked unfiltered. With no remaining callers, drop the .active op from struct xe_exec_queue_ops along with the GuC and execlist backend implementations (guc_exec_queue_active() and execlist_exec_queue_active()). Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Link: https://patch.msgid.link/20260608162745.338725-3-tilak.tirumalesh.tangudu@intel.com Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com>
2026-06-09drm/xe: include all registered queues in TLB invalidationTangudu Tilak Tirumalesh
Context-based TLB invalidation currently selects only scheduling-active exec queues via q->ops->active(). During rebind flows, queues may be suspended (or transitioning through resume) while still owning valid translations, causing them to be skipped from invalidation and leading to missed TLB invalidations on LR rebinds. The underlying issue is a TOCTOU: q->guc->state bits are flipped lock-free from enable_scheduling(), disable_scheduling{,_deregister}(), the suspend/resume sched-msg handlers, handle_sched_done(), and guc_exec_queue_stop(); nothing in send_tlb_inval_ctx_ppgtt() serializes against them, so any state-based predicate can race. Include all the registered queues so that TLB invalidations are not missed. This is race-free because list membership on vm->exec_queues.list is stable under vm->exec_queues.lock held by the caller. The performance impact is expected to be minimal and harmless. If it does turn out to be a concern, we can come back with a race-safe solution to ignore certain queues. Fixes: 6cdaa5346d6f ("drm/xe: Add context-based invalidation to GuC TLB invalidation backend") Assisted-by: Claude:claude-opus-4.6 Suggested-by: Thomas Hellstrom <thomas.hellstrom@linux.intel.com> Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260608162745.338725-2-tilak.tirumalesh.tangudu@intel.com Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com>
2026-06-09drm/v3d: Deprecate V3D 3.3 and 4.1 supportMaíra Canal
V3D 3.3 (Broadcom BCM7268) and V3D 4.1 (Broadcom BCM7278) has had no in-tree userspace since Mesa dropped support in 2024, on the grounds that those generations were no longer being tested. The situation in the kernel is similar: the maintainers don't have this hardware, the hardware is not available for purchase, and there is no known user of these GPUs. With no userspace left to drive it and no known users, maintaining the ver <= 41 code paths is a cost without a benefit, considering that these paths are not being exercised on real hardware. As a first step toward removal, emit a deprecation warning at probe for V3D versions earlier than or equal to 4.1. The hardware remains functional for now; this only warns. If any real user appears and explain its use-case, support can be retained. Schedule the removal of V3D 3.3 and 4.1 support to the next kernel release. Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25851 Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Link: https://patch.msgid.link/20260606185616.694188-2-mcanal@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/i915/bw: Simplify the best max_data_rate searchVille Syrjälä
For some reason we're tracking the best max_data_rate as the difference between the required data_rate and max_data_rate. That's pointlessly complicated as we're just looking for the minimum max_data_rate that is greater or equal to data_rate. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260528103458.18069-12-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-06-09drm/i915/bw: Use icl_qgv_bw()Ville Syrjälä
Replace a hand rolled copy of icl_qgv_bw() with the real thing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260528103458.18069-11-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-06-09drm/i915/bw: Print derated bandwidth numbers for DG2Ville Syrjälä
While DG2 is using hardcoded numbers for the memory bandwidth stuff, let's still print them to aid in debugging as there are two different SKUs to consider with different bandwidth numbers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260528103458.18069-10-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-06-09drm/i915/bw: Move peakbw[] out from the plane groupVille Syrjälä
The peak bandwidth doesn't depend on the number of planes, so there is no need to repeat the same information for each plane group. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260528103458.18069-9-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-06-09drm/i915/bw: Move psf_bw[] out from the plane groupVille Syrjälä
The PSF bandwidth doesn't depend on the number of planes, so there is no need to repeat the same information for each plane group. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260528103458.18069-8-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-06-09drm/i915/bw: Move num_{qgv,psf}_points out from the plane groupVille Syrjälä
We only have a single num_{qgv,psf}_points value, there is no need to replicate it in each plane group. And drop the somewhat misplaced comments about pcode behaviour from {icl,tgl}_max_bw_index() while at it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260528103458.18069-7-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-06-09drn/i915/bw: s/num_points/num_qgv_points/Ville Syrjälä
Rename 'num_points' to 'num_qgv_points' to make it a bit more specific. We already have the 'num_psf_points' counterpart. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260528103458.18069-6-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-06-09drm/i915/bw: Move 'bi_next' to tighter scopeVille Syrjälä
Move 'bi_next' into the scope where it's actually used. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260528103458.18069-5-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapilai@intel.com>
2026-06-09drm/i915/bw: Initialize num_planes sensibly for the first plane group in TGL+Ville Syrjälä
The way the TGL+ bw algorithm works is that 'num_planes' is really a maximum number of allowed planes (whereas in the ICL version it was more of a minimum), and the assumption is that the first plane group (max[0]) can be used with any number of planes (tgl_max_bw_index() always returns 0 at the end). To make things a bit less weird let's just set the first plane group's num_planes to some big number to indicate it has no real limit on the number of planes. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260528103458.18069-4-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-06-09drm/i915/bw: Streamline dg2_get_bw_info()Ville Syrjälä
Make dg2_get_bw_info() look a bit more like xe2_hpd_get_bw_info() so that we don't have so many different ways of writing the same stuff (namely the "set all plane groups to the same value" part). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260528103458.18069-3-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-06-09drm/i915/bw: Don't memcpy() pointlesslyVille Syrjälä
Structs can be copied with a simple assingment. Eliminate the pointless memcpy(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260528103458.18069-2-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-06-09drm/v3d: Ensure atomic submissions in v3d_submit_jobs()Maíra Canal
Currently, v3d_submit_jobs() arms and pushes each job one at a time, wiring dependencies between consecutive jobs after each push. If drm_sched_job_add_dependency() fails midway, the already-pushed jobs are scheduler-owned and will be submitted to the GPU for execution, even though the subsequent jobs won't be submitted. This breaks the atomicity of the submissions, as only some of the jobs from a submission would be submitted to the hardware, while the other part fails. Restructure v3d_submit_jobs() into three phases: (1) arm all jobs belonging to a given submission, (2) wire inter-job dependencies, and (3) push all jobs to the scheduler unconditionally. Phase (2) can fail; on failure, it marks every armed job finished fence with an error, so that run_job() callbacks skip hardware execution. This guarantees that every armed job is always pushed, either to run or to be skipped, and it also ensures the atomicity of a submission. Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-12-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/v3d: Reject invalid out_sync handles in submit ioctlsMaíra Canal
v3d_submit_process_post_deps() looks up the out_sync syncobj via drm_syncobj_find(), and if userspace passes a non-zero handle that doesn't refer to a valid syncobj, the lookup silently returns NULL and the post-deps step skips publishing the submission's last fence to it. The ioctl still returns success, leaving userspace to wait on a invalid syncobj. Instead of silently ignoring an invalid non-zero out_sync, move the syncobj lookup to the submission and make it fail with -ENOENT up front, mirroring the syncobj validation already done for in_sync. Now, v3d_submit_process_post_deps() only does the fence replacement. Note that the lookup is skipped when the multi-sync extension is in use, since args->out_sync is unused in that case. To keep cleanup symmetric on error paths, convert the function v3d_put_multisync_post_deps() into a single function that releases the references that were acquired but never published for both single-sync and multi-sync. Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-11-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/v3d: Split BO fence attach from syncobj output handlingMaíra Canal
v3d_attach_fences_and_unlock_reservation() does three different things: (1) attaches the submission's last fence to every BO, (2) releases drm_exec, and (3) replaces the userspace out_sync syncobjs. Decouple these three behaviors into different functions, so that each function has a more self-contained behavior. v3d_submit_jobs() now invokes the three steps explicitly, which makes the submission sequence self-documenting and keeps each helper self-contained. No functional change; just code consolidation. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-10-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/v3d: Refactor CPU ioctl into unified submission chainMaíra Canal
Restructure the CPU ioctl so that all job types, including indirect CSD, use a single struct v3d_submit chain and a single DRM exec context. Now that v3d_get_cpu_indirect_csd_params() is a pure parser and the submit helpers operate on struct v3d_submit, fold the indirect CSD path into the standard flow by appending the CSD and CLEAN_CACHE jobs to the same struct v3d_submit as the CPU job and locking the union of all jobs' BOs under one drm_exec. This eliminates the second drm_exec, the nested submission, and the conditional two-pass fence attachment that the CPU ioctl previously required for the indirect CSD path. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-9-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/v3d: Convert submit helpers to operate on struct v3d_submitMaíra Canal
Generalize the submission helpers so they act on a whole struct v3d_submit (the entire job chain) rather than on individual jobs and a drm_exec. This lets a submission of several chained jobs be locked, fenced, and finalized as a single unit, and is the groundwork for collapsing the indirect CSD path into one chain. The following helpers were generalized: - v3d_lookup_bos() - v3d_lock_bo_reservations() (renamed to v3d_submit_lock_reservations()): - v3d_attach_fences_and_unlock_reservation() - v3d_setup_csd_jobs_and_bos() Now, the locking helper now iterates over all jobs and locks the union of their BOs under one DRM exec, using DRM_EXEC_IGNORE_DUPLICATES to tolerate shared BO references. The fence-attach helper similarly walks every job and attaches the chain's last fence to all touched BOs. Also, v3d_submit_jobs() becomes the single submit-and-finalize entry point and callers no longer need to open-code fence attachment, reservation unlocking, etc. Update CL/TFU/CSD/CPU ioctls to use the new helper signatures. The CPU ioctl still uses two struct v3d_submit instances (one for the CPU job, one for the indirect CSD jobs) and keeps its manual two-pass fence-attach flow. Converting the indirect CSD path into the unified chain is done in the next commit. No functional change. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-8-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/v3d: Make v3d_get_cpu_indirect_csd_params() a pure parserMaíra Canal
v3d_get_cpu_indirect_csd_params() currently does double duty: it parses the indirect CSD extension and, while still inside the extension parser, also creates the CSD/clean jobs and locks their BOs through a separate DRM exec context. This nested submission deviates from the standard flow and makes it hard to fold the indirect CSD path into the unified submit chain. Stash the parsed drm_v3d_submit_csd args in struct v3d_indirect_csd_info and have the parser only fill in the parameters. Then, move job creation (v3d_setup_csd_jobs_and_bos()) into v3d_submit_cpu_ioctl(), where is the proper place to create jobs. No functional change, but prepares to move the CPU ioctl into the unified submission chain. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-7-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/v3d: Introduce struct v3d_submit and convert CL/TFU/CSD ioctlsMaíra Canal
As the V3D driver grew with time, different types of submission were added and the submission code grew more complex, but the driver stuck with the same abstractions. Nowadays, the submission ioctls don't submit a single job, but a chain of jobs: 1. v3d_submit_cl_ioctl() submits a BIN job (optional), RENDER job (mandatory), and a CLEAN_CACHE job (optional). 2. v3d_submit_csd_ioctl() submits a CSD, and a CLEAN_CACHE job. 3. v3d_submit_tfu_ioctl() submits a TFU job. Therefore, each ioctl submits a chain of jobs in which each job depends on the previous one. However, this concept is not well represented in software at the moment. To address this, introduce a new concept: the struct v3d_submit, which groups the submission state and represents the submission chain formed by an ordered array of jobs. Add new helpers to allocate, add jobs to the chain and submit jobs to the scheduler, all based on the new struct. Convert v3d_submit_cl_ioctl(), v3d_submit_tfu_ioctl() and v3d_submit_csd_ioctl() to the new pattern. Each ioctl now follows the same flow: add jobs -> attach perfmon -> lookup BOs -> lock reservations -> submit chain -> attach fences -> put jobs. The CPU ioctl is left on the old helpers for now; its indirect CSD path requires some restructuring that will be addressed in the next few commits. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-6-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/v3d: Migrate BO reservation locking to DRM execMaíra Canal
Replace the drm_gem_(un)lock_reservations() + ww_acquire_ctx pattern with DRM exec across all submit ioctls. Just a straightforward conversion; no functional change. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-5-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/v3d: Reject invalid syncobj handles in submit ioctlsMaíra Canal
drm_sched_job_add_syncobj_dependency() returns -ENOENT both when the handle is zero and when the handle is non-zero but does not find a corresponding existing syncobj (userspace bug). The driver previously ignored -ENOENT in both cases, silently accepting broken handles. Distinguish the two: skip the call entirely when the handle is zero, as there is no dependency, and let -ENOENT propagate for non-zero handles that don't resolve, turning the error into a proper return to userspace. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-4-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/v3d: Extract v3d_job_add_syncobjs() helperMaíra Canal
Move the syncobj dependency setup out of v3d_job_init() into its own v3d_job_add_syncobjs() helper and make the queue that the job was submitted a variable in struct v3d_job, so that v3d_job_add_syncobjs() can use it. No functional change. This prepares for the next commit which changes the error handling, and for a later consolidation that separates job allocation from syncobj attachment. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-3-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/v3d: Clear queue->active_job when v3d_fence_create() failsMaíra Canal
The run_job() callbacks for BIN, RENDER, TFU and CSD assign the incoming job to queue->active_job before calling v3d_fence_create(). If v3d_fence_create() fails, the callback returns NULL without clearing active_job, leaving a dangling pointer. Create a failure path in all run_job() callbacks that clears the active job before returning NULL. The BIN path takes queue->queue_lock around the clear as it races against v3d_overflow_mem_work(); RENDER, TFU and CSD paths have no concurrent reader, so the clear is lock-free. Fixes: a783a09ee76d ("drm/v3d: Refactor job management.") Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-2-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/v3d: Drop unused drm_encoder.h include from v3d_drv.hMaíra Canal
The V3D driver has no display pipeline, so nothing in the driver requires drm_encoder.h. Remove the stale include. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Link: https://patch.msgid.link/20260604-v3d-sched-misc-fixes-v4-1-c068f5bf5ccf@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-06-09drm/xe/hw_error: Use HW_ERR prefix in logRaag Jadav
Hardware errors should be logged with HW_ERR prefix. Make them consistent with existing logs. Fixes: 01aab7e1c9d4 ("drm/xe/xe_hw_error: Add support for PVC SoC errors") Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Link: https://patch.msgid.link/20260602044919.702209-5-raag.jadav@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-06-09drm/xe/drm_ras: Add per node cleanup actionRaag Jadav
cleanup_node_param() is not registered for previous node in case of counter allocation failure, which results in stale memory of previous node that isn't cleaned up on unwind. Add per node cleanup action which guarantees cleanup on unwind and also simplifies the cleanup logic. Fixes: b40db12b542f ("drm/xe/xe_drm_ras: Add support for XE DRM RAS") Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Link: https://patch.msgid.link/20260602044919.702209-4-raag.jadav@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-06-09drm/xe/drm_ras: Make counter allocation drm managedRaag Jadav
cleanup_node_param() is not registered for previous node in case of counter allocation failure, which results in stale memory of previous node that isn't cleaned up on unwind. Fix this using drm managed allocation, which is guaranteed to be cleaned up on unwind. Fixes: b40db12b542f ("drm/xe/xe_drm_ras: Add support for XE DRM RAS") Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Link: https://patch.msgid.link/20260602044919.702209-3-raag.jadav@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-06-09drm/i915/de: Remove the 2 usec fast timeoutVille Syrjälä
Currently any "slow" wait will first try a "fast" wait with a 2 usec timeout, and then fall back to whatever timeout was specified originally. The "slow" wait will anyway start off with a mere 10 usec polling interval, so basically we can only save 8 usec with the "fast" wait (maybe a bit more given hrtimer setup costs etc.). I don't think we really do any operations in the display code where that kinds of 8 usec saving would be meaningful. So just get rid of the whole "fast" wait complication and go straight for the "slow" wait. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260529161147.17573-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2026-06-09Merge tag 'tegra-for-7.2-pmc' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers soc/tegra: pmc: Changes for v7.2-rc1 The bulk of these changes converts existing users to the modern variants of the API that take a PMC instance as argument. This completes the transition to multi-instance support, which then makes room for cleanups and restricting the remaining legacy APIs to 32-bit platforms. Some changes in this set also clean up powergate debugfs and restrict the power-off handler to be installed only where appropriate. Lastly, support for Tegra238 is added. * tag 'tegra-for-7.2-pmc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Add Tegra238 support soc/tegra: pmc: Restrict power-off handler to Nexus 7 soc/tegra: pmc: Populate powergate debugfs only when needed soc/tegra: pmc: Move legacy code behind CONFIG_ARM guard soc/tegra: pmc: Remove unused legacy functions soc/tegra: pmc: Create PMC context dynamically usb: xhci: tegra: Explicitly specify PMC instance to use PCI: tegra: Explicitly specify PMC instance to use media: vde: Explicitly specify PMC instance to use drm/tegra: Explicitly specify PMC instance to use drm/nouveau: tegra: Explicitly specify PMC instance to use ata: ahci_tegra: Explicitly specify PMC instance to use Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-06-09fbdev: Wrap fbcon updates from vga-switcheroo in helperThomas Zimmermann
Handle console remapping in fbcon in fb_switch_output(). Vga-switcheroo invokes this functionality before switching physical outputs to a new graphics device. Open-coding fbcon state in vga-switcheroo exposed fbdev implementation details. Vga-switcheroo is used for switching physical outputs among graphics hardware. This functionality is only supported by DRM drivers. A later update will further move fb_switch_output() into DRM's fbdev emulation; thus fully decoupling vga-switcheroo from fbdev. v3: - remove Kconfig dependency related to fbcon (Geert) v2: - use '#if defined' (Helge) Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Helge Deller <deller@gmx.de>
2026-06-09gpu: nova-core: gsp: tu102: keep unloading if FWSEC-SB failsAlexandre Courbot
On Turing and Ampere, resetting the GSP involves running two firmware images: FWSEC-SB and Booter Unloader. They are independent from one another, and we should do whatever is possible to restore the GSP's unloaded state even if a failure occurs along the way. Thus, keep going and run Booter Unloader even if the execution of FWSEC-SB failed. Fixes: adb99ce3cc78 ("gpu: nova-core: run Booter Unloader and FWSEC-SB upon unbinding") Reported-by: Sashiko <sashiko-bot@kernel.org> Closes: https://sashiko.dev/#/patchset/20260529-nova-unload-v7-0-678f39209e00%40nvidia.com?part=3 Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260531-nova-unload-fix-v1-1-c8dcdc769b53@nvidia.com [acourbot: log Booter Unloader errors.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-06-09drm/virtio: Fix driver removal with disabled KMSDmitry Osipenko
DRM atomic and modesetting aren't initialized if virtio-gpu driver built with disabled KMS, leading to access of uninitialized data on driver removal/unbinding and crashing kernel. Fix it by skipping shutting down atomic core with unavailable KMS. Fixes: 72122c69d717 ("drm/virtio: Add option to disable KMS support") Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Tested-by: Ryosuke Yasuoka <ryasuoka@redhat.com> Reviewed-by: Ryosuke Yasuoka <ryasuoka@redhat.com> Link: https://patch.msgid.link/20260604122743.13383-1-dmitry.osipenko@collabora.com
2026-06-09drm/sched: Fix spelling mistake "sumission" -> "submission"Colin Ian King
There is a spelling mistake in a pr_info message. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Philipp Stanner <phasta@kernel.org> Link: https://patch.msgid.link/20260608172315.34626-1-colin.i.king@gmail.com
2026-06-09drm/i915/edp: Check supported link rates DPCD readNikita Zhandarovich
intel_edp_set_sink_rates() reads DP_SUPPORTED_LINK_RATES into a local stack array and then parses the array unconditionally. If the read fails, the array contents are not valid and may result in bogus sink link rates being used. Use drm_dp_dpcd_read_data() and clear the sink rate array on failure, so the existing parser falls back to the default sink rate handling. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 68f357cb7347 ("drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4") Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260529145759.1640646-1-n.zhandarovich@fintech.ru Signed-off-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit bd61c7756b34157e093028225a69383b4b1203cc) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-06-09gpu: nova-core: don't declare booter firmware for FSP chipsetsJohn Hubbard
The module firmware table lists booter_load and booter_unload for every chipset, but Hopper and Blackwell boot the GSP through FSP and never load the SEC2 booter. Those modinfo entries point at firmware files that are not shipped for FSP-based chipsets, so initramfs tooling looks for images that are never used. Declare the booter only for chipsets that boot via it, matching how the FMC and FWSEC bootloader images are already gated on chipset capabilities. Signed-off-by: John Hubbard <jhubbard@nvidia.com> Reviewed-by: Danilo Krummrich <dakr@kernel.org> Reviewed-by: Timur Tabi <ttabi@nvidia.com> Link: https://patch.msgid.link/20260607230539.144382-1-jhubbard@nvidia.com [acourbot: make comment on FMC/Booter choice a bit more precise.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-06-09gpu: nova-core: return FSP response buffer to callerZhi Wang
Change send_sync_fsp() to return the raw response buffer after validating the common MCTP/NVDM headers and error code. This allows callers to perform protocol-specific parsing on the response payload, which is needed for the upcoming PRC protocol support. For the existing COT caller, the response buffer is unused. Signed-off-by: Zhi Wang <zhiw@nvidia.com> Link: https://patch.msgid.link/20260604114339.1565660-4-zhiw@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-06-09gpu: nova-core: factor out common FSP message headerZhi Wang
Extract common MCTP + NVDM headers into FspMessageHeader, rename FspMessage to FspCotMessage, and update FspResponse to use the shared header. This prepares for adding new FSP message types. Signed-off-by: Zhi Wang <zhiw@nvidia.com> Link: https://patch.msgid.link/20260604114339.1565660-3-zhiw@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-06-09Merge tag 'drm-misc-next-fixes-2026-06-05' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next-fixes for v7.2-rc1: - Revert last minute IS_ERR_OR_NULL changes in nouveau/gsp. - Fix build warning in drm scheduler. - Flush caches and TLB before v3d runtime suspend. - Fix a trace and debug command in amdxdna. - Fix heap buffer address validation when PASID is disabled in amdxdna. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patch.msgid.link/a4a5bf50-3fc8-4faf-884b-08121687124a@linux.intel.com
2026-06-09gpu: nova-core: firmware: parse `FalconUCodeDescV2` via `zerocopy`Miguel Ojeda
Now that we have `zerocopy` support, we can avoid some `unsafe` code. For instance, for `FalconUCodeDescV2`, we can replace the `unsafe impl FromBytes` by safely deriving `zerocopy`'s `FromBytes` and then calling `read_from_prefix`. Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260608141439.182634-20-ojeda@kernel.org Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
2026-06-08drm/xe: improve Kconfig.profile help text for scheduler timeoutsRodrigo Vivi
The existing help texts for the JOB_TIMEOUT, TIMESLICE and PREEMPT_TIMEOUT configs were brief and did not make the role of each symbol clear: - _MIN / _MAX: hard bounds on the per-engine-class timeout. They are enforced unconditionally by the sysfs knobs, and (for TIMESLICE, the only one exposed via the SET_PROPERTY UAPI) they also bound CAP_SYS_NICE requests when DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT is enabled. - PREEMPT_TIMEOUT: the boot-time default; the JOB_TIMEOUT and TIMESLICE defaults are hardcoded in the driver, not configured here. Rewrite the help texts to reflect this, naming the relevant sysfs knobs and UAPI property explicitly. v2: Adjusted commit message based on Sashiko's review. Assisted-by: GitHub-Copilot:claude-sonnet-4.6 Assisted-by: GitHub-Copilot:claude-opus-4.8 #v2 Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patch.msgid.link/20260605140951.958172-2-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-06-08drm/virtio: fix dma_fence refcount leak on error in virtio_gpu_dma_fence_wait()Wentao Liang
dma_fence_unwrap_for_each() internally calls dma_fence_unwrap_first() which does cursor->chain = dma_fence_get(head), taking an extra reference. On normal loop completion, dma_fence_unwrap_next() releases this via dma_fence_chain_walk() -> dma_fence_put(). When virtio_gpu_do_fence_wait() fails and the function returns early from inside the loop, the cursor->chain reference is never released. This is the only caller in the entire kernel that does an early return inside dma_fence_unwrap_for_each. Add dma_fence_put(itr.chain) before the early return. Cc: stable@vger.kernel.org Fixes: eba57fb5498f ("drm/virtio: Wait for each dma-fence of in-fence array individually") Signed-off-by: Wentao Liang <vulab@iscas.ac.cn> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Link: https://patch.msgid.link/20260607090303.92423-1-vulab@iscas.ac.cn
2026-06-08drm/panel-edp: Add BOE NV116WH2-M30, BOE NT116WHM-N21, BOE NV116FH1-M31, BOE ↵Terry Hsiao
NV116FH1-M30 The raw EDIDs for each panel: BOE NV116WH2-M30 00 ff ff ff ff ff ff 00 09 e5 6e 38 00 00 00 00 0a 24 01 04 95 1a 0e 78 03 0b 55 9a 5f 58 95 28 1e 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 96 1d 56 c8 50 00 26 30 30 20 36 00 00 90 10 00 00 1a b9 13 56 c8 50 00 26 30 30 20 36 00 00 90 10 00 00 1a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 0d 40 ff 0a 3c 7d 0f 0c 17 7d 00 00 00 00 80 BOE NT116WHM-N21 00 ff ff ff ff ff ff 00 09 e5 79 38 00 00 00 00 08 24 01 04 95 1a 0e 78 03 3a d5 95 5c 58 94 29 24 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 38 1d 56 c8 50 00 1c 30 30 20 36 00 00 90 10 00 00 1a 7b 13 56 c8 50 00 1c 30 30 20 36 00 00 90 10 00 00 1a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 0d 40 ff 0a 3c 7d 0f 0c 17 7d 00 00 00 00 7a BOE NV116FH1-M31 00 ff ff ff ff ff ff 00 09 e5 8b 38 01 ff 00 00 0c 24 01 04 a5 1a 0e 78 03 50 d5 9c 55 52 8f 27 15 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 9a 36 80 a0 70 38 28 40 30 20 35 00 00 90 10 00 00 1a 67 24 80 a0 70 38 28 40 30 20 35 00 00 90 10 00 00 1a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 0d 36 ff 0a 3c 96 0f 0b 1a 96 00 00 00 01 cd 70 20 79 02 00 20 00 0c 9a 0e 00 8b 38 00 00 00 00 0c 1a 00 21 01 1d 03 0a a2 05 80 07 38 04 88 c2 39 55 1e 15 8f 7a 32 15 02 35 54 b0 5c b0 5c 00 36 12 78 22 00 14 ff 21 02 85 7f 07 9f 00 2f 00 1f 00 37 04 27 00 02 00 04 00 81 00 15 74 1a 00 00 03 00 28 3c 00 00 53 5a 53 5a 3c 00 00 00 00 00 00 2b 00 06 27 00 28 3b 00 00 2e 00 06 80 4b b0 5c b0 5c 00 00 00 00 00 00 00 00 00 89 90 BOE NV116FH1-M30 00 ff ff ff ff ff ff 00 09 e5 8c 38 01 ff 00 00 0c 24 01 04 a5 1a 0e 78 03 50 d5 9c 55 52 8f 27 15 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 9a 36 80 a0 70 38 28 40 30 20 35 00 00 90 10 00 00 1a 67 24 80 a0 70 38 28 40 30 20 35 00 00 90 10 00 00 1a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 0d 36 ff 0a 3c 96 0f 0b 1a 96 00 00 00 01 cc 70 20 79 02 00 20 00 0c 9a 0e 00 8c 38 00 00 00 00 0c 1a 00 21 01 1d 03 0a a2 05 80 07 38 04 88 c2 39 55 1e 15 8f 7a 32 15 02 35 54 b0 5c b0 5c 00 36 12 78 22 00 14 ff 21 02 85 7f 07 9f 00 2f 00 1f 00 37 04 27 00 02 00 04 00 81 00 15 74 1a 00 00 03 00 28 3c 00 00 53 5a 53 5a 3c 00 00 00 00 00 00 2b 00 06 27 00 28 3b 00 00 2e 00 06 80 4b b0 5c b0 5c 00 00 00 00 00 00 00 00 00 88 90 Signed-off-by: Terry Hsiao <terry_hsiao@compal.corp-partner.google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patch.msgid.link/20260608080310.15126-3-terry_hsiao@compal.corp-partner.google.com
2026-06-08drm/panel-edp: Add AUO B116XAT04.3, CMN N116BCP-EA2, CSW MNB601LS1-8Terry Hsiao
The raw EDIDs for each panel: AUO B116XAT04.3 00 ff ff ff ff ff ff 00 06 af c0 29 01 ff 00 00 00 24 01 04 95 1a 0e 78 03 9e a5 96 59 58 96 28 1b 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18 df 13 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 10 48 ff 0f 3c 7d 0d 0b 16 7d 00 00 20 01 d6 70 20 79 02 00 20 00 0c 10 d8 b1 c0 29 00 00 00 00 00 1a 00 21 01 1d 01 0a a0 05 56 05 00 03 88 68 59 59 8d 85 96 87 62 1b 02 35 54 00 80 00 80 00 80 11 78 22 00 14 0b 2a 01 84 55 05 e9 00 2f 80 1f 00 ff 02 19 00 03 00 05 00 2b 00 0c 27 00 28 3b 00 00 27 00 28 3b 00 00 2e 00 06 00 80 00 80 00 80 81 00 15 74 1a 00 00 03 01 28 3c 00 00 80 2b 80 2b 3c 00 00 00 00 00 00 00 00 00 2e 90 CMN N116BCP-EA2 00 ff ff ff ff ff ff 00 0d ae 6d 11 00 00 00 00 02 24 01 04 95 1a 0e 78 03 67 75 98 59 53 90 27 1c 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 da 1d 56 e2 50 00 20 30 30 20 a6 00 00 90 10 00 00 1a e7 13 56 e2 50 00 20 30 30 20 a6 00 00 90 10 00 00 1a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 0c 47 ff 08 3c 7d 0d 0a 15 7d 00 00 00 00 04 CSW MNB601LS1-8 00 ff ff ff ff ff ff 00 0e 77 0d 11 00 00 00 00 13 24 01 04 a5 1a 0e 78 03 a1 35 9b 5e 58 91 25 1c 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 09 1e 56 dc 50 00 28 30 30 20 36 00 00 90 10 00 00 1a 06 14 56 dc 50 00 28 30 30 20 36 00 00 90 10 00 00 1a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 0c 3d ff 0c 3c 7d 0e 0b 17 7d 00 00 00 00 01 Signed-off-by: Terry Hsiao <terry_hsiao@compal.corp-partner.google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patch.msgid.link/20260608080310.15126-2-terry_hsiao@compal.corp-partner.google.com
2026-06-08drm/i915/dp_link_training: Document DP link recovery logicImre Deak
Add kernel-doc documentation describing the Intel DP link training recovery state machine and the sequence of automatic retraining, fallback selection, and userspace notification. v2: - Rebase on dedicated intel-display documentation change. - Remove unnecessary indent in section bodies. (Jani) - Add recovery flowcharts. (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260601093836.3057345-23-imre.deak@intel.com
2026-06-08drm/i915/dp_link_training: Fix kernel-doc of intel_dp_init_lttpr_and_dprx_caps()Imre Deak
Fix the list formatting of return values in intel_dp_read_dprx_caps()'s kernel-doc. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260601093836.3057345-22-imre.deak@intel.com
2026-06-08drm/i915/dp_link_training: Disallow autoretrains after failed modesetImre Deak
intel_dp_check_link_state() and intel_dp_link_params_valid() perform only a coarse validation of the link configuration used by the active mode against the available configurations (as constrained by the link training fallback code after a previous LT failure). Even if these coarse checks find a seemingly usable configuration, the modeset check, which performs full verification, may still fail. Disallow further autoretrain attempts if an autoretrain modeset fails. Further attempts would just reuse the same modeset parameters and fail in the same way. Autoretrain will be reallowed unconditionally when the sink reports a change in its capabilities. This allows an autoretrain to proceed once both the link validation and modeset checks confirm a usable configuration. Also clarify in intel_dp_check_link_state() and intel_dp_link_params_valid() that these checks are coarse and that a full validation is only performed by the subsequent atomic modeset check. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260601093836.3057345-21-imre.deak@intel.com
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-12 20:59:26 +0000