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path: root/drivers/gpu
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2026-04-28drm/amdkfd: Reset queue/pipe in MESAmber Lin
When removing queues fails, KFD calls amdgpu_mes to detect and reset hung queues, then cleans up those hung queues in KFD. Suggested-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdkfd: Add detect+reset hangs to GC 12.1Amber Lin
Add detect_and_reset_hung_queues to user mode compute queues on GC 12.1. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu: Enable suspend/resume gang in mes 12.1Amber Lin
This patch adds code to mes_v12_1_suspend_gang and mes_v12_1_resume_gang. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu: Missing multi-XCC support in MESAmber Lin
In a multi-XCC GPU, pass the master XCC's ID to amdgpu_mes_suspend, amdgpu_mes_resume, and detect_and_reset_hung_queues so the command will be sent to the matching master MES when the compute partition mode is not SPX. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu: Move VM PTE MTYPE override to per-PTE granularityPhilip Yang
Refactor the NUMA-aware MTYPE override for VM page table entries: Move the override_vm_pte_flags call from the centralized amdgpu_vm_pte_update_flags() into the individual CPU and SDMA update backends, enabling per-PTE MTYPE override including for scattered pages (pages_addr path). Move APU, IP version, and direct-mapped eligibility checks from runtime (gmc_v9_0_override_vm_pte_flags) to init time (gmc_v9_0_set_gmc_funcs), to avoid repeated runtime checks on every PTE update. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/vcn3: Avoid overflow on msg bound checkBenjamin Cheng
As pointed out by SDL, the previous condition may be vulnerable to overflow. Fixes: b193019860d6 ("drm/amdgpu/vcn3: Prevent OOB reads when parsing dec msg") Cc: SDL <sdl@nppct.ru> Signed-off-by: Benjamin Cheng <benjamin.cheng@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/jpeg: set no_user_fence for JPEG v5.0.2 ringYinjie Yao
JPEG rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: 855e3e19f69c ("drm/amdgpu: Add JPEG_v5_0_2 IP block") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/jpeg: set no_user_fence for JPEG v5.0.1 ringYinjie Yao
JPEG rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: b8f57b69942b ("drm/amdgpu: Add JPEG5_0_1 support") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/jpeg: set no_user_fence for JPEG v5.0.0 ringYinjie Yao
JPEG rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: dfad65c65728 ("drm/amdgpu: Add JPEG5 support") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/jpeg: set no_user_fence for JPEG v4.0.5 ringYinjie Yao
JPEG rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: 8f98a715da8e ("drm/amdgpu/jpeg: add jpeg support for VCN4_0_5") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/jpeg: set no_user_fence for JPEG v4.0.3 ringYinjie Yao
JPEG rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: e684e654eba9 ("drm/amdgpu/jpeg: add jpeg support for VCN4_0_3") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/jpeg: set no_user_fence for JPEG v4.0 ringYinjie Yao
JPEG rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: b13111de32a9 ("drm/amdgpu/jpeg: add jpeg support for VCN4_0_0") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/jpeg: set no_user_fence for JPEG v3.0 ringYinjie Yao
JPEG rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: dfd57dbf44dd ("drm/amdgpu: add JPEG3.0 support for Sienna_Cichlid") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/jpeg: set no_user_fence for JPEG v2.5 ringYinjie Yao
JPEG rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: 14f43e8f88c5 ("drm/amdgpu: move JPEG2.5 out from VCN2.5") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/jpeg: set no_user_fence for JPEG v2.0 ringYinjie Yao
JPEG rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: 6ac27241106b ("drm/amdgpu: add JPEG v2.0 function supports") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/vcn: set no_user_fence for VCN v5.0.2 enc ringYinjie Yao
VCN encoder and decoder rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: 8433398c789c ("drm/amdgpu: Add VCN v5_0_2") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/vcn: set no_user_fence for VCN v5.0.1 enc ringYinjie Yao
VCN encoder and decoder rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: 346492f30ce3 ("drm/amdgpu: Add VCN_5_0_1 support") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/vcn: set no_user_fence for VCN v5.0.0 enc ringYinjie Yao
VCN encoder and decoder rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: b6d1a0632051 ("drm/amdgpu: add VCN_5_0_0 IP block support") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/vcn: set no_user_fence for VCN v4.0.5 enc ringYinjie Yao
VCN encoder and decoder rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: 547aad32edac ("drm/amdgpu: add VCN4 ip block support") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/vcn: set no_user_fence for VCN v4.0.3 enc ringYinjie Yao
VCN encoder and decoder rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: b889ef4ac988 ("drm/amdgpu/vcn: add vcn support for VCN4_0_3") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/vcn: set no_user_fence for VCN v4.0 enc ringYinjie Yao
VCN encoder and decoder rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: 8da1170a16e4 ("drm/amdgpu: add VCN4 ip block support") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/vcn: set no_user_fence for VCN v3.0 enc/dec ringsYinjie Yao
VCN encoder and decoder rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: cf14826cdfb5 ("drm/amdgpu: add VCN3.0 support for Sienna_Cichlid") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/vcn: set no_user_fence for VCN v2.5 enc/dec ringsYinjie Yao
VCN encoder and decoder rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: 28c17d72072b ("drm/amdgpu: add VCN2.5 basic supports") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: properly handle family setting for early GC 11.5.4Alex Deucher
Early variants need an override. Fixes: 57d00816c6a9 ("drm/amdgpu: set family for GC 11.5.4") Cc: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Cc: Roman Li <Roman.Li@amd.com> Cc: Mario Limonciello <superm1@kernel.org> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Tested-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu/vcn: set no_user_fence for VCN v2.0 enc/dec ringsYinjie Yao
VCN encoder and decoder rings do not support 64-bit user fence writes, reject CS submissions with user fences. Fixes: 1b61de45dfaf ("drm/amdgpu: add initial VCN2.0 support (v2)") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yinjie Yao <yinjie.yao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu: Move amdgpu_device_check_iommu_direct_map() earlierPhilip Yang
So device init ram_is_direct_mapped is available when gmc_funcs are selected during IP early init. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/pm: Update emit clock logicLijo Lazar
If only one level is enabled in clock table, there is no need to follow the fine grained clock logic which expects a minimum of two levels (min/max). Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: Promote DC to 3.2.380Taimur Hassan
This version brings along following update: -Fix root clock disabled when DSC power gate disabled for DCN314 -Enable/Disable some power gating -Remove Mall, SubVP and MCLK from DCN42 -Unify fast update classification paths -Fix narrowing boundaries in dml -Update MCIF_ADDR macro to address IGT DWB regression -Fix dual cursor shows on extend desktop -Fix hubp tmz field define mismatch Acked-by: Alex Hung <Alex.Hung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: [FW Promotion] Release 0.1.57.0Taimur Hassan
[Why & How] Modify some IPS related commands. Acked-by: Alex Hung <Alex.Hung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: fix root clock disabled when DSC power gate disabled for DCN314Jing Zhou
[Why] When set debug.disable_dsc_power_gate = true, the original code uses an early return to skip the power gate sequence and root clock enable and disable. For this case, install new driver without uninstall old driver. The sequence like below: 1. On the power-off path, the old driver will power gate dsc and disable_dsc() (root clock disable) due to debug.disable_dsc_power_gate = false. 2. On the power-on path, the new driver will force power on dsc but skip enable_dsc() (root clock enable) due to debug.disable_dsc_power_gate = true. Finally, when mode needs DSC but the root clock is disabled, underflow happened. [How] - Moving enable_dsc() before the disable_dsc_power_gate check so the root clock is always enabled on the power-on path. - Replacing the early return with a goto that skips only the power gate register writes, allowing disable_dsc() to still execute on the power-off path. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Jing Zhou <Jing.Zhou@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: Disable hpo power gateLeo Chen
[Why & How] Disable HPO power gate temporarily to work around some DP 2 LL compliance failures on DCN42. Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: Remove Mall, SubVP and MCLK from DCN42Ivan Lipski
[Why&How] Remove MALL, SubVP and MCLK features from DCN42 resource file since it is an APU and does not support them. Assisted-by: Claude:opus-4.6 Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: Unify fast update classification pathsRafal Ostrowski
[Why] The dc_fast_update intermediate struct created code duplication and complexity with multiple classification paths (populate_fast_updates, fast_nonaddr_updates_exist, full_update_required). This refactoring simplifies the update classification system by consolidating to a single path while maintaining compatibility and adding comprehensive test coverage for fast sequence functionality. [How] Remove entire dc_fast_update struct and associated helper functions: - populate_fast_updates - fast_nonaddr_updates_exist - full_update_required and - Refactor check_update_surfaces_for_stream as the single classification path with explicit handling for func_shaper, lut3d_func, cursor_csc_color_matrix_change and scaler_sharpener_update. - Add reserved bitfields to surface_update_flags and stream_update_flags unions for completeness guards. - Extract dc_check_address_only_update and dc_check_update_surfaces_for_stream as public. - Add comprehensive test coverage with parameterized tests for all FAST flags, update classification tests for MED/FULL paths, and completeness guard tests. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: Fix narrowing boundaries in dmlGaghik Khachatrian
[Why] DML code paths include implicit integer narrowing at protocol and storage boundaries. Making these boundaries explicit improves clarity and reduces warning noise while preserving behavior. [How] Apply explicit C-style casts at intentional narrowing boundaries across DML calculation, mode support, RQ/DLG, wrapper, and DSC helper paths. Keep intermediate arithmetic in natural-width types where practical, with minor type-consistency cleanups where needed. Add explicit boundary casts for intentional narrowing and keep intermediate math in wider types where practical, with small type-consistency cleanups to maintain behavior and readability. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdkfd: Validate CRIU-restored IDs before idr_allocSrinivasan Shanmugam
The KFD CRIU restore flow restores previously saved object IDs from userspace. For event restore: kfd_criu_restore_event() -> create_signal_event() / create_other_event() -> allocate_event_notification_slot() -> idr_alloc(..., *restore_id, *restore_id + 1, ...) For BO restore: criu_restore_memory_of_gpu() -> idr_alloc(..., bo_priv->idr_handle, ...) In both cases, the restored ID comes from userspace-provided CRIU data. idr_alloc() expects the ID range values to fit within signed int limits. If a restored ID is larger than INT_MAX, it can trigger a WARN in the IDR layer. A kernel WARN is undesirable because it prints a warning trace and may cause a panic or reboot on systems with panic_on_warn enabled. Smatch reported these paths as allowing unchecked userspace values to reach idr_alloc(). Add INT_MAX validation before using restored IDs in: - kfd_criu_restore_event() - criu_restore_memory_of_gpu() If the restored ID is invalid, return -EINVAL. This prevents invalid restore data from reaching the IDR layer and avoids WARN-triggering paths, while keeping valid restore behavior unchanged. Fixes: 40e8a766a761 ("drm/amdkfd: CRIU checkpoint and restore events") Reported-by: Dan Carpenter <error27@gmail.com> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Cc: David Yat Sin <david.yatsin@amd.com> Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: David Yat Sin <david.yatsin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu: rework userq fence signal processingChristian König
Move more code into a common userq function. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu: move read_indexed_register to amdgpu_reg_accessGabriel Almeida
The read_indexed_register helper is duplicated across multiple files with identical logic. Move it to amdgpu_reg_access.c as amdgpu_read_indexed_register and update all users accordingly. No functional changes intended. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Gabriel Almeida <gabrielsousa230@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amdgpu: move program_aspm to amdgpu_nbioGabriel Almeida
The program_aspm helper is duplicated across multiple files with identical logic. Move it to amdgpu_nbio.c as amdgpu_nbio_program_aspm and update all users accordingly. Signed-off-by: Gabriel Almeida <gabrielsousa230@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: Enable HUBP/OPTC/DPP power gatingLeo Chen
[Why & How] Enable driver power gating on DCN42 for HUBP OPTC and DPP HW blocks. Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: Fix implicit conversion warningGaghik Khachatrian
[Why & How] Fix implicit narrowing conversion warnings. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: Update MCIF_ADDR macro to address IGT DWB regressionGaghik Khachatrian
[Why] A previous warning-fix commit updated type casts in the DCN3 mmhubbub code but missed updating the MCIF_ADDR macro to the correct, fully parenthesized and casted version. This caused a regression during DWB tests, where address values could be misinterpreted, potentially leading to incorrect hardware programming. [How] Updated the MCIF_ADDR macro in dcn30_mmhubbub.c to use the proper parenthesization and type casting, ensuring correct address handling. Removed redundant casts from REG_UPDATE calls for improved clarity and consistency with current coding standards. Fixes: f4cdbb5d5405 ("drm/amd/display: Fix implicit narrowing conversion warnings") Reviewed-by: Clayton King <clayton.king@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: fix dual cursor shows on extend desktopCharlene Liu
[why & how] when dpp pipe power gating disabled in driver, disable_pipe did not disable cursor so next time as long as this pipe powers up, it will be visible. port dcn314 logic: disable cursor when it should be pipe pg. Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: fix hubp tmz field define mismatchCharlene Liu
[why & how] to make hubp surface_flip_registers field define mismatch with dc_plane_address Reviewed-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/amd/display: Enable driver power gatingLeo Chen
[Why & How] Enable driver power gating. Temporarily disable DIO power gating. Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-28drm/i915/dp: Skip AS SDP for DP branch devicesAnkit Nautiyal
Currently, VRR is not implmented for DP branch devices. So skip sending AS SDP for them. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260424090942.3060291-4-ankit.k.nautiyal@intel.com
2026-04-28drm/i915/dp: Add a helper to decide if AS SDP can be usedAnkit Nautiyal
Add a helper that determines whether AS SDP can be used for the current DP configuration. For now this is true only when the sink supports AS SDP and VRR is enabled, but more conditions may be added later. v2: - Rename to intel_dp_needs_as_sdp(). (Ville) - Add a #FIXME documenting non-atomic of DP SDP updates. (Ville) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260424090942.3060291-3-ankit.k.nautiyal@intel.com
2026-04-28drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sinkAnkit Nautiyal
Currently we do not support VRR with HDMI so skip vrr compute config step for all DP branch devices. v2: Restrict VRR on all DP branch devices instead for checking only for HDMI. (Ville) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260424090942.3060291-2-ankit.k.nautiyal@intel.com
2026-04-28drm/nouveau: WQ_PERCPU added to alloc_workqueue usersMarco Crivellari
Currently if a user enqueue a work item using schedule_delayed_work() the used wq is "system_wq" (per-cpu wq) while queue_delayed_work() use WORK_CPU_UNBOUND (used when a cpu is not specified). The same applies to schedule_work() that is using system_wq and queue_work(), that makes use again of WORK_CPU_UNBOUND. This lack of consistentcy cannot be addressed without refactoring the API. alloc_workqueue() treats all queues as per-CPU by default, while unbound workqueues must opt-in via WQ_UNBOUND. This default is suboptimal: most workloads benefit from unbound queues, allowing the scheduler to place worker threads where they’re needed and reducing noise when CPUs are isolated. This change adds a new WQ_PERCPU flag to explicitly request alloc_workqueue() to be per-cpu when WQ_UNBOUND has not been specified. With the introduction of the WQ_PERCPU flag (equivalent to !WQ_UNBOUND), any alloc_workqueue() caller that doesn’t explicitly specify WQ_UNBOUND must now use WQ_PERCPU. Once migration is complete, WQ_UNBOUND can be removed and unbound will become the implicit default. Suggested-by: Tejun Heo <tj@kernel.org> Signed-off-by: Marco Crivellari <marco.crivellari@suse.com> Link: https://patch.msgid.link/20251031102020.95349-3-marco.crivellari@suse.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-04-28drm/nouveau: replace use of system_unbound_wq with system_dfl_wqMarco Crivellari
Currently if a user enqueue a work item using schedule_delayed_work() the used wq is "system_wq" (per-cpu wq) while queue_delayed_work() use WORK_CPU_UNBOUND (used when a cpu is not specified). The same applies to schedule_work() that is using system_wq and queue_work(), that makes use again of WORK_CPU_UNBOUND. This lack of consistency cannot be addressed without refactoring the API. system_unbound_wq should be the default workqueue so as not to enforce locality constraints for random work whenever it's not required. Adding system_dfl_wq to encourage its use when unbound work should be used. The old system_unbound_wq will be kept for a few release cycles. Suggested-by: Tejun Heo <tj@kernel.org> Signed-off-by: Marco Crivellari <marco.crivellari@suse.com> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20251031102020.95349-2-marco.crivellari@suse.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-04-28drm/udl: Increase GET_URB_TIMEOUTShixiong Ou
[WHY] A situation has occurred where udl_handle_damage() executed successfully and the kernel log appears normal, but the display fails to show any output. This is because the call to udl_get_urb() in udl_crtc_helper_atomic_enable() failed without generating any error message. [HOW] 1. Increase timeout of getting urb. 2. Add error messages when calling udl_get_urb() failed in udl_crtc_helper_atomic_enable(). Signed-off-by: Shixiong Ou <oushixiong@kylinos.cn> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Fixes: 5320918b9a87 ("drm/udl: initial UDL driver (v4)") Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Cc: <stable@vger.kernel.org> # v3.4+ Link: https://patch.msgid.link/20260424124427.657-1-oushixiong1025@163.com
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-09 15:45:01 +0000