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2026-04-17drm/amd/display: Fix double freeIlya Bakoulin
[Why/How] Reset pointer/address to avoid double free. Reviewed-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Fix implicit narrowing conversion warningsGaghik Khachatrian
[Why] Multiple display source files contain implicit narrowing conversions when assigning wider integer types (int, uint32_t) to narrower fields (uint8_t, uint16_t) at hardware register, protocol, and storage boundaries. These conversions are intentional but undocumented, and accompanying runtime assertions add noise without providing compile-time safety. [How] Add explicit casts at all intentional narrowing boundaries across display source files. Use narrower loop variable types where loop bounds guarantee safe range. Remove runtime assertions paired with narrowing casts, inline single-use intermediate variables, and revert block scopes and braces introduced solely to contain those assertions. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Align HWSS fast commit path with legacy pathRafal Ostrowski
Add missing operations to commit_planes_for_stream_fast and hwss_build_fast_sequence to match the legacy commit_planes_for_stream behavior for UPDATE_TYPE_FAST updates. - Add stream-level fast update flags (cursor_attr, cursor_pos, periodic_interrupt, info_frame, dmdata, dither) to dc_stream.h - Add stream-level fields to dc_fast_update struct for fast/full update classification in populate_fast_updates/fast_updates_exist - Add HWSS_SETUP_PERIODIC_INTERRUPT block sequence entry, delegating to dc->hwss.setup_periodic_interrupt instead of calling dcn10 directly - Add HUBP_ENABLE_3DLUT_FL block for 3DLUT FL with should_update_pipe_for_stream/plane guards - Add DPP_SET_CURSOR_MATRIX block with new cursor_csc_change flag - Widen DPP_PROGRAM_GAMUT_REMAP to also trigger on stream gamut_remap - Add info frame, dmdata, dither, and cursor blocks to hwss_build_fast_sequence - Reclassify cursor_position/cursor_attributes as UPDATE_TYPE_FAST - Extract dc_dmdata_types.h to resolve circular include between hw_sequencer.h and dc_stream.h - Remove dcn10_hwseq.h include from dc_hw_sequencer.c Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Unset Replay desync error verification by defaultAllen Li
[Why & How] There will be an unexpected desync error while doing PSR -> Replay transit, so we want to disable the replay desync error detection by default. Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: Allen Li <allen.li@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Remove unused dml2_projectRoman Li
Remove all references to dml2_project_dcn40 from dml2. The project is not used. Signed-off-by: Roman Li <roman.li@amd.com> Acked-by: Chenyu Chen <chen-yu.chen@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: bypass post csc for additional color spaces in dcn42Roman Li
[Why] This aligns dcn42 with: "drm/amd/display: bypass post csc for additional color spaces in dal" [How] Apply the same post csc bypass logic to dcn42 dpp using the helper function. Signed-off-by: Roman Li <roman.li@amd.com> Acked-by: Chenyu Chen <chen-yu.chen@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Add allow_clock_gating to dcn42 dccgRoman Li
[Why] The allow_clock_gating function is present in all other DCN versions and is required to properly migrate DCCG registers access from hwseq to the dccg component, resolving register conflicts. [How] Add the missing .allow_clock_gating function pointer to the dccg42_funcs struct. Signed-off-by: Roman Li <roman.li@amd.com> Acked-by: Chenyu Chen <chen-yu.chen@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Add gc v12_1_0 ip headers v6Bing Ma
Add header files for gc v12_1_0 register offsets and shift masks v2: Update gc v12_1_0 ip headers v3: Update gc v12_1_0 ip headers v4, v5: Clean up registers (Alex) v6: Update gc v12_1_0 ip headers Signed-off-by: Bing Ma <Bing.Ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Add gc v12_1_1 ip headers v3Bing Ma
Add header files for gc v12_1_1 register offsets and shift masks v2: Update gc v12_1_1 ip headers v3: Update gc v12_1_1 ip headers Signed-off-by: Bing Ma <Bing.Ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Update mes 12.1's suspend/resumeAmber Lin
Update mes_v12_1_suspend and mes_v12_1_resume to line up with mes_v12_0. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Create hqd info structureAmber Lin
Create hung_queue_hqd_info structure and fill in hung queses information passed by MES, including queue type, pipe id, and queue id. Suggested-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Fixup detect and resetAmber Lin
Identify hung queues by comparing doorbells shown in hqd_info from MES with doorbells stored in the driver to find matching queues. Suggested-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Fixup boost mes detect hang array sizeAmber Lin
When allocate the hung queues memory, we need to take the number of queues into account for the worst hang case. Suggested-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdkfd: fix redundant MQD iterations in GFX v12.1Alex Sierra
The init_mqd_v12_1 function and its sub-call update_mqd_v12_1 both independently iterate over XCC-specific MQDs. This nested iteration is redundant and can cause MQDs in different queues to be overwritten. This patch removes the duplicate loop logic to prevent queue corruption. Fixes: 01bbc4a4b947 ("drm/amdkfd: Add MQD manager for GFX 12.1.0") Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: make driver manages local vram allocations for for gmc v12.1 A+ALe Ma
Limit mc_vram_size to node_segment_size to prevent allocations to prevent allocations on remote HBM. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Place psp pri_fw bo to VRAM on A+AFeifei Xu
On A+A, psp requires firmware bo be placed on VRAM. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Move get mes version info to the end of set_hw_resourceShaoyun Liu
After init mes queue, it require some time for mes to execute init code including setup version info in CP_MES_GP3 register. Put it after first MES call(set_hw_resource package). Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/amdgpu : Distribute inv_tlbs on individual XCCShaoyun Liu
From MES version 0x74 and above, pipe 1(kiq) support use the shared command buffer to distribute the tasks among the xccs within the same partition. It's more efficient for tlb invalidation been done individually on the each XCC at the same time compare to let master xcc loop all xccs. This requires the coop_mode been set before kiq set_hw_resource. Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: support toc_1 fw load for mp0 v15_0_8Likun Gao
Support for TOC fw load for psp v15_0_8 rev id 0. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: support rlc_1 fw load for gc 12_1Likun Gao
Add support to load rlc firmware for rev_id 0 of gfx v12_1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/pm: Add thermal alert logging to smu15.0.8Lijo Lazar
Add logging for thermal events in SMUv15.0.8 SOCs Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/pm: Add mem temp to gpu metrics for smu_v15_0_8Asad Kamal
Add mem temp to gpu metrics as maximum hbm stack temperature for smu_v15_0_8 Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/pm: Add partition metrics supportAsad Kamal
Add partition metrics support for smu_v15_0_8 Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/pm: Enable thermal alert on SMUv15.0.8Lijo Lazar
Enable thermal alert interrupts on SMUv15.0.8 v2: squash in cleanups Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu/gfx12_1: Increase reserved memory size to 150MAlex Sierra
Increase reserved memory to 150 MB. v2: squash in fixes (Alex) Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Rename CPER Fatal severity macroXiang Liu
Rename CPER severity macro to avoid conflicting with UEFI definition. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: update cp cmd pkt for gfx v12_1 v2Likun Gao
Update CP command package for gfx v12.1. 1. Update to common command pkg format for PACKET3_ACQUIRE_MEM. 2. Update to definition PACKET3_PRED_EXEC command pkt. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Fix gfx_hqd_mask in mes 12.1Amber Lin
Same as compute and sdma, gfx_hqd_mask has been initialized properly in amdgpu_mes_init. set_hw_res should use those initialization accordingly. Hardcoding it causes the mismatch between driver and MES. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: fix integer overflow in amdgpu_gem_align_pitch()Werner Kasselman
amdgpu_gem_align_pitch() is passed u32 width and cpp from dumb buffer creation but uses signed int internally. The round-up add and the aligned * cpp multiplication can overflow, returning zero or a negative pitch. A zero pitch propagates to a zero-sized GEM object allocation that reaches userspace via DRM_IOCTL_MODE_CREATE_DUMB. Switch the helper to unsigned int and use check_add_overflow() / check_mul_overflow() so wraparound returns zero. Reject a zero pitch or size in amdgpu_mode_dumb_create() rather than allocating a zero- byte BO. Fixes: 8e911ab770f7 ("drm: amdgpu: Replace drm_fb_get_bpp_depth() with drm_format_plane_cpp()") Signed-off-by: Werner Kasselman <werner@verivus.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu/jpeg: Fix sprintf buffer overflow warning in jpeg_v2_5Michal Simek
Replace sprintf() with snprintf() to fix the -Werror=format-overflow warning when building with allmodconfig: drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c:152:47: error: '%d' directive writing between 1 and 11 bytes into a region of size 7 [-Werror=format-overflow=] 152 | sprintf(ring->name, "jpeg_dec_%d", i); The ring->name buffer is 16 bytes. Using snprintf() with sizeof() ensures the buffer cannot overflow regardless of the integer value. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/radeon: replace nested min calls with min3Thorsten Blum
In dce6_available_bandwidth() and dce8_available_bandwidth(), replace nested min() calls with min3(). Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/pm: Align PPTable fill with non-Q10 static metricsAsad Kamal
Remove Q10 rounding when applying smu_v15_0_8 static metrics to the driver PPTable as the firmware now provide raw data Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: use DRM_SCHED_PRIORITY_KERNEL for all ttm entitiesPierre-Eric Pelloux-Prayer
ttm jobs must have higher priority than any userspace jobs. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: split amdgpu_ttm_set_buffer_funcs_status in 2 funcsPierre-Eric Pelloux-Prayer
Makes a code slightly clearer and reduces indentation. --- v5: use amdgpu_in_reset in amdgpu_ttm_disable_buffer_funcs --- Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: rename amdgpu_fill_buffer as amdgpu_ttm_clear_bufferPierre-Eric Pelloux-Prayer
This is the only use case for this function. --- v2: amdgpu_ttm_clear_buffer instead of amdgpu_clear_buffer --- Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: get rid of amdgpu_ttm_clear_bufferPierre-Eric Pelloux-Prayer
It's doing the same thing as amdgpu_fill_buffer(src_data=0), so drop it. The only caveat is that amdgpu_res_cleared() return value is only valid right after allocation. --- v2: introduce new "bool consider_clear_status" arg v6: dont pass a NULL resv when calling amdgpu_fill_buffer from amdgpu_bo_create --- Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: drop userq fence driver refs out of fence process()Prike Liang
amdgpu_userq_wait_ioctl() takes extra references on waited-on fence drivers and stores them in waitq->fence_drv_xa. When a new userq fence is created, those references are transferred into userq_fence->fence_drv_array so they can be released when the fence completes. However, those inherited references are currently only dropped from amdgpu_userq_fence_driver_process(). If a fence never reaches that path, such as it is already signaled when created, so we need to explicitly release those fences in that case. v2: use a list(list_cut_before) for managing the signal userq driver fences.(Christian) Link: https://patchwork.freedesktop.org/patch/718078/?series=164763&rev=2 v3: Doesn't cache the userq first unsignaled fence and use the cut before list head directly.(Christian) Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: give ttm entities access to all the sdma schedsPierre-Eric Pelloux-Prayer
With this change we now have as many clear and move entities as we have sdma engines (limited to TTM_NUM_MOVE_FENCES). To enable load-balancing this patch gives access to all sdma schedulers to all entities, except default_entity which has no use for multiple schedulers. --- v6: add comment --- Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu/userq: unpin and unref doorbell and wptr outside mutexSunil Khatri
In amdgpu_userq_destroy once unmap_helpder is called within mutex there is no need to hold mutex. This helps in avoiding a deadlock between doorbell and wptr ww mutex and we could unpin and unref these bos outside mutex safely. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: create multiple clear/move ttm entitiesPierre-Eric Pelloux-Prayer
This enables parallelism of operations. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu/userq: use pm_runtime_resume_and_get and fix err handlingSunil Khatri
Use pm_runtime_resume_and_get instead of pm_runtime_get_sync as it return error but put the reference in the function itself. In goto statements we need to drop the pm reference too. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: only use working sdma schedulers for ttmPierre-Eric Pelloux-Prayer
It's possible that some sdma instances aren't working so we shouldn't try to use them from TTM. To achieve this, delay the call to amdgpu_sdma_set_buffer_funcs_scheds after the rings have been tested, and then use the 'ready' property to decide if a sched should be used or not. Note that currently it's not doing much, because if the ring helper fails for any ring, the whole sdma block init fails. --- v5: check buffer_funcs_enabled from amdgpu_ttm_access_memory_sdma --- Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu/userq: unmap_helper dont return the queue stateSunil Khatri
We check for return value of amdgpu_userq_unmap_helper and compare it against the queue->state which is logically wrong and we should just check for failure and do the needfull. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: pass all the sdma scheds to amdgpu_mmanPierre-Eric Pelloux-Prayer
This will allow the use of all of them for clear/fill buffer operations. Since drm_sched_entity_init requires a scheduler array, we store schedulers rather than rings. For the few places that need access to a ring, we can get it from the sched using container_of. Since the code is the same for all sdma versions, add a new helper amdgpu_sdma_set_buffer_funcs_scheds to set buffer_funcs_scheds based on the number of sdma instances. Note: the new sched array is identical to the amdgpu_vm_manager one. These 2 could be merged. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Acked-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu/userq: unmap is to be called before freeing doorbell/wptr boSunil Khatri
Unmap the queue after freeing doorbell and wptr memory is completely wrong. Any operation on the queue needs the doorbell and wptr to be valid and hence fixing the ordering. Also since we are using amdgpu_bo_reserve in non interruptrable mode so there is no need to check for its return values. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu/userq: hold root bo lock in caller of input_va_validateSunil Khatri
Caller should hold the reservation lock for root.bo in func amdgpu_userq_input_va_validate. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu/userq: caller to take reserv lock for vas_list_cleanupSunil Khatri
In function amdgpu_userq_buffer_vas_list_cleanup, remove the reservation lock for vm and caller should make sure it's taken before locking userq_mutex. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu/userq: create_mqd does not need userq_mutexSunil Khatri
Reshuffle the code to run create_mqd outside the mutex. code here is mostly setting up software structure init before actually registering the userqueue in the xa and to the driver. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu/userq: dont lock root bo with userq_mutex heldSunil Khatri
Do not hold reservation lock for root bo if userq_mutex is already held in the call flow this cause a lock issue with ttm_bo_delayed_delete. Its better to lock the vm->root.bo first and then go ahead with userq_mutex so userq_mutex threads dont get stuck until the reservation lock is held. In this case it helps in the function amdgpu_userq_buffer_vas_mapped for each queue during restore_all. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu/userq: fix kerneldoc for amdgpu_userq_ensure_ev_fenceSunil Khatri
Move the comment for the caller to the definition for amdgpu_userq_ensure_ev_fence in kerneldoc format. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-03 11:47:12 +0000