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2026-04-08drm/imagination: Update check to skip prepare_job() for fragment jobsAlessio Belle
By the time prepare_job() is called on a paired fragment job, the paired geometry job might already be finished and its PM reference dropped. Check the fragment job's PM reference instead which is a bit more likely to be still set. This is a very minor optimization. Signed-off-by: Alessio Belle <alessio.belle@imgtec.com> Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-7-7de8c09cef8c@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-04-08drm/imagination: Move repeated job fence check to its own functionAlessio Belle
This should make the code slightly clearer. Signed-off-by: Alessio Belle <alessio.belle@imgtec.com> Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-6-7de8c09cef8c@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-04-08drm/imagination: Rename fence returned by pvr_queue_job_arm()Alessio Belle
Rename from done_fence to finished_fence, both because the function returns a drm_sched_fence's finished fence, and to avoid confusion with the job fence, which is called the same but has a different purpose. Signed-off-by: Alessio Belle <alessio.belle@imgtec.com> Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-5-7de8c09cef8c@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-04-08drm/imagination: Rename pvr_queue_fence_is_ufo_backed() to reflect usageAlessio Belle
This function is only used by the synchronization code to figure out if a fence belongs to this driver. Rename it to pvr_queue_fence_is_native() and update its documentation to reflect its current purpose. Signed-off-by: Alessio Belle <alessio.belle@imgtec.com> Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-4-7de8c09cef8c@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-04-08drm/imagination: Skip check on paired job fence during job submissionAlessio Belle
While submitting a paired fragment job, there is no need to manually look for, and skip, the paired job fence, as the existing logic to resolve dependencies to pvr_queue_fence objects will have failed to resolve it already and continued with the next one. Point this out where the fence is actually accessed and drop the related check. Signed-off-by: Alessio Belle <alessio.belle@imgtec.com> Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-3-7de8c09cef8c@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-04-08drm/imagination: Fit paired fragment job in the correct CCCBAlessio Belle
For geometry jobs with a paired fragment job, at the moment, the DRM scheduler's prepare_job() callback: - checks for internal (driver) dependencies for the geometry job; - calls into pvr_queue_get_paired_frag_job_dep() to check for external dependencies for the fragment job (the two jobs are submitted together but the common scheduler code doesn't know about it, so this needs to be done at this point in time); - calls into the prepare_job() callback again, but for the fragment job, to check its internal dependencies as well, passing the fragment job's drm_sched_job and the geometry job's drm_sched_entity / pvr_queue. The problem with the last step is that pvr_queue_prepare_job() doesn't always take the mismatched fragment job and geometry queue into account, in particular when checking whether there is space for the fragment command to be submitted, so the code ends up checking for space in the geometry (i.e. wrong) CCCB. The rest of the nested prepare_job() callback happens to work fine at the moment as the other internal dependencies are not relevant for a paired fragment job. Move the initialisation of a paired fragment job's done fence and CCCB fence to pvr_queue_get_paired_frag_job_dep(), inferring the correct queue from the fragment job itself. This fixes cases where prepare_job() wrongly assumed that there was enough space for a paired fragment job in its own CCCB, unblocking run_job(), which then returned early without writing the full sequence of commands to the CCCB. The above lead to kernel warnings such as the following and potentially job timeouts (depending on waiters on the missing commands): [ 552.421075] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#2: kworker/u16:5/63 [ 552.421230] Modules linked in: [ 552.421592] CPU: 2 UID: 0 PID: 63 Comm: kworker/u16:5 Tainted: G W 7.0.0-rc2-gc5d053e4dccb #39 PREEMPT [ 552.421625] Tainted: [W]=WARN [ 552.421637] Hardware name: Texas Instruments AM625 SK (DT) [ 552.421655] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] [ 552.421744] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 552.421766] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] [ 552.421850] lr : pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] [ 552.421923] sp : ffff800084c47650 [ 552.421936] x29: ffff800084c47740 x28: 0000000000000df8 x27: ffff800088a77000 [ 552.421979] x26: 0000000000000030 x25: ffff800084c47680 x24: 0000000000001000 [ 552.422017] x23: ffff800084c47820 x22: 1ffff00010988ecc x21: 0000000000000008 [ 552.422055] x20: 0000000000000208 x19: ffff000006ad5a88 x18: 0000000000000000 [ 552.422093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 [ 552.422130] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 [ 552.422167] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 [ 552.422204] x8 : 00000000f2f2f200 x7 : ffff700010988ecc x6 : 0000000000000008 [ 552.422241] x5 : 0000000000000000 x4 : 1ffff0001114ee00 x3 : 0000000000000000 [ 552.422278] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f [ 552.422316] Call trace: [ 552.422330] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) [ 552.422411] pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] [ 552.422486] pvr_queue_run_job+0x3a4/0x990 [powervr] [ 552.422562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] [ 552.422623] process_one_work+0x520/0x1288 [ 552.422657] worker_thread+0x3f0/0xb3c [ 552.422679] kthread+0x334/0x3d8 [ 552.422706] ret_from_fork+0x10/0x20 Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") Cc: stable@vger.kernel.org Signed-off-by: Alessio Belle <alessio.belle@imgtec.com> Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-2-7de8c09cef8c@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-04-08drm/imagination: Count paired job fence as dependency in prepare_job()Alessio Belle
The DRM scheduler's prepare_job() callback counts the remaining non-signaled native dependencies for a job, preventing job submission until those (plus job data and fence update) can fit in the job queue's CCCB. This means checking which dependencies can be waited upon in the firmware, i.e. whether they are backed by a UFO object, i.e. whether their drm_sched_fence::parent has been assigned to a pvr_queue_fence::base fence. That happens when the job owning the fence is submitted to the firmware. Paired geometry and fragment jobs are submitted at the same time, which means the dependency between them can't be checked this way before submission. Update job_count_remaining_native_deps() to take into account the dependency between paired jobs. This fixes cases where prepare_job() underestimated the space left in an almost full fragment CCCB, wrongly unblocking run_job(), which then returned early without writing the full sequence of commands to the CCCB. The above lead to kernel warnings such as the following and potentially job timeouts (depending on waiters on the missing commands): [ 375.702979] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#1: kworker/u16:3/47 [ 375.703160] Modules linked in: [ 375.703571] CPU: 1 UID: 0 PID: 47 Comm: kworker/u16:3 Tainted: G W 7.0.0-rc2-g817eb6b11ad5 #40 PREEMPT [ 375.703613] Tainted: [W]=WARN [ 375.703627] Hardware name: Texas Instruments AM625 SK (DT) [ 375.703645] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] [ 375.703741] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 375.703764] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] [ 375.703847] lr : pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] [ 375.703921] sp : ffff800084a97650 [ 375.703934] x29: ffff800084a97740 x28: 0000000000000958 x27: ffff80008565d000 [ 375.703979] x26: 0000000000000030 x25: ffff800084a97680 x24: 0000000000001000 [ 375.704017] x23: ffff800084a97820 x22: 1ffff00010952ecc x21: 0000000000000008 [ 375.704056] x20: 00000000000006a8 x19: ffff00002ff7da88 x18: 0000000000000000 [ 375.704093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 [ 375.704132] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 [ 375.704168] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 [ 375.704206] x8 : 00000000f2f2f200 x7 : ffff700010952ecc x6 : 0000000000000008 [ 375.704243] x5 : 0000000000000000 x4 : 1ffff00010acba00 x3 : 0000000000000000 [ 375.704279] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f [ 375.704317] Call trace: [ 375.704331] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) [ 375.704411] pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] [ 375.704487] pvr_queue_run_job+0x3a4/0x990 [powervr] [ 375.704562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] [ 375.704623] process_one_work+0x520/0x1288 [ 375.704658] worker_thread+0x3f0/0xb3c [ 375.704680] kthread+0x334/0x3d8 [ 375.704706] ret_from_fork+0x10/0x20 [ 375.704736] ---[ end trace 0000000000000000 ]--- Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") Cc: stable@vger.kernel.org Signed-off-by: Alessio Belle <alessio.belle@imgtec.com> Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-1-7de8c09cef8c@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-04-08drm/i915/pci: move intel_pci_config.h under include/drm/intelJani Nikula
Since the PCI registers are used from both i915 display and core, move intel_pci_config.h to include/drm/intel/pci_config.h. Drop the intel_ prefix from the name to reduce tautology. With this, we can drop the corresponding xe display compat header. v2: Rebase Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/5aac6c711c3f0a09fc52f322455a4a4b35f80a82.1775590536.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-04-08drm/i915: drop unnecessary intel_pci_config.h includeJani Nikula
There's an unnecessary include. Drop it. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/8323c99f379809b2973c99ebe54c21fd274d246c.1775590536.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-04-08drm/i915/mchbar: move intel_mchbar_regs.h under include/drm/intelJani Nikula
Since the mchbar registers are used from both i915 display and core, move intel_mchbar_regs.h to include/drm/intel/mchbar_regs.h. Drop the intel_ prefix from the name to reduce tautology. With this, we can drop the corresponding xe display compat header. v2: Rebase Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/6c951b2c05db74ea517d52a3912986f7eb886422.1775590536.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-04-08drm/i915/mchbar: drop unnecessary intel_mchbar_regs.h includeJani Nikula
There are some unnecessary includes. Remove. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/7eaf98e648240e3011bfb85d0330787074c39205.1775590536.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-04-08drm/i915/mchbar: include intel_mchbar_regs.h from intel_mchbar.hJani Nikula
As an exception to the rule of not including unnecessary headers from headers, include intel_mchbar_regs.h from intel_mchbar.h. In order to use the interfaces in intel_mchbar.h you will always have to include the registers anyway, so the includes are in pairs everywhere. There is zero asymmetry. Simplify. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/e44dc2daf3fc39d02c3f598c323caa3c08a54304.1775590536.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-04-08drm/ast: Fix open-coded scu_rev accessThomas Zimmermann
Replace all open-coded access to P2A and SCU registers in the device detection with the appropriate calls to ast_moutdwm() and ast_mindwm(). Use P2A and MCR register constants. Name variables according to registers. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-16-tzimmermann@suse.de
2026-04-08drm/ast: dp501: Fix open-coded register accessThomas Zimmermann
Replace all open-coded access to SCU registers in DP501 support with the appropriate calls to ast_moutdwm() and ast_mindwm(). Use SCU register constants. Name variables according to registers. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-15-tzimmermann@suse.de
2026-04-08drm/ast: Gen6: Fix open-coded register accessThomas Zimmermann
Replace all open-coded access to MCR and SCU registers in Gen6 with the appropriate calls to ast_moutdwm() and ast_mindwm(). Use MCR and SCU register constants. Name variables according to registers. v2: - also fix MCR constants Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-14-tzimmermann@suse.de
2026-04-08drm/ast: Gen4: Fix open-coded register accessThomas Zimmermann
Replace all open-coded access to MCR and SCU registers in Gen4 with the appropriate calls to ast_moutdwm() and ast_mindwm(). Use MCR and SCU register constants. Name variables according to registers. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-13-tzimmermann@suse.de
2026-04-08drm/ast: Gen2: Fix open-coded register accessThomas Zimmermann
Replace all open-coded access to MCR and SCU registers in Gen2 with the appropriate calls to ast_moutdwm() and ast_mindwm(). Use MCR and SCU register constants. Name variables according to registers. The values in MCR04 that control VRAM allocation do not look correct. Leave a FIXME comment for later investigation. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-12-tzimmermann@suse.de
2026-04-08drm/ast: Gen1: Fix open-coded register accessThomas Zimmermann
Replace all open-coded access to MCR registers in Gen1 with the appropriate calls to ast_moutdwm() and ast_mindwm(). Use MCR register constants. For the poll loop on MCR100, add ast_moutdwm_poll(). The helper polls the register until it has been updated to the given value. Relax the CPU while busy-waiting. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-11-tzimmermann@suse.de
2026-04-08drm/ast: Store register addresses in struct ast_dramstructThomas Zimmermann
Struct ast_dramstruct contains a 16-bit index field that either contains a magic value or serves as index into the P2A address segment at 0x1e600000. This segment serves MCR and SCU registers, which the ast_dramstruct programs. It's fragile and relies upon the ast_post_chip_*() functions to set up the segment correctly. Replace the 16-bit index with a full 32-bit address of the SCU and MCR addresses. Initialize the DRAM tables with full register constants and write them out with ast_moutdwm(). This sets the correct segment on each write. Drop __AST_DRAMSTRUCT_DRAM_TYPE as it simply referred to MCR04. Use the latter for initializing the DRAM tables. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-10-tzimmermann@suse.de
2026-04-08drm/ast: Use constants for SDRAM registersThomas Zimmermann
Aspeed hardware allows for acceessing the SDRAM from the host. SDRAM registers are located at the memory range at [0x80000000, 0xffffffff]. Refer to memory access with the macro AST_SDRAM(). Also add a TODO item for the nonsensical documentation next to its caller. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-9-tzimmermann@suse.de
2026-04-08drm/ast: Use constants for WDT registersThomas Zimmermann
WDT is the Watchdog timer. WDC registers are located at the memory range at [0x1e785000, 0x1e785fff]. There are currently up to 8 watchdog timers in the range, of which 2 are being used by AST2500. Refer to them with macros named AST_REG_WDT<n>, where <n> is the byte offset into the watchdog timer's memory range. Each macro also takes the index of the watchdog timer to access. A new watchdog timer starts at each 0x40 byte offset. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-8-tzimmermann@suse.de
2026-04-08drm/ast: Use constants for A2P registersThomas Zimmermann
A2P is the AHB-to-P Bridge. A2P registers are located at the memory range at [0x1e720000, 0x1e73ffff]. Refer to them with constants named AST_REG_A2P<n>, where <n> is the byte offset into the range. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-7-tzimmermann@suse.de
2026-04-08drm/ast: Use constants for SCU registersThomas Zimmermann
SCU is the System Control Unit. SCU registers are located in the memory range at [0x1e6e2000, 0x1e6e2fff]. Refer to them with constants named AST_REG_SCU<n>, where <n> is the byte offset into the range. Replacing the magic values in the ast driver was done with grep and sed as shown below git grep -l \,\ 0x1e6e2 | xargs sed -i -e 's/, 0x1e6e2/, AST_REG_SCU/g' git grep -l \,\ 0x1E6E2 | xargs sed -i -e 's/, 0x1E6E2/, AST_REG_SCU/g' plus some manual fixes. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-6-tzimmermann@suse.de
2026-04-08drm/ast: Use constants for MCR registersThomas Zimmermann
SDRAM registers are located in the memory range at [0x1e160000, 0x1e160fff]. Refer to them with constants named AST_REG_MCR<n>, where n is the byte offset into the range. Replacing the magic values in the ast driver was done with grep and sed as shown below git grep -l \,\ 0x1e6e00 | xargs sed -i -e 's/, 0x1e6e00/, AST_REG_MCR/g' git grep -l \,\ 0x1E6E00 | xargs sed -i -e 's/, 0x1E6E00/, AST_REG_MCR/g' plus some manual fixes. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-5-tzimmermann@suse.de
2026-04-08drm/ast: Use constants for AHBC registersThomas Zimmermann
AHBC is the Advanced High-Speed Bus Controller. AHBC registers are located in the memory range within [0x1e600000, 0x1e61ffff]. Refer to them with constants named AST_REG_AHBC<n>, where <n> is the byte offset into the range. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-4-tzimmermann@suse.de
2026-04-08drm/ast: Move 32-bit register-access helpers to ast_drv.{c, h}Thomas Zimmermann
The helpers ast_mindwm() and ast_moutdwm() access the I/O memory of the various IP modules on the Aspeed device. This is based on the "P-Bus to AHB Bridge" interface. Reimplement the access function with properly defined constants and helper macros. - Define P2A constants for the related registers and addresses. The P2A interface is located in the memory range at [0x00000000, 0x00010000]. - Memory access is segmented. An address' upper 16-bit select the memory segment, the lower 16-bit select the offset within the segment. Implement segment selection in a shared helper __ast_segsel(). Validate that the segment hs been changes. This logic has previously been part of __ast_moudwm() and __ast_mindwm(). Relax the CPU while busy-waiting. - Put intra-segment reads and writes in the helpers __ast_rdseg32() and __ast_wrseg32(). The helpers set the segment offset automatically. - Reimplement the existing interfaces on top of these helpers. Put the new implementation next to the other I/O helpers. v2: - fix typo in commit description (Jocelyn) Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-3-tzimmermann@suse.de
2026-04-08drm/panthor: Fix kernel-doc warning in panthor_sched.cYicong Hui
Fix the following W=1 kerneldoc warnings by adding the missing parameter descriptions for @ptdev and @events in panthor_sched_report_fw_events() and @ptdev in panthor_sched_report_mmu_fault() Warning: drivers/gpu/drm/panthor/panthor_sched.c:1898 function parameter 'ptdev' not described in 'panthor_sched_report_fw_events' Warning: drivers/gpu/drm/panthor/panthor_sched.c:1898 function parameter 'events' not described in 'panthor_sched_report_fw_events' Warning: drivers/gpu/drm/panthor/panthor_sched.c:2783 function parameter 'ptdev' not described in 'panthor_sched_report_mmu_fault' Fixes: de8548813824 ("drm/panthor: Add the scheduler logical block") Signed-off-by: Yicong Hui <yiconghui@gmail.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Signed-off-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20260405192309.389039-1-yiconghui@gmail.com
2026-04-08Merge tag 'rust-timekeeping-for-v7.1' of ↵Miguel Ojeda
https://github.com/Rust-for-Linux/linux into rust-next Pull timekeeping updates from Andreas Hindborg: - Expand the example section in the 'HrTimer' documentation. - Mark the 'ClockSource' trait as unsafe to ensure valid values for 'ktime_get()'. - Add 'Delta::from_nanos()'. This is a back merge since the pull request has a newer base -- we will avoid that in the future. And, given it is a back merge, it happens to resolve the "subtle" conflict around '--remap-path-{prefix,scope}' that I discussed in linux-next [1], plus a few other common conflicts. The result matches what we did for next-20260407. The actual diffstat (i.e. using a temporary merge of upstream first) is: rust/kernel/time.rs | 32 ++++- rust/kernel/time/hrtimer.rs | 336 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 362 insertions(+), 6 deletions(-) Link: https://lore.kernel.org/linux-next/CANiq72kdxB=W3_CV1U44oOK3SssztPo2wLDZt6LP94TEO+Kj4g@mail.gmail.com/ [1] * tag 'rust-timekeeping-for-v7.1' of https://github.com/Rust-for-Linux/linux: hrtimer: add usage examples to documentation rust: time: make ClockSource unsafe trait rust/time: Add Delta::from_nanos()
2026-04-08Merge drm/drm-next into drm-misc-nextThomas Zimmermann
Backmerging to get fixes from -rc7. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2026-04-08drm/i915/backlight: Fix VESA backlight possible check conditionSuraj Kandpal
VESA backlight enable is possible when BACKLIGHT_AUX_ENABLE_CAPABLE is true via AUX command or when BACKLIGHT_PIN_ENABLE_CAPABLE is true via eDP connector pin. Similarly, backlight brightness adjustment can be done via AUX-based control or PWM pin-based control. It means there can be three configurations: 1) Full AUX-based: Enable and adjustment both via AUX. We currently support this (apart from the AUX luminance-based backlight control). 2) Hybrid: Enable via the BL_ENABLE pin, adjustment via either AUX or PWM. 3) Fully PWM pin-based: Enable via the BL_ENABLE pin, adjustment via PWM. Since that only 1 is supported as of now we need to make sure we do not try to manipulate backlight when BACKLIGHT_AUX_ENABLE_CAPABLE is not set. Also fix return value when condition is not fulfilled. Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/15907 Fixes: 0fb03890d182 ("drm/i915/backlight: Check if VESA backlight is possible") Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260407030710.1440046-1-suraj.kandpal@intel.com
2026-04-08ttm/pool: track allocated_pages per numa node.Dave Airlie
This gets the memory sizes from the nodes and stores the limit as 50% of those. I think eventually we should drop the limits once we have memcg aware shrinking, but this should be more NUMA friendly, and I think seems like what people would prefer to happen on NUMA aware systems. Cc: Christian Koenig <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2026-04-08ttm/pool: make pool shrinker NUMA aware (v2)Dave Airlie
This enable NUMA awareness for the shrinker on the ttm pools. Cc: Christian Koenig <christian.koenig@amd.com> Cc: Dave Chinner <david@fromorbit.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2026-04-08ttm/pool: drop numa specific poolsDave Airlie
The list_lru will now handle numa for us, so no need to keep separate pool types for it. Just consolidate into the global ones. This adds a debugfs change to avoid dumping non-existant orders due to this change. Cc: Christian Koenig <christian.koenig@amd.com> Cc: Johannes Weiner <hannes@cmpxchg.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
2026-04-08ttm/pool: port to list_lru. (v2)Dave Airlie
This is an initial port of the TTM pools for write combined and uncached pages to use the list_lru. This makes the pool's more NUMA aware and avoids needing separate NUMA pools (later commit enables this). Cc: Christian Koenig <christian.koenig@amd.com> Cc: Johannes Weiner <hannes@cmpxchg.org> Cc: Dave Chinner <david@fromorbit.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2026-04-08drm/ttm: use gpu mm stats to track gpu memory allocations. (v4)Dave Airlie
This uses the newly introduced per-node gpu tracking stats, to track GPU memory allocated via TTM and reclaimable memory in the TTM page pools. These stats will be useful later for system information and later when mem cgroups are integrated. Cc: Christian Koenig <christian.koenig@amd.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: Johannes Weiner <hannes@cmpxchg.org> Cc: linux-mm@kvack.org Cc: Andrew Morton <akpm@linux-foundation.org> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2026-04-07drm/xe: Fix bug in idledly unit conversionVinay Belgaumkar
We only need to convert to picosecond units before writing to RING_IDLEDLY. Fixes: 7c53ff050ba8 ("drm/xe: Apply Wa_16023105232") Cc: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com> Acked-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Link: https://patch.msgid.link/20260401012710.4165547-1-vinay.belgaumkar@intel.com (cherry picked from commit 13743bd628bc9d9a0e2fe53488b2891aedf7cc74) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-04-07drm/i915/pin: switch to i915 core runtime pmJani Nikula
Remove a dependency on struct intel_display from i915 core code. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/c06366c1c6f9202be5d0b6ea649c20aba414e5bc.1775556190.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-04-07drm/i915/pin: s/dev_priv/i915/ and drop struct drm_device usageJani Nikula
Improve consistency within i915_fb_pin.c by replacing dev_priv naming with i915, and dropping struct drm_device usage. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/3a4ac0a732a561a487e46838bde6327cff5ccb38.1775556190.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-04-07drm/i915: move intel_fb_pin.c to i915_fb_pin.cJani Nikula
intel_fb_pin.c is the final file in display/ that's specific to i915 only. Move it to i915 core, renaming it to i915_fb_pin.c. It'll still depend on a lot of display stuff, unfortunately. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/ab1ffc08bcd1364715396142f91780b6261bbe65.1775556190.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-04-07drm/i915/gt: fix refcount underflow in intel_engine_park_heartbeatSebastian Brzezinka
A use-after-free / refcount underflow is possible when the heartbeat worker and intel_engine_park_heartbeat() race to release the same engine->heartbeat.systole request. The heartbeat worker reads engine->heartbeat.systole and calls i915_request_put() on it when the request is complete, but clears the pointer in a separate, non-atomic step. Concurrently, a request retirement on another CPU can drop the engine wakeref to zero, triggering __engine_park() -> intel_engine_park_heartbeat(). If the heartbeat timer is pending at that point, cancel_delayed_work() returns true and intel_engine_park_heartbeat() reads the stale non-NULL systole pointer and calls i915_request_put() on it again, causing a refcount underflow: ``` <4> [487.221889] Workqueue: i915-unordered engine_retire [i915] <4> [487.222640] RIP: 0010:refcount_warn_saturate+0x68/0xb0 ... <4> [487.222707] Call Trace: <4> [487.222711] <TASK> <4> [487.222716] intel_engine_park_heartbeat.part.0+0x6f/0x80 [i915] <4> [487.223115] intel_engine_park_heartbeat+0x25/0x40 [i915] <4> [487.223566] __engine_park+0xb9/0x650 [i915] <4> [487.223973] ____intel_wakeref_put_last+0x2e/0xb0 [i915] <4> [487.224408] __intel_wakeref_put_last+0x72/0x90 [i915] <4> [487.224797] intel_context_exit_engine+0x7c/0x80 [i915] <4> [487.225238] intel_context_exit+0xf1/0x1b0 [i915] <4> [487.225695] i915_request_retire.part.0+0x1b9/0x530 [i915] <4> [487.226178] i915_request_retire+0x1c/0x40 [i915] <4> [487.226625] engine_retire+0x122/0x180 [i915] <4> [487.227037] process_one_work+0x239/0x760 <4> [487.227060] worker_thread+0x200/0x3f0 <4> [487.227068] ? __pfx_worker_thread+0x10/0x10 <4> [487.227075] kthread+0x10d/0x150 <4> [487.227083] ? __pfx_kthread+0x10/0x10 <4> [487.227092] ret_from_fork+0x3d4/0x480 <4> [487.227099] ? __pfx_kthread+0x10/0x10 <4> [487.227107] ret_from_fork_asm+0x1a/0x30 <4> [487.227141] </TASK> ``` Fix this by replacing the non-atomic pointer read + separate clear with xchg() in both racing paths. xchg() is a single indivisible hardware instruction that atomically reads the old pointer and writes NULL. This guarantees only one of the two concurrent callers obtains the non-NULL pointer and performs the put, the other gets NULL and skips it. Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/15880 Fixes: 058179e72e09 ("drm/i915/gt: Replace hangcheck by heartbeats") Cc: <stable@vger.kernel.org> # v5.5+ Signed-off-by: Sebastian Brzezinka <sebastian.brzezinka@intel.com> Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/d4c1c14255688dd07cc8044973c4f032a8d1559e.1775038106.git.sebastian.brzezinka@intel.com
2026-04-07drm/i915/pfit: Prevent negative coordinates in center modeNemesa Garg
When the pipe_src width or height are greater than adjusted_mode hdisplay and vdisplay, computed x and y offsets for center mode can be negative. Writing negative values into the pch_fit registers result in a state error. Add a check to clamp these values so that they are never negative. v2: Compare in terms of pipe_src width and height.[Ville] v3: Change width/height to pipe_src_w/h in logging. [Ville] Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260402061310.111073-1-nemesa.garg@intel.com
2026-04-08drm/exynos: Drop MAX_FB_BUFFER in favor of DRM_FORMAT_MAX_PLANESChen-Yu Tsai
MAX_FB_BUFFER refers to the maximum number of buffer planes for a framebuffer. This is the same as DRM_FORMAT_MAX_PLANES, which denotes the maximum number of planes. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2026-04-08drm/exynos: Drop exynos_drm_gem.size fieldChen-Yu Tsai
A size field is already included in the base GEM object, and is initialized through drm_gem_object_init() with the same value. Drop the field in the subclass to save some space. More changes to make exynos_drm_gem a subclass of drm_gem_dma_object will follow. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2026-04-08drm/exynos: Use DRM core dedicated DMA device tracking facilityChen-Yu Tsai
The exynos driver tracks a dedicated DMA device in its private data. The DRM core already has facilities to do this, and it is integrated into DRM PRIME imports and GEM DMA helpers. Convert the exynos driver to use the core's dedicated DMA device tracking facility. Also get rid of exynos_drm_gem_prime_import() as it is identical to drm_gem_prime_import() after the conversion. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2026-04-08drm/exynos: Internalize exynos_drm_gem_free_object()Chen-Yu Tsai
exynos_drm_gem_free_object() is only provided as a callback for GEM objects. It does not need to be exposed to the rest of the driver. Move it above where it is used and internalize it to just the GEM functions. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2026-04-07Merge v7.0-rc7 into drm-nextSimona Vetter
Thomas Zimmermann needs 2f42c1a61616 ("drm/ast: dp501: Fix initialization of SCU2C") for drm-misc-next. Conflicts: - drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c Just between e927b36ae18b ("drm/amd/display: Fix NULL pointer dereference in dcn401_init_hw()") and it's cherry-pick that confused git. - drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c Deleted in 6b0a6116286e ("drm/amd/pm: Unify version check in SMUv11") but some cherry-picks confused git. Same for v12/v14. Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch>
2026-04-07drm/i915/display: Panel Replay BW optimization for DP2.0 tunnelingAnimesh Manna
Unused bandwidth can be used by external display agents for Panel Replay enabled DP panel during idleness with link on. Enable source to replace dummy data from the display with data from another agent by programming TRANS_DP2_CTL [Panel Replay Tunneling Enable]. v2: - Enable pr bw optimization along with panel replay enable. [Jani] v3: - Write TRANS_DP2_CTL once for both bw optimization and panel replay enable. [Jani] v4: - Read DPCD once in init() and store in panel_replay_caps. [Jouni] v5: - Avoid reading DPCD for edp. [Jouni] - Use drm_dp_dpcd_read_byte() and some cosmetic changes. [Jani] v6: - Extend the corresponding interface defined in drm_dp_tunnel.c to query the Panel Replay optimization capability. [Imre] v7: - Clear TRANS_DP2_PR_TUNNELING_ENABLE if pr bw optimization is not allowed. [Jouni] - Move intel_dp_is_edp() check. [Jouni] Bspec: 68920 Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patch.msgid.link/20260330133620.3750559-4-animesh.manna@intel.com
2026-04-07drm/i915/display: Add hook to check optimization support for Intel platformsAnimesh Manna
Add a hook that uses the drm core tunneling function to check whether panel replay bandwidth optimization support is present. v2: Move DISPLAY_VER() check to intel_dp_tunnel_pr_optimization_supported(). [Jouni] Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patch.msgid.link/20260330133620.3750559-3-animesh.manna@intel.com
2026-04-07drm/display: Add drm helper to check pr optimization supportAnimesh Manna
Add api to check panel replay optimization supported or not to drm-core DP tunneling framework which can be used by other driver as well. v2: Split generic drm changes from Intel specific changes. [Jouni] Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Suggested-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Acked-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/20260330133620.3750559-2-animesh.manna@intel.com
2026-04-07rust: bump Clippy's MSRV and clean `incompatible_msrv` allowsMiguel Ojeda
Following the Rust compiler bump, we can now update Clippy's MSRV we set in the configuration, which will improve the diagnostics it generates. Thus do so and clean a few of the `allow`s that are not needed anymore. Reviewed-by: Tamir Duberstein <tamird@kernel.org> Acked-by: Danilo Krummrich <dakr@kernel.org> Reviewed-by: Gary Guo <gary@garyguo.net> Link: https://patch.msgid.link/20260405235309.418950-7-ojeda@kernel.org Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-04 07:10:34 +0000