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12 daysdrm/i915/bios: de/allocate VS/PE-O buffers for each portMichał Grzelak
Every devdata needs VS/PE-O dedicated buffers since each port can request an override. Add intel_ddi_buf_trans{,_entry} pointers into intel_bios_encoder_data. Allocate struct intel_ddi_buf_trans{,_entry} for the port if VS/PE-O was requested and is supported. Keep NULL in vspeo if any allocation failed or VS/PE-O was not requested. It will be used later for checking if override should actually take place. Note that we theoretically could store intel_ddi_buf_trans_entry inside `entries` field of newly allocated intel_ddi_buf_trans. However it will be impossible to overwrite the buffer during intel_ddi_get_buf_trans() without discarding const qualifier of `entries` field. This would involve either void casting or deconstifying entries field and in turn all predefined tables as well. Thus add a separate non-const qualified field into intel_bios_encoder_data for the buffer, which after overwriting will be promoted to be const qualified. Deallocate the buffer as well as entries if requested. v11->v12 - set vspeo->num_entries once (Sashiko) - free allocated vspeo->entries (Sashiko) v9->v10 - add separate non-const field for `entries` caching - cache `entries` into const field after data is overwritten (Jani) v4->v5 - set devdata->vspeo->num_entries in intel_bios.c Signed-off-by: Michał Grzelak <michal.grzelak@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260904123148.2165596-5-michal.grzelak@intel.com
12 daysdrm/i915/bios: print VS/PE-O port infoMichał Grzelak
Issue a debug message when port asks to override default Vswing / Preemphasis tables. Add helper intel_bios_encoder_requests_vspeo() to check if port requests for overriding default VS/PE tables. v6->v7 - expand VS/PE-O acronym in debug logging (Jani) v3->v4 - change debug message when requesting VS/PE-O (Suraj) Signed-off-by: Michał Grzelak <michal.grzelak@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260904123148.2165596-4-michal.grzelak@intel.com
12 daysdrm/i915/bios: store VBT #57's metadata in intel_vbt_dataMichał Grzelak
Store tables, number of tables, number of rows and number of columns in intel_vbt_data when search for the VBT #57 has succeeded. Structurize all VS/PE-O relevant metadata inside anonymous struct named as vspeo. Presence of C20 or newer PHY causes each table to contain 16 rows. Each table contains 10 rows in case C20 PHY is absent. Use display version to determine number of rows since there is no helper in intel_bios.c to check presence of any C20+ PHY. pre-MTL platforms should have 10 rows while MTL+ should have 16 rows. v5->v6 - add Bspec (Suraj) v3->v4 - remove unnecessary init of VS/PE-O metadata (Suraj) - add helper for computing number of rows (Suraj) - fix num_rows's type (Jani, Suraj) - declare num_rows (Suraj) Bspec: 68963 Signed-off-by: Michał Grzelak <michal.grzelak@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260904123148.2165596-3-michal.grzelak@intel.com
12 daysdrm/i915/bios: search for VBT #57 by defaultMichał Grzelak
Start searching for Vswing / Preemphasis Override Block during VBT parsing at init_bdb_blocks(). Check for failure since pre-ICL GOPs do not contain the block. Check also if VBT version is appropriately up-to-date. v6->v7 - parse VBT#57 before blocks dependent on child device list (Jani) - remove debug message (Suraj) v3->v4 - add Bspec (Suraj) Bspec: 32063 Signed-off-by: Michał Grzelak <michal.grzelak@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260904123148.2165596-2-michal.grzelak@intel.com
12 daysMerge tag 'drm-xe-next-2026-08-31-1' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next Cross-subsystem Changes: - MAINTAINERS: Add entries for drm_ras (Rodrigo) - alerts and controller enabling modifications (Heikki) Core Changes: - Introduce cold reset recovery method (Mallesh) - Add drm_ras netlink error event support (Riana) - Introduce error threshold to drm_ras (Raag) Driver Changes: - Remove sysfs entry on idr_alloc failure in xe_oa_add_config_ioctl (Lu) - match argument naming with PCODE_DATAx (Grzelak) - fix stale GGTT mappings on unmap (Tangudu) - Introduce error threshold to drm_ras (Raag) - Add debugfs knob to control GPGPU preemption granularity (Varun) - fix vecs config for powergating info (Ashutosh) - Read mailbox phase bit from hardware (Anoop) - alerts and controller enabling modifications (Heikki) - Use int instead of u32 for mailbox status (Umesh) - Reject page faults from non-fault-mode scratch VMs (Arvind) - Add CCS to the powergating info print (Balasubramani) - Do not apply WA 14025883347 to media 3503 (Daniele) - don't WARN on kernel job timeout when device already wedged (Nitin) - handle exec queue teardown after hot-unplug (Nitin) - Allow debugging PCI errors (Raag) - Add structured SIGID error logging infrastructure (Wajdeczko, Rodrigo) - Enable package and vram temperatures for CRI (Karthik) - Introduce cold reset recovery method (Mallesh) - fix error message in xe_migrate_sanity_test (Dan Carpenter) - Add drm_ras netlink error event support (Riana) - Fix a bug in pc_adjust_freq_bounds() (Vinay) - Fix xe_device_probe() failure (Raag) - Page fault cleanups (Wajdeczko) - OA memory fixes (Linmao) - document sentinel and make CTX_TIMESTAMP read TOCTOU-safe (Gajendra) - Move has_drm_ras check to drm_ras layer (Raag) - add termination on resume (Daniele) - Add _locked variants of some config functions (Wajdeczko) - Order ring writes before ring tail updates (Brost) - Parallel page fault handling (Brost) - handle CRI+ power interval encoding (Karthik) - allocate UM queues in a separate UC BO (Jia) - Fix boot-time ras error processing (Raag) - VF migration for multi-queue (Niranjana) - Apply RCS/CCS yield policy to SR-IOV VFs (Marcin) - Fix memory leak in exec_queue_set_hang_replay_state (Winiarski) - Use IBC v3 on PTL (Vinay) - Reduce MERT debug log spam (Lukasz, Piotr) - Validate sysctrl response (Raag) - Changes for Xe3p_HPM media (Ashutosh) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/apYbnrklyk6nNO7Q@gsse-cloud1.jf.intel.com
12 daysdrm/msm/adreno: Only check for PAS when a zap shader is presentPaul Hollinsky
Commit 0be72be03ca7 ("drm/msm: Switch to generic PAS TZ APIs") replaced the qcom_scm_is_available() check in adreno_zap_shader_load() with qcom_pas_is_available(). These are not equivalent: the former reports whether the SCM transport is up, the latter whether the TrustZone firmware implements the peripheral authentication service. On SC7180 Chromebooks (trogdor) TZ does not implement PAS at all. SCM call-availability queries return 0 for every PAS command while other services answer normally: svc 0x06 cmd 0x01 IS_CALL_AVAIL -> 1 svc 0x02 cmd 0x01 PAS_INIT_IMAGE -> 0 svc 0x02 cmd 0x05 PAS_AUTH_RESET -> 0 svc 0x02 cmd 0x07 PAS_IS_SUPPORTED -> 0 svc 0x0c cmd 0x16 MP_ASSIGN -> 1 svc 0x05 cmd 0x01 IO_READ -> 1 so qcom_scm_probe() never registers a PAS backend and qcom_pas_is_available() is false for the lifetime of the boot. That on its own need not matter, because sc7180-trogdor.dtsi does /delete-node/ &gpu_zap_shader;, and the intended path for such a board is for zap_shader_load_mdt() to find no zap-shader child, clear zap_available, return -ENODEV, and let the caller fall back to SECVID_TRUST_CNTL. The problem is the ordering. zap_available is a static initialised to true and is only ever cleared inside zap_shader_load_mdt(), but adreno_zap_shader_load() consults PAS before calling it. The discovery that decides whether a zap shader is needed at all can therefore never run, the flag is never cleared, and every call returns -EPROBE_DEFER: adreno 5000000.gpu: [drm:adreno_zap_shader_load] *ERROR* PAS is not available msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* gpu hw init failed: -517 Nothing retries that deferral, either. adreno_zap_shader_load() is called from a6xx_hw_init() rather than from probe, so the -EPROBE_DEFER is not a probe return value: it propagates up until adreno_load_gpu() returns NULL. load_gpu() re-attempts on every DRM open while priv->gpu is NULL, each open fails identically, and PAS cannot become available in between - which is why the error repeats and userspace stays on llvmpipe. Move the availability check into zap_shader_load_mdt(), behind the zap-shader node lookup, so the driver only consults PAS once it knows it needs PAS. Boards with no zap-shader node take the intended -ENODEV fallback without ever asking, and boards that do have one keep the qcom_pas_is_available() gate. Fixes: 0be72be03ca7 ("drm/msm: Switch to generic PAS TZ APIs") Link: https://lore.kernel.org/r/20260808034716.58888-1-phollinsky@holtechnik.com Signed-off-by: Paul Hollinsky <phollinsky@holtechnik.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/747583/ Message-ID: <20260821081325.89088-1-phollinsky@holtechnik.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
12 daysMerge tag 'rust-dma-7.4-rc1' of ↵Danilo Krummrich
git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core into drm-rust-next rust: dma: tie DMA allocations to the device's bound lifetime DMA allocations carry device resources (e.g. IOMMU mappings) that must not outlive the device's bound lifetime. Add lifetime parameters to the DMA allocation types (Coherent, CoherentBox, CoherentHandle) to enforce at compile time that they are freed before the device is unbound. Since DMA types with lifetime parameters are exposed through debugfs in the nova-core driver, first drop the unnecessary T: 'static bound from the debugfs ScopedDir file creation methods by formalizing a type invariant on FileOps. This is a stable tag for other trees to merge. Signed-off-by: Danilo Krummrich <dakr@kernel.org>
12 daysdrm/xe: Guard page-fault worker with runtime PM checkVarun Gupta
During VM teardown, the VM's runtime PM reference is dropped asynchronously, allowing the device to autosuspend while stale page faults belonging to the now-dead VM are still queued. When the page-fault worker later tries to ack one of these, it calls into guc_ct_send_locked() on an already-suspended device, tripping:   Assertion `!xe_pm_runtime_suspended(xe)` failed!   WARNING at xe_device.c:1267 xe_device_assert_mem_access+0x11c/0x140 [xe] A live VM/exec queue always holds a PM reference while it has outstanding work, so if the device is suspended at ack time, the owning context is already gone and the fault is stale. Take a runtime PM reference across the entire pagefault queue worker to safely deliver acks for torn-down VMs. v3: - Move PM ref to the generic xe_pagefault_queue_work using guard(xe_pm_runtime)(xe) instead of tracking it in the GuC backend(Matt Brost). v2: - Hold PM ref across the entire batch (begin/end) instead of per-ack. This prevents the device from autosuspending mid-batch, which would leave write_only acks written but the end flush skipped, and skip counter++, desyncing the cadence check.(Himal) - Add a comment explaining stale faults.(Himal) Fixes: f289f7807119 ("drm/xe: Add xe_guc_pagefault layer") Signed-off-by: Varun Gupta <varun.gupta@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Link: https://patch.msgid.link/20260907050011.497181-2-varun.gupta@intel.com Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
12 daysMerge drm/drm-next into drm-misc-nextThomas Zimmermann
Backmerging to get drm-misc-next up to v7.3-rc2. Requested for commit 3a2c4d55e32a ("treewide: refresh kmalloc_obj() conversions"). Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
13 daysgpu: nova-core: mm: Add PRAMIN aperture self-testsJoel Fernandes
Add self-tests for the PRAMIN aperture mechanism to verify correct operation during GPU probe. The tests validate various alignment requirements and corner cases. The tests are default disabled and behind CONFIG_NOVA_CORE_SELFTESTS. When enabled, tests run after GSP boot during probe. Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> [ecourtney: convert the tests to window_at(), macros, and the new types] [ecourtney: cfg-gate the tests and expect(dead_code), not a runtime no-op] [ecourtney: run the self-tests on all architectures, drop the chipset arg] [ecourtney: test within a usable FB region, skip when none is large enough] [ecourtney: report failures without failing probe, start banner at dev_dbg] [ecourtney: removed the mm-specific Kconfig option] Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260827-pramin-split-v3-10-24b24d7afc52@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
13 daysgpu: nova-core: Add self-test assertion macros and config optionEliot Courtney
The existing assert! and assert_eq! macros cause a panic. For self tests in nova-core, it's inconvenient to cause a panic since these need to be run on actual hardware. Instead, define similar macros that log an error then return an Err. Also add the NOVA_CORE_SELFTESTS Kconfig option that gates the driver self-tests. Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260827-pramin-split-v3-9-24b24d7afc52@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
13 daysgpu: nova-core: mm: Add GpuMm centralized memory managerJoel Fernandes
Introduce GpuMm as the centralized GPU memory manager. At this point in the series, GpuMm only owns the PRAMIN window for direct VRAM access; the buddy allocator and TLB manager are added later when those backing types become available. This provides a clean ownership model where GpuMm provides accessor methods for its components that can be used for memory management operations, and lets follow-on patches (such as the PRAMIN aperture self-tests) reference `pramin_mut()` cleanly. Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> [ecourtney: squash the total VRAM end patch, drop its dev_info print] [ecourtney: take the maximum FB limit before adding one, fail with EINVAL] [ecourtney: rebase for the Bar0 lifetime and ownership changes, drop Arcs] [ecourtney: source the chipset through gsp_resources] [ecourtney: build the VRAM region in new(), pramin() becomes pramin_mut()] [ecourtney: declare mm before gsp_resources, doc wording cleanups] Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260827-pramin-split-v3-8-24b24d7afc52@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
13 daysgpu: nova-core: mm: Add support to use PRAMIN windows to write to VRAMJoel Fernandes
PRAMIN apertures are a crucial mechanism for direct CPU read/write to VRAM. Add a `Pramin` manager whose `window_at()` returns a typed MMIO view of VRAM through the 1 MiB PRAMIN aperture in BAR0, validating the view against the VRAM region and repositioning the window as needed for the accessed address. A view borrows `Pramin` mutably, so the window cannot move while the view is in use, and it inserts an ordering point on Drop. Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> [ecourtney: split the registers and HAL into the two preceding patches] [ecourtney: rebase w.r.t. Bar0 lifetime changes and register projections] [ecourtney: drop the window guard and mutex, use &mut self] [ecourtney: position at init to avoid reads, reposition in window_offset] [ecourtney: return typed MMIO views instead of read/write accessors] [ecourtney: insert an ordering read when a view drops] [ecourtney: declare the window location, drop the doc examples] [ecourtney: add the copyright header, doc and naming cleanups] [ecourtney: the pramin module is mm-internal] Co-developed-by: Eliot Courtney <ecourtney@nvidia.com> Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260827-pramin-split-v3-6-24b24d7afc52@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
13 daysgpu: nova-core: mm: Add the memory management HALEliot Courtney
Positioning the PRAMIN window requires writing an architecture-specific register: `NV_PBUS_BAR0_WINDOW` on Turing, Ampere and Ada, and `NV_XAL_EP_BAR0_WINDOW` with a different field width on Hopper and on Blackwell. A `MmHal` trait with one implementation per hardware family hides the register choice from the rest of the mm code, matching the layout of the driver's other HALs. Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260827-pramin-split-v3-4-24b24d7afc52@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
13 daysgpu: nova-core: mm: Add PRAMIN window registersJoel Fernandes
PRAMIN apertures are a crucial mechanism for direct CPU read/write to VRAM. Add the BAR0 window registers that position the PRAMIN aperture on all supported GPU architectures: Turing, Ampere, Ada (via `NV_PBUS_BAR0_WINDOW`), Hopper (via `gh100::NV_XAL_EP_BAR0_WINDOW`), and Blackwell (via `gb100::NV_XAL_EP_BAR0_WINDOW`). Hopper/Blackwell window-base registers are based on Eliot Courtney's offlist reference patch. Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> [ecourtney: split the registers out of the PRAMIN patch into mm/regs.rs] [ecourtney: drop the register read path] [ecourtney: reword the message for the split, narrow visibility to mm] [ecourtney: plain base fields, as the bitfield cast+shift patch is dropped] [ecourtney: rename the target to VidMem, fix derives, redo the target docs] [ecourtney: annotate the register base types] Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260827-pramin-split-v3-3-24b24d7afc52@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
13 daysgpu: nova-core: mm: Implement Alignable and Debug for VramAddressEliot Courtney
Later patches align VRAM addresses down to the PRAMIN window. Implement `Alignable` trait for `VramAddress` and plus add a `ZERO` constant. Also print the address in hex under `{:?}`, so it reads well in debug output. Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260827-pramin-split-v3-2-24b24d7afc52@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
13 daysgpu: nova-core: mm: Add VramAddress typeJoel Fernandes
Add the `VramAddress` type representing a physical address in VRAM. Also add an arithmetic helper, comparison, and operator overloads which are required in later patches for address arithmetic. Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> [ecourtney: create mm.rs here, squashing in the arithmetic patch] [ecourtney: splice the two commit bodies] [ecourtney: drop the Pfn fields, open-coding what bitfield! generated] [ecourtney: drop align_down and the IntoVramOffset/IntoVramRange traits] [ecourtney: make checked_add() const over a plain u64, derive the ordering] [ecourtney: doc wording, header, import, and signature cleanups] Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260827-pramin-split-v3-1-24b24d7afc52@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
13 daysMerge tag 'rust-io-7.4-rc1' of ↵Danilo Krummrich
git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core into drm-rust-next rust: io: support register projections and remove relative registers Currently registers work for all untyped I/O regions, which is not ideal. It allows registers defined for device A to work for another device B and there is no safeguarding at all. Change this by requiring a base type for registers. `register!` can still define registers on untyped `Region`s, although users would need to do so explicitly and supply a concrete type. This change makes it possible to use projection for relative registers; relative registers can be implemented by defining new types for the I/O subregions and just define registers for these subregion types like normal registers. This actually results in more ergnomic code for users of relative registers (currently only nova-core), because non-array registers can be written to with #[...] struct Subregion(...); register! { base: MyBase; SUBREGION: Subregion @ ...; } register! { base: Subregion; REG(u32) @ .. { .. } } let subregion = io_project!(bar, build: SUBREGION); subregion.read(REG) subregion.write_reg(reg) instead of struct SubregionType; struct Subregion; impl RegisterBase<SubregionType> for Subregion { const BASE: usize = ...; } register! { REG(u32) @ Subregion + .. { .. } } bar.read(REG::of::<Subregion>()) bar.write(WithBase::of::<Subregion>(), reg) This also allows a lot more code sharing between I/O projection and `register!` macro. The expressiveness power of Rust declarative macros is becoming limiting, so it is converted to a proc macro before new features being added to it. This is a stable tag for other trees to merge. Signed-off-by: Danilo Krummrich <dakr@kernel.org>
13 daysgpu: nova-core: convert hshub0 from relative register to projectionGary Guo
Similar to the PFALCON and PFALCON2 conversion, the hshub0 relative access can also be achieved cleanly with projection and a new base. Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Gary Guo <gary@garyguo.net> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://patch.msgid.link/20260901-typed_register-v4-13-5552b1d59525@garyguo.net [ Split nested import into kernel vertical style. - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
13 daysgpu: nova-core: use projection for PFALCON and PFALCON2 registersGary Guo
Add fixed size region types `PFalconRegisters` and `PFalcon2Registers` and update PFALCON and PFALCON2 registers to be fixed register on them and not relative registers on `NovaRegisters`. Update `Falcon` struct to store projected views when constructing and access with `self.pfalcon` and `self.pfalcon2`. Signed-off-by: Gary Guo <gary@garyguo.net> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://patch.msgid.link/20260901-typed_register-v4-12-5552b1d59525@garyguo.net Signed-off-by: Danilo Krummrich <dakr@kernel.org>
13 daysdrm/tyr: specify base type for registersGary Guo
All registers use the same base type, which is `<IoMem as IO>::Target`. Thus add the base parameter to `register!` invocation. Signed-off-by: Gary Guo <gary@garyguo.net> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://patch.msgid.link/20260901-typed_register-v4-8-5552b1d59525@garyguo.net Signed-off-by: Danilo Krummrich <dakr@kernel.org>
13 daysgpu: nova-core: specify base type for registersGary Guo
All registers use the same base type, which is `<Bar0 as IO>::Target`. Thus add the base parameter to `register!` invocation. Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Gary Guo <gary@garyguo.net> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://patch.msgid.link/20260901-typed_register-v4-7-5552b1d59525@garyguo.net Signed-off-by: Danilo Krummrich <dakr@kernel.org>
14 daysMerge tag 'kmalloc_obj-v7.3-rc2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux Pull kmalloc_obj conversions from Kees Cook: "Another run of the Coccinelle script for converting kmalloc() family of allocations to kmalloc_obj() via the existing rules in scripts/coccinelle/api/kmalloc_objs.cocci" * tag 'kmalloc_obj-v7.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux: treewide: refresh kmalloc_obj() conversions drm/amd/display: Fix harmless type mismatch in allocation
14 daysgpu: nova-core: gsp: fix a broken doc link on GspMessageJohn Hubbard
The doc comment on the GSP message type names Cmdq as the type that defines wait_for_msg. That method belongs to CmdqInner, so the link has no target. Nothing catches the break, because rustdoc resolves a link only in an item it documents, and the kernel's rustdoc run skips private items. Point the link at CmdqInner. Assisted-by: LLM Signed-off-by: John Hubbard <jhubbard@nvidia.com> Reviewed-by: Gary Guo <gary@garyguo.net> Link: https://patch.msgid.link/20260905023800.1293631-1-jhubbard@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-09-04treewide: refresh kmalloc_obj() conversionsKees Cook
This is another run of the Coccinelle script for converting kmalloc() family of allocations to kmalloc_obj() via the existing rules in scripts/coccinelle/api/kmalloc_objs.cocci This catches both the set of kmalloc() uses added since the first kmalloc_obj() conversions in v7.0 and adds a large group missed in the first pass due to Coccinelle not interacting well with the cleanup.h scoped_...() family of macros[1]. I worked around this with spatch's "--macro-file" argument to a file with all the scoped_...() macros mapped to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control flow indicator I could find. Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc, riscv, and s390 with no new warnings. Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1] Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2] Signed-off-by: Kees Cook <kees+treewide@kernel.org>
2026-09-04drm/amd/display: Fix harmless type mismatch in allocationKees Cook
While converting to kmalloc_obj() API, a type assignment mismatch was found between the desired struct dcn42_resource_pool and the allocated struct dcn401_resource_pool. Fix the type (it is harmless: the objects have the same contents and size). Signed-off-by: Kees Cook <kees@kernel.org> --- Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Rodrigo Siqueira <siqueira@igalia.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@gmail.com> Cc: Simona Vetter <simona@ffwll.ch> Cc: Dan Wheeler <daniel.wheeler@amd.com> Cc: Roman Li <Roman.Li@amd.com> Cc: Ovidiu Bunea <ovidiu.bunea@amd.com> Cc: Charlene Liu <Charlene.Liu@amd.com> Cc: Leo Chen <leo.chen@amd.com> Cc: Ivan Lipski <ivan.lipski@amd.com> Cc: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Cc: <amd-gfx@lists.freedesktop.org> Cc: <dri-devel@lists.freedesktop.org>
2026-09-04rust: dma: tie Coherent and CoherentBox to the device's bound lifetimeDanilo Krummrich
Add a lifetime parameter to Coherent and CoherentBox that ties the DMA allocation to the device's bound scope, ensuring it is freed before the device is unbound. DMA allocations carry device resources (e.g. IOMMU mappings) that must not outlive the device's bound lifetime. Without a lifetime parameter, there was no compile-time enforcement that a Coherent or CoherentBox is dropped before the device is unbound. Propagate the new lifetime parameter through all users. Reviewed-by: Gary Guo <gary@garyguo.net> Link: https://patch.msgid.link/20260830193824.471089-5-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-09-04rust: dma: tie CoherentHandle to the device's bound lifetimeDanilo Krummrich
Add a lifetime parameter to CoherentHandle that ties the DMA allocation to the device's bound scope, ensuring it is freed before the device is unbound. DMA allocations carry device resources (e.g. IOMMU mappings) that must not outlive the device's bound lifetime. Without a lifetime parameter, there was no compile-time enforcement that a CoherentHandle is dropped before the device is unbound. Reviewed-by: Gary Guo <gary@garyguo.net> Link: https://patch.msgid.link/20260830193824.471089-3-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-09-04Merge tag 'drm-xe-fixes-2026-09-03' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes A small fix on the error handling of an OA uapi and the addition of a drm_info message to report FLAT_CSS base misalignment. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/apnVOtDv4WAIoj_X@intel.com
2026-09-04Merge tag 'amd-drm-fixes-7.3-2026-09-03' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/amdgpu/kernel into drm-fixes amd-drm-fixes-7.3-2026-09-03: amdgpu: - SR-IOV fix - GFX8 fix - MES queue reset fix - GPUVM fixes - DCN 6 warning fix - DCN 3.5/3.6 fix - DML fix - Backlight fix - Colorop fix - DC get_estimated_bw() fix - devcoredump fix - Userq fixes - APU PSP fix - Cursor fix amdkfd: - MES queue eviction fix - MQD debugfs fix UAPI: - Fix for drm_amdgpu_info_device with mixed 64 bit kernel and 32 bit userspace Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260903174712.584320-1-alexander.deucher@amd.com
2026-09-04Merge tag 'drm-intel-fixes-2026-09-03' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes drm/i915 fixes for v7.3-rc2: - Drop an accidentally duplicated panel fitter call in DP MST - Fix DDI clock programming for Cx0 and LT PHY - Fix PTL CDCLK handling at probe, causing a glitch - Fix dg2_power_well_count() return type - Fix a NULL pointer deref at forced probe - Fix selective fetch disable Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/affe11af9d5eb9dc6f906441495cb843f9d4817c@intel.com
2026-09-03drm/xe: Add fault-inject based VRAM page offline injectionTejas Upadhyay
Add a fault-inject based debugfs interface for testing VRAM page offlining. This replaces the previous standalone debugfs approach with the standard kernel fault-inject infrastructure. Two debugfs entries are created under the xe debugfs root for CRI platforms: - inject_mempage_offline/: Standard fault-inject knobs (probability, times, interval, etc.) created by fault_create_debugfs_attr(). Without CONFIG_FAULT_INJECTION_DEBUG_FS, the stub returns ERR_PTR(-ENODEV) and no knobs are created, making the trigger effectively a no-op. - inject_mempage_offline_trigger: Write a PFN value to inject a specific page, or write "0" to auto-pick the last unallocated VRAM page The trigger accepts: - "0" : auto-pick last unallocated page - "0xPFN" : inject fault at a specific PFN address Usage: echo 100 > inject_mempage_offline/probability echo 1 > inject_mempage_offline/times echo 0 > inject_mempage_offline_trigger probability: likelihood of should_fail() returning true (0-100) times: number of times injection is allowed (-1 for unlimited) v7: - Use PAGE_SIZE v6(Himal): - Add warning to rebind driver post test run v5(Sashiko): - exclude SRIOV and remove dpa_base addition, already absolute dpa v4(Himal): - Use xe_fault_mempage_offline() instead of IS_ENABLED() + direct should_fail(). CONFIG_FAULT_INJECTION_DEBUG_FS is now an implicit requirement for the trigger to function. v3(Himal): - Use FAULT_ACTION v2(sashiko): - use cond_resched() - validate input first and fix addr < 0 case - validate vr, move block, found var as local to scope_guard Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-32-tejas.upadhyay@intel.com
2026-09-03drm/xe/uapi: Expose ban reason in EXEC_QUEUE_GET_PROPERTY_BANTejas Upadhyay
Extend DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN to return a bitmask indicating the reason for the ban, rather than a simple boolean. This allows userspace to distinguish between different ban causes: - DRM_XE_EXEC_QUEUE_BAN_REASON_GPU_HANG (bit 0): exec queue was banned due to a GPU hang or job timeout detected by the TDR. - DRM_XE_EXEC_QUEUE_BAN_REASON_PAGE_OFFLINE (bit 1): exec queue was banned because a VRAM page backing its resources was taken offline. The ban_reason field is added to struct xe_exec_queue and set at the point where the ban is triggered: - In guc_exec_queue_timedout_job() for GPU hang. - In xe_ttm_vram_purge_page() for memory page offline, before calling xe_exec_queue_kill() or xe_vm_kill(). The reset_status op is updated to return u64 with the reason bitmask. When a queue is banned but no explicit reason was recorded (e.g., from a generic CAT error), it defaults to GPU_HANG for backward compatibility. A value of 0 means the exec queue is not banned. v5 (Sashiko/MattB): - Take the write lock for the traversal to tag ban_reason v4(Sashiko): - Add ban reason for non-LR exec queues - Add TODO for multiqueue v3(Rodrigo): - Add doc in xe_drm.h v2(Sashiko): - Use atomic_t for ban_reason to fix concurrent updates from TDR and page-offline - Guard GPU_HANG bit with !exec_queue_killed to avoid masking page-offline reason - Clear ban_reason on queue recovery (clear_exec_queue_banned path) - Use atomic_read in guc_exec_queue_reset_status for lockless read Assisted-by: Copilot:claude-opus-4.6 Acked-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Michal Mrozek <michal.mrozek@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-31-tejas.upadhyay@intel.com
2026-09-03drm/xe: Expose bad VRAM pages via debugfsTejas Upadhyay
Add a debugfs file "vram_bad_pages" that shows offlined and queued VRAM pages across all tiles. Each entry displays the page frame number, GPU page size, and status flag (R=reserved, P=pending, F=failed). example, cat /sys/kernel/debug/dri/0/vram_bad_pages max_pages: 10000 0x0000000000000000 : 0x0000000000001000 : R 0x0000000000001234 : 0x0000000000001000 : P 0x0000000000080000 : 0x0000000000001000 : R ← tile 1 addr v3(Michal): -add kernel doc v2(Sashikoi/Michal/Himal): -Remove block iteration, use offline and queue list only -Move platform check inside api Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-30-tejas.upadhyay@intel.com
2026-09-03drm/xe/vram: Check disable_vram_page_offline policy in fault handlerTejas Upadhyay
Before reserving a page at a faulting address, check the cached disable_vram_page_offline policy from xe->ras. If the policy is enabled (logging only), log the corrupted address and return -EOPNOTSUPP so that RAS can report to firmware to drop the address from the SRAM queue without attempting to offline the page. Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-29-tejas.upadhyay@intel.com
2026-09-03drm/xe/ras: Cache disable_vram_page_offline policy at initTejas Upadhyay
The configfs disable_vram_page_offline attribute can only be set before device bind, so its value is immutable at runtime. Cache it in struct xe_drm_ras during xe_ras_init() to avoid repeated configfs lookups on every fault. Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-28-tejas.upadhyay@intel.com
2026-09-03drm/xe/configfs: Add disable_vram_page_offline attributeTejas Upadhyay
Add a new configfs attribute 'disable_vram_page_offline' to control how bad VRAM pages are handled: 0, n, N, false - Do not disable (Offlining is active - default) 1, y, Y, true - Disable vram page offline (Logging only) The attribute can only be set before binding to the device and defaults to false (offlining enabled). This gives administrators control over whether corrupted VRAM pages detected by hardware (e.g., ECC errors) are actively offlined or only logged. v3(Sashiko): - fix doc v2(Sashiko): - keep default value in case configfs not present Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-27-tejas.upadhyay@intel.com
2026-09-03drm/xe/vram: Add VRAM page offline fault handlerTejas Upadhyay
Add the core VRAM page offlining logic to handle HW-reported faulty physical addresses: - xe_ttm_vram_purge_page(): Purges the BO containing the faulty address. Bans the associated VM (if page table BO) and exec queue (if LRC BO). Moves xe_exec_queue_kill() outside xe_bo_lock() to avoid AB-BA deadlock with vm->lock. Uses READ_ONCE(bo->q) to safely access the exec queue pointer. - xe_ttm_vram_page_already_processed(): Checks if an address is already tracked in offlined_pages or queued_pages lists to avoid double-processing. - xe_ttm_vram_reserve_page_at_addr(): Two-phase reservation that first queues the page, purges the BO outside the lock, then reserves the buddy block. Handles both allocated (BO present) and free page cases. Returns -EIO for critical kernel BOs to trigger system reset. - xe_ttm_vram_addr_to_region(): Maps a DPA to its corresponding VRAM region. Checks if the address falls within usable space, or infrastructure zones (CCS, GSM, DSM) where it returns NULL to flag a reset path. If the target address is outside any known region returns ERR_PTR(-EOPNOTSUPP) - xe_ttm_vram_handle_addr_fault(): Entry point called by RAS. Returns -EEXIST if already processed, -EIO for GSM/critical BO, -EOPNOTSUPP if out of bounds. v15: - Add immediate reservation for free pages - Use lock before accessing tbo v14(Sashiko/MattB): - Retry queued pages during xe_ttm_vram_mgr_del() - Move all changes to find owner of bo to its API v13(Himal): - Remove redundant code v12(Sashiko): - Handle multi tile and add assert for 4K align - Remove unaligned action comment for ENXIO v11(Himal): - match everywhere with enum vs bool for status member - Fix comment and remove unused var - if purge fail let next alloc confirm failure - pass absolute address, useful for multi tile Assisted-by: Copilot:claude-opus-4.6 Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-26-tejas.upadhyay@intel.com
2026-09-03drm/xe/vram: Add page offline data structures and lifecycleTejas Upadhyay
Add xe_ttm_vram_offline_resource to track individual offlined VRAM pages, and extend xe_ttm_vram_mgr with offlined_pages/queued_pages lists and their counters. Initialize the lists in __xe_ttm_vram_mgr_init() and add xe_ttm_vram_free_bad_pages() to release all tracked pages during xe_ttm_vram_mgr_fini() teardown. v3(Sashiko): - Reorder xe_ttm_vram_buddy_free and list_del_rcu - Introduce reservation status v2(Himal): - Address possible leak in xe_ttm_vram_mgr_fini() - Remove unused dev and add comment for used_visible_size 0 Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-25-tejas.upadhyay@intel.com
2026-09-03drm/xe/vram: Extract buddy allocation and free helpersTejas Upadhyay
Factor out xe_ttm_vram_buddy_alloc() and xe_ttm_vram_buddy_free() from xe_ttm_vram_mgr_new() and xe_ttm_vram_mgr_del(). These new helpers consolidate block allocation/deallocation with visible-size tracking. This modularization makes the logic reusable by the upcoming VRAM page offlining reservation path. No functional change. Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-24-tejas.upadhyay@intel.com
2026-09-03drm/xe: Guard teardown paths against purged BOsTejas Upadhyay
VRAM page offlining can purge BOs that are still referenced by page tables, exec queues, and DMA-buf exports. Add xe_bo_is_purged() guards in the teardown paths to prevent unpinning or mapping an already-purged BO: - xe_bo_unpin_map_no_vm(): skip unpin if purged - xe_dma_buf_map(): return -ENOENT early if purged - xe_exec_queue_update_run_ticks(): skip LRC timestamp read if purged - xe_pt_destroy(): skip unpin if purged v4(Sashiko): - Move bo purge check in xe_bo_unpin() to handle all instances v3(Sashiko): - Remove dma_resv is already held v2(Himal): - take dma_resv lock before calling xe_bo_is_purged() Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-23-tejas.upadhyay@intel.com
2026-09-03drm/xe/bo: Make xe_bo_is_user() publicTejas Upadhyay
Export xe_bo_is_user() so it can be used by the VRAM page offline code to distinguish user-created BOs from kernel BOs when deciding whether a faulty page can be safely purged or requires a full reset. Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-22-tejas.upadhyay@intel.com
2026-09-03drm/xe: Handle NULL resource and allow purging of VRAM pagesTejas Upadhyay
Add NULL checks for the buffer object's resource pointer in xe_bo_is_vram() and xe_bo_is_stolen() to prevent potential NULL pointer dereferences when checking memory location during page offlining. Additionally, remove the `!ttm_bo->ttm` check from xe_ttm_bo_purge(). This restriction is stripped away to explicitly allow the driver to purge VRAM pages during the memory page offline sequence. v2(Sashiko): - Split export and this patch also Check NULL res in xe_bo_is_vram() and xe_bo_is_stolen() Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-21-tejas.upadhyay@intel.com
2026-09-03drm/xe: Export xe_ttm_bo_purge()Tejas Upadhyay
Remove the static qualifier from xe_ttm_bo_purge() and add its prototype to xe_bo.h. This allows the function to be called from other parts of the driver outside of xe_bo.c, specifically needed for the memory page offline feature. Cc: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Arvind Yadav <arvind.yadav@intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-20-tejas.upadhyay@intel.com
2026-09-03drm/xe: Link LRC BO and its execution queue with safe lifetime rulesTejas Upadhyay
Introduce an execution queue back-pointer (`q`) within `struct xe_bo`, primarily for Logical Ring Context (LRC) Buffer Objects. This back-pointer allows the driver to identify and execute targeted corrective actions on a specific queue if its associated LRC BO encounters errors like memory corruption or eviction. Because this back-pointer takes no reference on its target execution queue, strict lifetime and serialization rules are implemented to prevent concurrent readers from encountering use-after-free or dangling pointer bugs: - Encapsulate tracking logic inside xe_exec_queue_set_lrc_bo_backpointer() and xe_exec_queue_clear_lrc_bo_backpointer(). - Explicitly wrap all back-pointer writes and clears under the BO's dma_resv lock via xe_bo_lock(). Readers must hold this same lock across both the pointer read and its subsequent xe_exec_queue_get_unless_zero() call to guarantee serialization against teardown. - Defer publishing the back-pointer until the very end of xe_exec_queue_create(). This ensures that early initialization failure paths (which bypass the kref mechanism and immediately free the queue structure) never leak a transient pointer to concurrent readers. - Clear the back-pointer at the absolute top of __xe_exec_queue_fini(). This strips the pointer before q->ops->fini() destroys the hardware backend, ensuring that any reader holding the BO lock either observes a fully functional queue or NULL. For multi-queue engines, secondary LRC BOs safely point to the primary queue, which is guaranteed to outlive the teardown pass due to active references held by its secondaries. V4 (MattB): - Add LRC BO's execution queue safe lifetime rules V3 (Sashiko): - Use 8-byte placeholder structure compatibility for non-LRC BO cases. - Wrap assignments and clears securely under dma_resv locks. V2 (Matt B): - Add native support handling multi-queue configuration tracking. Assisted-by: Copilot:claude-opus-4.6 Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-19-tejas.upadhyay@intel.com
2026-09-03drm/xe: Link VRAM resource allocation with gpu buddyTejas Upadhyay
Setup to link allocation resource structure inside gpu buddy. This functionality is critical for supporting the memory page offline feature on CRI, where identified faulty pages must be traced back to their originating buffer for safe removal. v3(MattB): store memory resource(res) instead of tbo V2(MattB): Clear block->private in xe_ttm_vram_mgr_del as well Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-18-tejas.upadhyay@intel.com
2026-09-04drm/panic: clean new `clippy::needless_range_loop` lint for Rust 1.100.0Miguel Ojeda
Starting with Rust 1.100.0 (expected 2026-11-12), Clippy warns: warning: the loop variable `i` is only used to index `self.decimals` --> drivers/gpu/drm/drm_panic_qr.rs:410:18 | 410 | for i in 0..len { | ^^^^^^ | note: for this index operation --> drivers/gpu/drm/drm_panic_qr.rs:411:13 | 411 | self.decimals[i] = (chunk % 10) as u8; | ^^^^^^^^^^^^^^^^ = help: for further information visit https://rust-lang.github.io/rust-clippy/main/index.html#needless_range_loop = note: `-W clippy::needless-range-loop` implied by `-W clippy::all` = help: to override `-W clippy::all` add `#[allow(clippy::needless_range_loop)]` help: consider using an iterator | 410 - for i in 0..len { 410 + for <item> in self.decimals.iter_mut().take(len) { | The lint did not trigger here before because it could not handle arrays behind a field access such as `self.decimals` -- Clippy was improved to catch those cases [1][2]. Thus clean the warning by iterating over a slice rather than using `take()` so that an out-of-range `len` still triggers the same bounds check as the indexed loop. Cc: stable@vger.kernel.org # Needed in 6.18.y and later. Link: https://github.com/rust-lang/rust-clippy/issues/16631 [1] Link: https://github.com/rust-lang/rust-clippy/pull/16634 [2] Assisted-by: LLM Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260826145642.43807-1-ojeda@kernel.org Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
2026-09-03drm/xe/vm: Add srcid to xe_vm_get_property_ioctl fault reportJonathan Cavitt
Add the SRCID of the faulting hardware unit to the return of the xe_vm_get_property_ioctl fault report. v2: - Readd pad check, as the pad in the ioctl struct was not changed (jcavitt) v3: - Squash SRCID with ASID to keep the struct compact (Matthew) Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: David Airlie <airlied@gmail.com> Cc: Simona Vetter <simona@ffwll.ch> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260902214358.348399-3-jonathan.cavitt@intel.com
2026-09-03drm/xe/pagefault: Add SRCID to pagefault structJonathan Cavitt
Add SRCID information to pagefault struct for the purpose of reporting the hardware unit that resulted in the pagefault. v2: - Squash SRCID with ASID to keep the struct compact (Matthew) v3: - Use BUILD_BUG_ON and move ASID definition in one function (Matthew) v4: - Various formatting fixes Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: David Airlie <airlied@gmail.com> Cc: Simona Vetter <simona@ffwll.ch> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260902214358.348399-2-jonathan.cavitt@intel.com
2026-09-03drm/xe/vram: report FLAT_CCS base misalignmentMatthew Auld
So we can easily check if a machine had the CCS bug, when looking back over bug reports where we have the same machine with newer kernel. Example print for a machine with the CCS bug: FLAT_CCS base:27bbff800, aligned:no v2 (Matt B): - Unconditionally print the base + alignment Fixes: 37173392741c ("drm/xe/vram: fix ccs offset calculation") Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: stable@kernel.org Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260902124117.918018-9-matthew.auld@intel.com (cherry picked from commit d00b7f4f03bbeb2efad872f1686130e18c2b4141) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-19 17:14:55 +0000