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path: root/drivers/gpu
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2026-08-25drm/amdkfd: gfx12.1 add no-op prefetch on trap entryJay Cornwall
VMEM instructions may hang after trap exit. Issue a no-op prefetch to reset wave VMEM state. v2: squash in preserve SCC on trap entry Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Cc: Joseph Greathouse <joseph.greathouse@amd.com> Cc: Michael Chen <michael.chen@amd.com> Cc: Lancelot Six <lancelot.six@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdkfd: enable trap ID work aroundJames Zhu
on gfx12.1 trap handler Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdkfd: add stochastic in 1st trap handlerJames Zhu
to support gfx12.1.0 PC Sampling. Co-authored-by: Lancelot SIX <Lancelot.Six@amd.com> Co-authored-by: Jay Cornwall <jay.cornwall@amd.com> Co-authored-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Vladimir Indic <Vladimir.Indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdkfd: enhance host trap process in 1st trap handlerJames Zhu
to support multiple processes, and process correctly when s_trap and context saving exception occur simultaneously. -v2: update comments advised from Lancelot -v3: update advised from Jay -v4: remove state bit S_SAVE_PC_HI_NEED_2ND_LVL_TH_SHIFT -v5: add STATUS.HALT handling Co-authored-by: Lancelot SIX <Lancelot.Six@amd.com> Co-authored-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Lancelot SIX <Lancelot.Six@amd.com> Reviewed-by: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Skip showing available NPS modesLijo Lazar
Dynamic memory partition switch is not supported on CPU-GPU xgmi connected configurations. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: skip DPX mode for unsupported GC partsMangesh Gadre
DPX is unsupported on GC 9.4.3/9.4.4/9.5.0 skip these 6-XCC parts,so do not advertise it. Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add DPX mode for 6-XCC configurationMangesh Gadre
Add DPX to the 6-XCC supported mode mask This allows DPX to be advertised and selected Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add NPS2 memory cap for soc v1.0 DPX modeLe Ma
DPX currently advertises only NPS1 as a compatible memory partition mode in soc_v1_0_get_xcp_res_info(). As a result, supported_nps_configs and amd-smi partition --accelerator report NPS1 for the DPX profile even when the device supports both NPS1 and NPS2. Include NPS2 in the DPX compatible NPS mask so the reported profile capabilities match the supported memory partition modes. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: free memory partition info on gmc v12 sw_finiLe Ma
Reset the partition count and free the buffer on gmc v12 sw_fini during driver unload. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add memory partition sysfs init/fini for GC 12.1.0Le Ma
Add the nps sysfs node for GC 12.1.0 Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: init NPS supported modes for GC 12.1.0Le Ma
Add nps supported modes init for gc 12.1.0 Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Init soc_v1_0 rev_id from IP discovery die_idHoratio Zhang
Software components need to detect die revisions in order to apply the correct software workarounds. During system boot, ASP firmware reads the IDCODE values from the MID, AID and XCD fuses and encodes the die revision into die_info[0].die_id in the IP discovery blob. v2: Default die_rev_id to 0 and warn instead of failing probe when IP discovery does not provide a die rev id. v3: Update names for external_rev_id enumerators. Signed-off-by: Horatio Zhang <hongkun.zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: handle LSDMA instance and harvest information from ip discoveryLe Ma
Track discovered LSDMA instances in inst_mask and clear harvested instances when processing the harvest table. Report the harvest state through IP discovery sysfs for LSDMA v7.1.0. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: handle MMHUB harvest information from ip discoveryLe Ma
Clear harvested MMHUB instances from mmhub.inst_mask when processing the harvest table. Report the harvest state through IP discovery sysfs for MMHUB v4.2.0. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu/discovery: skip MEM_RESERVED_INFO on unsupported ASICsFeifei Xu
Some ASICs' MEM_RESERVED_INFO table_entry may carry non-zero garbage, causing signature check failed thus probe fail. Move signature check in amdgpu_discovery_get_mem_reserved_info_table(), returning -ENOENT when invalid so the table is skipped. v1->v2: Add discovery binary header check before populate the mem_reserved_info table. (Lijo) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Candice Li <candice.li@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add mem_reserved_info sysfs attributeFeifei Xu
Expose the cached MEM_RESERVED_INFO discovery table via a per-device sysfs file: /sys/class/drm/cardX/device/mem_reserved_info The file is read-only and dumps every region as: list_num=<N> [<i>] id=<id> (<name>) size=0x<size> start=0x<start> Only created when the table was successfully resolved at discovery init time. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add amdgpu_discovery_dump_mem_reserved_info_tableFeifei Xu
Walk the cached MEM_RESERVED_INFO table once at discovery init time and log every entry (region id, symbolic name, size, start). Add for debugging purpose. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: query the reserved info with get_fw_reserved_infoFeifei Xu
Extend amdgpu_ttm_init_fw_resv_region() to honour the ->get_fw_reserved_info(). Previously the FW carveout was hardcoded and placed at the top of VRAM (real_vram_size - reserve_size): - a hard-coded 144/256 MB for GC 12.1.0; - or DISCOVERY_TMR_OFFSET fallback. The hard-coded GC 12.1.0 path is replaced by ->get_fw_reserved_info(), which returns a (size, offset_within_VRAM) pair derived from the MASTER_DIE_UMF_REGION embedded in IP discovery, and falls back only when the discovery region is missing or invalid. v1->v2: Remove !adev->bios check, and call the get_fw_reserved_info interface when it is available. (suggested by Hawking) Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: set reserve_tmr in amdgpu_discovery_get_tmr_infoFeifei Xu
If reading mmDRIVER_SCRATCH_2 returns non-zero, discovery.reserve_tmr is set to true and driver need reserve tmr for firmware. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add get_fw_reserved_info implementationFeifei Xu
Add asic specific callback ->get_fw_reserved_info() that returns the firmware/UMF VRAM carveout as a (size, offset_within_VRAM) pair, and provide the soc v1.0 implementation. Query MASTER_DIE_UMF_REGION_ID from the discovery MEM_RESERVED_INFO table for the carveout size/start. SPECIFIC_PURPOSE_REGION_ID is used to resolve the VRAM base in multi-die layouts where VRAM may not start at the default base. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add amdgpu_discovery_get_mem_reserved_region_by_idFeifei Xu
Add a lookup helper to pass a MEM_RESERVED_REGION_ID and receive the region's start address and size. A static amdgpu_discovery_mem_reserved_region_name() helper is also introduced so debug output can refer to regions by symbolic name rather than raw IDs. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add amdgpu_discovery_get_mem_reserved_info_tableFeifei Xu
Add interface to query the optional MEM_RESERVED_INFO table: - introduce amdgpu_discovery_get_mem_reserved_info_table() which resolves the table from the discovery binary and caches the pointer in adev->discovery.mem_reserved_table so subsequent lookups are cheap; - invoke it once at init time. Missing/invalid table is non-fatal. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Add NPS_INFO case to amdgpu_discovery_table_checkFeifei Xu
Add a NPS_INFO case with check_table=false to skip annoying "invalid ip discovery table id" error. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add MEM_RESERVED_INFO to discovery tableFeifei Xu
MEM_RESERVED_INFO holds the reserved info like size/offset for firmware usage. On soc_v1_0, MASTER_DIE_UMF_REGION_ID is to query UMF reserved region info for master die MPASP. SPECIFIC_PURPOSE_REGION_ID is to query VRAM base. v1->v2: convert // to /* */ and move comments ahead of declarations (per Christian's review) Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add amdgpu_discovery_log_bad_signature helperFeifei Xu
Add a helper that prints the actual vs expected signature for debugging purpose. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: enable RAS on psp v15_0_8Candice Li
Enable psp v15_0_8 RAS support. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Add PSP v15.0.8 interrupt handlerLijo Lazar
Register and add interrupt handler in PSP v15.0.8. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Add psp interrupt handlingLijo Lazar
Add interrupt manager for handling psp interrupts and callbacks to enable/disable psp interrupts. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: add supported aca blocks mappingStanley.Yang
Add dacee_be, ucie_pcs, lsdma aca blocks mapping, add pcs_xgmi aca block info. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/amdgpu: Allow reset init for smu_v15_0_8Asad Kamal
Trigger reset init and fini for smu_v15_0_8 Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/amdgpu: Add soc_v1_0 reset handlerAsad Kamal
Add soc_v1_0 reset handler for mode2 reset v2: Remove XGMI parallel reset dispatch and xgmi_update_topology() call, reset on soc_v1_0 is per-device only. (Lijo) v3: Remove ras as will be plugged later as separate ip. Remove vcn from ip mask as vcn not part of reset sequence yet (Lijo) Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/pm: add 5s custom timeout for unload messagesAsad Kamal
The default SMU message timeout may be too short for the PrepareMp1ForUnload message on smu_v15_0_8, leading to spurious -ETIME errors under load or slow firmware response conditions. Introduce SMU_V15_0_8_MSG_TIMEOUT_US (5 seconds) and apply it to: - smu_v15_0_8_notify_unload(): switch from smu_cmn_send_smc_msg() to smu_cmn_send_smc_msg_with_params_ext() to pass the explicit timeout. v2: Use c2pmsgctl and args directly (Lijo) Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Use 100M as refclock for SOCv1.0Lijo Lazar
When VBIOS is not available, fallback to use 100M for refclock value. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add get_rom_offset callback for NBIO 6.3.2Le Ma
Add the get_rom_offset callback to retrieve the VBIOS ROM offset from REGS_ROM_OFFSET_CTRL for vbios imaging fetching from spirom. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Enable translate further for gc v12_1 v3Hawking Zhang
Enable translate further for gc v12_1 to resolve the tlb reach issue v2: ensure PTE.P is set to 1 for leaf PTE v3: Do not clear the P bit when it has been set on a PDB0 entry by the common VM update code Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Horatio Zhang <hongkun.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: recompute the dw estimate after allocating a new VM update jobYuBiao Wang
amdgpu_vm_sdma_update() keeps the number of free dwords of the current job in a local variable. When the job runs out of room it is committed and a new one is allocated, but that local variable is not refreshed and still describes the job which was just submitted. The stale value is then used to decide how many PTEs fit into the new job. If it happens to be copy_pte_num_dw + 7, or one more than that, the result is zero. copy_pte() encodes the transfer size as count * 8 - 1, so a count of zero asks the engine for a 1GB copy starting inside the IB pool. That runs off the end of the pool, faults on the first unmapped GART page above it and hangs the ring. Re-initialize the estimate from the newly allocated job, which is empty and therefore has its full budget available. Cc: stable@vger.kernel.org Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Report vm fault status HI32 when avaialbleHawking Zhang
VM fault status is 64 bits on gfxhub v12_1 and mmhub v4_2, with fields such as FED located in the upper status register. Add an optional HI32 fault status callback to help identify FED status on gfxhub v12_1 and mmhub v4_2 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Horatio Zhang <hongkun.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Use global addr for mmhub v4_2 reg accessHawking Zhang
Use global SMN addresses for MMHUB v4_2_0 register access across all instances. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Drop BUG_ON in PDE address verification for GFX 12.1Mukul Joshi
Update the address mask to support 52-bits addresses when validating the PDE addresses for GFX 12.1. Currently the address mask was incorrect and only permitted 48-bits addresses. Additionally, drop the BUG_ON() and replace it with code to reset the invalid address and valid bit if the address verification fails. This should help generate a page fault instead of crashing the kernel. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: clean up vm flush func for gc v12_1Likun Gao
Clean up gfx_v12_1_ring_emit_vm_flush function, since PFP_SYNC_ME cmd not support on gc v12_1, and it does not have gfx ring. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd: force remote MTYPE_NC on GFX12.1 mtype_local=0Alex Sierra
Work around this in both the amdgpu GMC and KFD SVM paths by explicitly selecting MTYPE_NC for remote memory when amdgpu_mtype_local is 0. Remove this once rev_id-based AID detection is reliable. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25Revert "drm/amdgpu: Set default xnack mode for gfx_v12.1 A0/B0"Alex Sierra
This reverts commit bfeb7b28e9f8c5d16ab00b60b42559791b16a12c. Revert the rev 0x1 (B0) special case for IP_VERSION(12, 1, 0) that forced noretry_default off. Align GFX12.1.0 with the GC >= 10.3.0 noretry default. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Update no-retry PTE flags for GFX12Mukul Joshi
The current combination of PTE flags to translate a retry fault into a no-retry fault is not valid for GFX12. Use a valid no-retry PTE flags combination that works for GFX 12. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Use mmhub inst_mask for gmc v12_1 vmhub setupHawking Zhang
gmc v12_1 currently derives the number of mmhub vmhubs from the aid_mask when populating vmhubs_mask. This breaks when mmhub is represented by mid and mmhub inst_mask does not match the aid_mask. Iterate over adev->mmhub.inst_mask instead so vmhubs_mask reflects the discovered mmhub instances. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Use discovered mmhub inst_mask for v4_2_0Hawking Zhang
mmhub v4_2_0 used adev->aid_mask as the mid_mask when programming MMHUB instances. That assumption is not valid for products with more AIDs than MIDs. Track discovered MMHUB instances in mmhub.inst_mask and use that mask for mmhub v4_2_0 programming paths. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Fix GMC v12.1.0 MID1 page fault vmhub selectionPhilip Yang
For GMC v12.1.0, the IH cookie NodeID spacing is 8 (MID0=0x0, MID1=0x8), not 4. The wrong divisor caused NPA page faults (node_id=8) to select mmhub2 instead of the correct mmhub1. Fix the divisor from 4 to 8, and add a comment documenting the NodeID to DIE mapping for reference. Warn once if page fault from the vmhub but vmhub print fault status function not initialized because not all hubs are initialized. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdkfd: Skip pairwise CU mask check for GFX12.1Mukul Joshi
GFX12.1 doesn't follow the pair-wise CU mask requirement as is the case for GFX 10,GFX 11 and GFX 12. Currently, the ioctl call is returning error because of this incorrect condition of checking for a pair of CUs to be enabled in the CU mask. Fix the issue by removing this check for GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdkfd: disable debug before retiring MES process context on teardownAlex Sierra
On process teardown, kfd_process_notifier_release_internal() called kfd_process_dequeue_from_all_devices() (which issues the MES SET_SHADER_DEBUGGER process_ctx_flush=1 that retires the process context) before kfd_dbg_trap_disable(). For a process under a debugger, the debug teardown path (kfd_dbg_trap_disable -> kfd_dbg_trap_deactivate) then issues several SET_SHADER_DEBUGGER process_ctx_flush=0 packets (reset wave launch mode, clear debug flags, reset MES debug mode). Because those packets carry the process_context_addr, MES re-adds the process to its scheduler list after the flush had retired it. Teardown then frees proc_ctx_bo, and a later MES scheduling pass dereferences the freed process context, producing a GPUVM page fault (vmid 0, GC_UTCL2) on the freed page. This is intermittent because it depends on an MES pass landing on the process before its GART page is reused. It is specific to the debugger path, where queues are added with skip_process_ctx_clear=1 so the last REMOVE_QUEUE does not clear the context and delisting relies on the flush. Reorder teardown so debug is disabled first, and the process context is flushed/retired last, so nothing re-adds the process after it is retired. kfd_dbg_trap_disable() now runs while queues still exist, which matches the normal live debug-disable ordering. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Fix MES wb status pointer overwriting adjacent wb slotPhilip Yang
status_ptr was declared as u64 * but the WB allocation is only one u32. Writing through a u64 * pointer zeroed 8 bytes, corrupting the adjacent WB slot. Fix by using u32 * to match the actual allocation size. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: move tlb invalidation to mes sched pipeShaoyun Liu
The heavy weight shootdown need special handling in MES sched pipe Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-20 08:14:55 +0000