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2026-07-01drm/amd/display: add GPIO HW translation helpersGuilherme Ivo Bozi
Add generic helpers and lookup table types for GPIO hardware translation. The new helpers provide reusable conversions between GPIO IDs, register offsets and DDC lines, allowing ASIC-specific drivers to replace large switch statements with static lookup tables. No functional changes intended. Signed-off-by: Guilherme Ivo Bozi <guilherme.bozi@usp.br> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Acked-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: remove check for nonexistent CONFIG_HAVE_KGDBEthan Nelson-Moore
drivers/gpu/drm/amd/display/dc/sspl/spl_debug.h checks for CONFIG_HAVE_KGDB or CONFIG_KGDB to determine whether to call kgdb_breakpoint(). CONFIG_HAVE_KGDB has never existed in the kernel. Remove the check for it and retain only the correct check for CONFIG_KGDB. Discovered while searching for CONFIG_* symbols referenced in code but not defined in any Kconfig file. Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Acked-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: avoid large stack allocation in ↵Arnd Bergmann
commit_planes_do_stream_update_sequence The function has two arrays on the stack to hold temporary dsc_optc_config and dsc_config objects. The combination blows through common stack frame warning limits in combination with the other local variables: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:4070:22: error: stack frame size (1352) exceeds limit (1280) in 'commit_planes_do_stream_update_sequence' [-Werror,-Wframe-larger-than] Since neither array is initialized or used outside of the add_link_update_dsc_config_sequence() function, there is no actual need to keep each element around. Replace the arrays with a single instance each to reduce the stack usage to less than half. Fixes: 9f49d3cd7e71 ("drm/amd/display: Implement block sequencing infrastructure for modular hardware operations.") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Acked-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Remove redundant IPS mode case for DCN 4.2Alex Hung
[WHAT] Remove the redundant IP_VERSION(4, 2, 0) case from dm_get_default_ips_mode() since it only reassigns the same DMUB_IPS_ENABLE value already set at initialization. Also remove the corresponding KUnit test. Reviewed-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Promote DC to 3.2.387Taimur Hassan
DC Automatic Code Cutoff Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Acked-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: [FW Promotion] Release 0.1.64.0Taimur Hassan
Added panel polarity feature Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Acked-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Add Debug Option To Enable Per-DPM De-rate UsageAustin Zheng
[Why] DML has been updated to use per-DPM derates when provided but per-DPM de-rates have not been finalized. Need to validate to see what values should be stored in the bounding box. [How] Add debug options to set custom derates per DPM (starting at DPM0) and their values Each entry in the custom derate expects the derates to be stored in the following format: bits 0-7: dram_derate_percent_pixel bits 8-15: fclk_derate_percent bits 16-23: dcfclk_derate_percent bits 24-31 are unused. e.g. Using the value 0x414020 will set the following derates for DPM0 DPM0: 0x20, 0x40, 0x41 for dram, fclk, and dcfclk respectively Note that global derate value will be used if the per-DPM derate is 0. Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Refactor Driver PG's skip PG logicLeo Chen
[Why & How] When driver allows idle optimization, no HW state should be modified further by DC. Refactor the skip PG logic in pg_cntl in DCN42. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Enable HUBP/DPP power gate for DCN42Leo Chen
[Why & How] Enable Driver PG for HUBP and DPP in DCN42. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Remove unnecessary DSCCLK enable during DSC PGLeo Chen
[Why & How] DSCCLK is not required when power gating or ungating the DSC block. Remove the unnecessary DSCCLK enable sequence. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Update ONO PG Workaround for DCN42Leo Chen
[Why & How] There is an updated workaround for PG Repeater issue in DCN42. This PR is addressing the dynamic power gating use cases (Driver PG) to align with the new sequence. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Update LSDMA commands to explicitly handle DCC fieldsAlvin Lee
[Description] - Previously linear copy commands for LSDMA assumed no DCC - Update so that there is explicit assignment for DCC related fields - Caller can 0 out the fields if DCC is not used - For linear copy command don't subtract 1 from the count - this will be done at a lower layer Reviewed-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Add flag to disable dynamic expansion for 12bpcGeorge Shen
[Why] Dynamic expansion is not needed when outputting 12bpc test patterns. [How] Add a debug flag to control disabling dynamic expansion in the case of 12bpc test patterns. Reviewed-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Fix intermittently CRC open failure during active renderingChandana G B
[Why] Opening the CRC data file during active rendering can fail with -EINVAL. Closing the CRC data file with ctrl+C (which will send SIGINT to the kernel and if the wait thread in sleep, kernel will send the -ERESTARTSYS to the wait_for_completion_interruptible_timeout) resulting in intermittently getting -ERESTARTSYS. which will just do the clean up without releasing the vblank reference causing -EINVAL while opening the crc data file in the next iteration [How] Ignoring the ERESTARTSYS as this is a return value for the wait_for_completion_interruptible_timeout() Reviewed-by: Chen-Yu Chen <chen-yu.chen@amd.com> Signed-off-by: Chandana G B <Chandana.GB@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Allow Per-DPM De-rates Instead Of A Single Global ValueAustin Zheng
[Why] Currently only a singular de-rate is used for all DPM levels. The intent was to limit the bandwidth utilization at high DPMs so the display requirements are not competing with other engines for bandwidth. At lower DPMs, the de-rates could be more lenient so more bandwidth can be utilized without the need to increase the DPM level and result in potential power savings. i.e. DPM0 could be achieved on certain display configs instead of DPM1 if de-rates were a couple percentage points higher The system average de-rates can be adjusted as needed as only urgent de-rates are defined for the SOC. [How] Update QOS parameters to have a table of derates with a per-DPM granularity If the per-DPM value is provided, that will value be used. Otherwise use the global value if there is no DPM specific value. Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Disable DPPCLK RCG to fix cursor disappearingKaren Chen
[Why & How] DPP clock is gated when programming the cursor. This change disables DPPCLK RCG in dccg42_init before accessing DPP, ensuring cursor programming latches correctly. Assisted-by: Cursor Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Karen Chen <Karen.Chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu: bounds check atom indirect io methodLijo Lazar
Bound indirect io method execution by the BIOS size to avoid out-of-bounds reads. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: split TF/LUT colorop state lookups into separate upfront phasesHarry Wentland
In __set_dm_plane_colorop_shaper and __set_dm_plane_colorop_blend the single colorop_state variable was reused sequentially: first to capture the TF state, then (after mutating the colorop pointer) to capture the LUT state. Split into separate tf_state / lut_state pointers and introduce a dedicated lut_colorop local. Resolve both pointers upfront before any computation begins. This separates the concern of "find the states" from "use the states" and makes the code easier to follow. No functional change. Assisted-by: Copilot:claude-opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: drop redundant colorop type and TF checksHarry Wentland
DRM core builds the curve_1d_type enum property with only the supported TF values, so any curve_1d_type that reaches atomic_commit is already guaranteed to be in the supported set. The per-colorop type field is immutable — it cannot change between the loop that finds colorop_state and the if block that uses it, so re-checking colorop->type there is dead code. Remove the redundant checks: - colorop->type == DRM_COLOROP_1D_CURVE in the shaper TF if block - colorop->type == DRM_COLOROP_1D_LUT in the shaper LUT if block - colorop->type == DRM_COLOROP_1D_CURVE in the blend TF if block - colorop->type == DRM_COLOROP_1D_LUT in the blend LUT if block - BIT(colorop_state->curve_1d_type) & supported_blnd_tfs in the blend TF if block (already guaranteed by the loop filter) - BIT(colorop_state->curve_1d_type) & supported_blnd_tfs in the blend LUT if block (nonsensical: a 1D_LUT colorop has no curve_1d_type) No functional change. Assisted-by: Copilot:claude-opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Remove DCCG registers not needed in DCN42Matthew Stewart
[why] Some resources that exist in the DCN block are not needed and shouldn't be used. [how] Remove defines from register lists. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdkfd: use scnprintf/vscnprintf in kfd_smi_event_addWilliam Palacek
snprintf() and vsnprintf() return the number of bytes that would have been written if the buffer were large enough, not the actual bytes written. If truncation occurs, the accumulated length can exceed the buffer size, causing kfifo_in() to read past the fifo_in[] stack buffer. Switch to scnprintf() and vscnprintf() which return the actual number of bytes written, excluding the null terminator. This prevents the potential buffer over-read when calculating the offset for subsequent writes. Signed-off-by: William Palacek <William.Palacek@amd.com> Reviewed-by: Alysa Liu <Alysa.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Rewrite dccg42_initMatthew Stewart
[why] DCN42 reuses dccg42_init, which causes problems due to undefined masks. [how] - Read res_pool to determine the quantities of the respective resources - Remove the physymclk root_clock_optimization check, as it seems like it shouldn't do anything (defaults to disabled already). Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Fix DCN42 null registers & register masksMatthew Stewart
[why] The register lists used on DCN42 variants are different. Some reused codepaths are trying to access registers not used. [how] Add DISPCLK_FREQ_CHANGECNTL, HUBPREQ_DEBUG, and HDMISTREAMCLK_CNTL to the register lists. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Reintroduce "Force validation link training on all ASICs"Ivan Lipski
[Why & How] 'skip_frl_pretraining' was introduced and enabled along w/ HDMI 2.1 initial upstream, but is causing HDMI validation link training to be s kipped on short hotplugs and compliance issues. Remove this behaviour to force link training on all hotplugs for all ASICs. Reviewed-by: Relja (Reggie) Vojvodic <relja.vojvodic@amd.com> Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Add 12bpc Color Ramp SupportMichael Strauss
[WHY] 12bpc color ramp pattern was never implemented. [HOW] Add correct DPG_RAMP_CONTROL programming to match DP color ramp spec. Reviewed-by: George Shen <george.shen@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Integrate power_helpers.c functionality into power.c.Lohita Mudimela
[Why] Reduces file fragmentation in the power module by consolidating power_helpers.c . The helper file contained minimal functionality (single utility function and shared includes) that didn't warrant a separate compilation unit, leading to increased build complexity and maintenance overhead. [How] Consolidated power_helpers.c content into the internal module implementation. Moved macro outside platform-specific conditional block for wider availability. Reviewed-by: Josip Pavic <josip.pavic@amd.com> Signed-off-by: Lohita Mudimela <lohita.mudimela@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Fix 4018 warningPiotr Maziarz
[Why] It is required by Security Guidance for All Software Components. [How] Change variable type to unsigned in dc\dml\dcn314\display_mode_vba_31.c and dc\dml\dcn31\display_mode_vba_314.c. Explicit cast to unsigned in dc\link\protocols\link_hdmi_frl.c. Move warning from UNSOLVED set to SOLVED set. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Enable PSR and Replay on DCN4 variant and fix AUX instanceGabe Teeger
[Why] Enable PSR and Panel Replay on a DCN4 variant for display power savings. On links without native I2C (no DDC pin), the AUX channel must use aux_hw_inst to avoid NULL pointer access during PSR and Replay setup. [How] Enable PSR and Replay in the DCN4 variant panel config defaults. Add no_ddc_pin check in dp_setup_panel_replay(), edp_setup_freesync_replay(), and fsft_send_msg_to_fw() to use link->aux_hw_inst when dp_connector_no_native_i2c and no_ddc_pin are set. Reviewed-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Add dcn42b_soc_and_ip_translatorMatthew Stewart
[why] DCN42B was not using its own max_ip_caps table. Need to create a separate soc_and_ip_translator in order to not reuse the DCN42 one. [how] Separate DCN42B into its own soc_and_ip_translator.c file to handle this. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu: defer KCQ remap until after MES resume in reset flowJesse Zhang
Split amdgpu_gfx_mes_reset_queue_start() into reset+unmap now and queue reinit later, and do the remap only after amdgpu_mes_resume(). Avoids re-adding legacy queues while MES gangs are still suspended. Suggested-by: Shaoyun Liu <shaoyun.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu/gfx11: handle error interrupts for userqsJesse Zhang
Call the new userq reset helper, and dispatch KQs first by ring_id before falling back to the user-queue lookup. v2: squash in fixes Co-developed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu/userq: add reset helper and identify guilty user queueJesse Zhang
If we get an interrupt for a bad user queue (bad opcode, etc.), add a helper to handle the reset for user queues. v2: squash in fixes v3: - schedule the reset via amdgpu_userq_start_hang_detect_work() instead of open-coding mod_delayed_work() - drop the per-queue guilty flag; always reset the queue the hang detect work belongs to, matching the non-compute reset path Co-developed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdkfd: flush MES queue on reset-time queue removalJesse Zhang
Pass flush_mes_queue=true in reset_queue_mes() to match the GFX post-reset drop semantics. Suggested-by: Shaoyun Liu <shaoyun.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu/mes12: drop queue state on RESET_QUEUES unmapJesse Zhang
Set remove_queue_after_reset=1 (MES >= 0x5a) so MES drops its internal state instead of re-unmapping an already MMIO-reset queue, which can timeout into a GPU reset. Suggested-by: Shaoyun Liu <shaoyun.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdkfd: Guard m->cp_hqd_eop_control setting by q->eop_ring_buffer_sizeXiaogang Chen
To avoid wraparound if the value is 0. Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu/vce: fix integer overflow in image sizeBoyuan Zhang
Fix a security vulnerability where malicious VCE command streams with oversized dimensions (e.g. 65536×65536) cause 32-bit integer overflow, wrapping the calculated buffer size to 0. This bypasses validation and allows GPU firmware to perform out-of-bound memory access. The fix uses 64-bit arithmetic to detect overflow and rejects invalid dimensions before they reach the hardware. V2: remove redundant check V3: modify max height value V4: remove size64 Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu/vcn4: avoid rereading IB param lengthBoyuan Zhang
Reuse the parameter length returned by vcn_v4_0_enc_find_ib_param() instead of rereading it from the IB. This avoids a potential TOCTOU issue if the IB contents change between reads. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: David Rosca <david.rosca@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu: fix division by zero with invalid uvd dimensionsBoyuan Zhang
When width or height is less than 16, width_in_mb or height_in_mb becomes 0, leading to fs_in_mb being 0. This causes a division by zero when calculating num_dpb_buffer in H264 and H264 Perf decode paths. Add validation to reject frames with width < 16 or height < 16 before performing any calculations that depend on these values. V2: Format change - move up all vaiable definitions. V3: Use warn_once to avoid spam. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu: Support some Barco AMD based graphics adaptersMatthew Jacob
These adapters typically are only supported by Barco on the Windows platform. However, with these changes in the linux driver, multiple monitor support should work correctly. Signed-off-by: Matthew Jacob <mjacob@feralsw.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdkfd: avoid PTL confused warning messageEric Huang
PTL is a special feature for gfxv9.4.4, but the warning is always appearing on other ASICs when rocprof is running, it causes confusion, so move hw_supported check earlier to avoid it. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdkfd: drop struct kfd_signal_page wrapperYongqiang Sun
struct kfd_signal_page now only wraps a single uint64_t *kernel_address pointer. Drop the wrapper struct (and the page_slots() helper) and store the signal page pointer directly in kfd_process::signal_page. Since the signal page is the GTT BO mapping provided by user mode and is not owned by the events code, no separate allocation/free is needed for it, so shutdown_signal_page() goes away as well. No functional change intended. Signed-off-by: Yongqiang Sun <Yongqiang.Sun@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu: bounds check ATOM IIO table parsingLijo Lazar
atom_index_iio() parsed the IIO bytecode without bounds checks, allowing out-of-bounds reads on a malformed VBIOS. Pass the BIOS size into amdgpu_atom_parse() and bound the parse loops by it. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Assisted-by: Claude Code Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu: Guard reads in pcie state readoutLijo Lazar
Internal US/DS switch may not be exposed in passthrough. Guard the upstream port reads to avoid a NULL dereference. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: set MSA MISC1 bit 6 when using VSC SDP for DCE 11.xLeorize
When BT.2020 colorimetry is selected, the driver sends information using VSC SDP but does not set "ignore MSA colorimetry" bit on older GPUs with DCE-based IPs. This causes certain sinks to prefer colorimetry information in DP MSA, resulting in terrible color rendering ("dull" colors) when HDR is enabled. This commit wires up the MISC1 bit 6 for GPUs with DCE 11.x based IPs to correctly configure sinks to ignore colorimetry information in MSA, resolving the color rendering issue. Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/4849 Assisted-by: oh-my-pi:GPT-5.5 Signed-off-by: Leorize <leorize+oss@disroot.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu/gfx8: Enable IP block soft reset as a GPU recovery methodTimur Kristóf
Enable IP block soft reset as a GPU recovery method for GFX8 graphics and compute rings. Tested with the "hard_reset_cp_wait" test case from the Hang Test Suite created by Natalie Vock and Konstantin Seurer. This Vulkan testcase waits for an event that never occurs, effectively a WAIT_REG_MEM packet that intentionally hangs. IP block soft reset can resolve that hang and allow the rest of the system to move on and keep functioning without needing a full ASIC reset. Tested on the following chips: Polaris 10 (Radeon RX 570) Polaris 11 (Radeon RX 560) Polaris 12 (Radeon RX 550) Fiji (Radeon R9 Nano) Tonga (Radeon R9 380X) Carrizo (A8-9600) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu/gfx8: Fixup IP block soft resetTimur Kristóf
Always reset everything in the GFX block at once as opposed to trying to figure out which blocks need to be reset based on their busy flags. This makes the reset more robust and predictable. Increase delays when waiting for the GRBM and SRBM soft reset to complete. Call IP block suspend/resume to ensure correct operation now that we no longer have pre/post_soft_reset(). Call clock/powergating functions, otherwise power consumption will increase after the GFX IP block is soft reset. Return correct error code to signal failure in case not all rings are functional after the IP block is soft reset. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu/gfx8: Adjust EDC GPR workaroundTimur Kristóf
When the compute queue is unavailable to run the IB, return -EBUSY instead of silently failing. Make sure the IB is always executed during reset: Set preempt condition (may be cleared during reset), and flush HDP cache so the GPU sees the updated value. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu/gfx8: Support COND_EXEC on compute ringsTimur Kristóf
It is useful to minimize collateral damage during an IP block soft reset. We can clear the COND_EXEC condition so that only the currently executing submission is at risk. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu/gfx8: Return error when testing all ringsTimur Kristóf
The gfx_v8_0_cp_test_all_rings() function should return success only when all ring tests were successful. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amdgpu/gfx8: Stop CP and RLC during resetTimur Kristóf
The only case when they may not go idle is when we are dealing with a GPU hang, in which case we should just forcibly disable these even when they aren't idle. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-08-16 02:28:10 +0000