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3 daysdax/fsdev: don't leave a dangling dev_dax->pgmap on probe failureJohn Groves
After the dynamic path set dev_dax->pgmap, any later probe failure left dev_dax->pgmap dangling: devres frees the devm_kzalloc'd pgmap on probe failure, and subsequent probe attempts would hit the "dynamic-dax with pre-populated page map" check and fail permanently. Factor pgmap acquisition out into fsdev_acquire_pgmap(), and defer the dev_dax->pgmap assignment until probe can no longer fail. A failed probe now never publishes the pointer at all, so there is nothing to unwind. This also matches kill_dev_dax(), which already clears the dynamic pgmap pointer on unbind: dev_dax->pgmap is now non-NULL only while the pgmap is actually valid. Refactor suggested by Dave Jiang. Fixes: d5406bd458b0a ("dax: add fsdev.c driver for fs-dax on character dax") Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: John Groves <john@groves.net> Link: https://patch.msgid.link/0100019ecc092ca1-ffc7a5fd-1252-4be5-882c-fd5efdc102a9-000000@email.amazonses.com Signed-off-by: Alison Schofield <alison.schofield@intel.com>
3 daysdax/fsdev: clear vmemmap_shift when binding static pgmapJohn Groves
Clear pgmap->vmemmap_shift for static DAX devices. When rebinding a static device from device_dax (which may set vmemmap_shift based on alignment) to fsdev_dax, the stale vmemmap_shift persists on the shared pgmap. Explicitly zero it before devm_memremap_pages() so the vmemmap is built for order-0 folios as fsdev requires. Fixes: d5406bd458b0a ("dax: add fsdev.c driver for fs-dax on character dax") Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: John Groves <john@groves.net> Link: https://patch.msgid.link/0100019ecc090eea-7c46f51e-5393-402c-850d-78059bb6d343-000000@email.amazonses.com Signed-off-by: Alison Schofield <alison.schofield@intel.com>
3 daysdax/fsdev: fix multi-range offset in memory_failure handlerJohn Groves
Fix memory_failure offset calculation for multi-range devices. The old code subtracted ranges[0].range.start from the faulting PFN's physical address, which produces an incorrect (inflated) logical offset when the PFN falls in ranges[1] or beyond due to physical gaps between ranges. Add fsdev_pfn_to_offset() to walk the range list and compute the correct device-linear byte offset relative to ranges[0].start (the device data start) -- the base the holder (xfs, famfs) maps from -- for both static and dynamic devices. V5 walked the pagemap's immutable pgmap->ranges[] instead, to avoid reading the mutable dev_dax->ranges[] from this callback. That had a different problem: it regressed static devices, where pgmap->ranges[0].start can sit data_offset below the data start, so the reported offset came out data_offset too high and the holder would act on the wrong blocks. For dynamic devices the two arrays are identical, so pgmap->ranges[] only ever helped the dynamic case while breaking the static one. Walk dev_dax->ranges[] instead. (Richard Cheng spotted the static regression.) Reading dev_dax->ranges[] here may race a concurrent krealloc() of the range array via sysfs (mapping_store(), under dax_region_rwsem, which this ->memory_failure callback does not hold). That exposure is pre-existing -- the original single-range code read dev_dax->ranges[0] locklessly as well -- so this patch does not make it worse; a proper fix (locking or snapshotting) belongs in a separate change. Fixes: d5406bd458b0a ("dax: add fsdev.c driver for fs-dax on character dax") Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: John Groves <john@groves.net> Reviewed-by: Richard Cheng <icheng@nvidia.com> Link: https://patch.msgid.link/0100019ecc08d74f-ec0d09b8-11e9-4e5b-af48-8c6d382af486-000000@email.amazonses.com Signed-off-by: Alison Schofield <alison.schofield@intel.com>
3 daysnvdimm/btt: reject an arena whose nfree is below the lane countBryam Vargas
The BTT info block's nfree field, the number of reserve free blocks, is read from the medium without validation. btt_freelist_init() and btt_rtt_init() size the per-lane freelist[] and rtt[] arrays by nfree, but the I/O path indexes them by the lane from nd_region_acquire_lane(), which is bounded by nd_region->num_lanes (ND_MAX_LANES), not by nfree. A crafted or foreign arena whose nfree is below the lane count makes freelist[lane]/rtt[lane] run past the allocation: an out-of-bounds write. btt.rst documents the nlanes = min(nfree, num_cpus) invariant, which the code does not currently honor: num_lanes is ND_MAX_LANES regardless of nfree. Reject an arena whose nfree is below num_lanes at discovery, before the per-lane arrays are allocated, enforcing that invariant. Fixes: 5212e11fde4d ("nd_btt: atomic sector updates") Cc: stable@vger.kernel.org Signed-off-by: Bryam Vargas <hexlabsecurity@proton.me> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Tested-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260620-b4-disp-88b2514b-v1-1-3834e707d232@proton.me Signed-off-by: Alison Schofield <alison.schofield@intel.com>
3 dayslibnvdimm/labels: Bound the on-media label size before the shiftBryam Vargas
For a v1.2+ index, __nd_label_validate() computes the label size as 1 << (7 + nsindex[i]->labelsize), where labelsize is a u8 read from the label storage medium. A value of 25 or more makes the shift count reach or exceed the width of int -- undefined behavior -- and 24 already shifts into the sign bit. Only 0 (128-byte) and 1 (256-byte) are valid. Reject a labelsize above 1 before the shift. The result was rejected by the following size comparison anyway, so this only removes the undefined shift on a crafted or corrupted medium; conforming labels are unaffected. Fixes: 564e871aa66f ("libnvdimm, label: add v1.2 nvdimm label definitions") Signed-off-by: Bryam Vargas <hexlabsecurity@proton.me> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260624-b4-disp-d8279485-v3-2-cdb6cab28b41@proton.me Signed-off-by: Alison Schofield <alison.schofield@intel.com>
3 dayslibnvdimm/labels: Prevent integer overflow in __nd_label_validate()Bryam Vargas
The on-media namespace index field nslot is a u32 read from the DIMM label storage area. __nd_label_validate() bounds it against the config area size, but sizeof_namespace_label() returns unsigned, so the product nslot * label_size is evaluated in 32-bit and wraps modulo 2^32 before the comparison. A crafted nslot passes the bound and is then used as the loop trip count in nd_label_data_init(), whose memset() walks off the end of the config_size buffer: an out-of-bounds write. The field is not trusted -- it comes from the medium, or from userspace via ND_CMD_SET_CONFIG_DATA. Evaluate the product in 64-bit so the bound check is exact; conforming labels are unaffected. The check was safe when introduced by commit 4a826c83db4e ("libnvdimm: namespace indices: read and validate"): it multiplied by sizeof(struct nd_namespace_label), a size_t, so on a 64-bit build the product did not wrap. Commit 564e871aa66f ("libnvdimm, label: add v1.2 nvdimm label definitions") narrowed it to 32 bits when the label size became a runtime value read via sizeof_namespace_label(). Fixes: 564e871aa66f ("libnvdimm, label: add v1.2 nvdimm label definitions") Cc: stable@vger.kernel.org Reviewed-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Bryam Vargas <hexlabsecurity@proton.me> Link: https://patch.msgid.link/20260624-b4-disp-d8279485-v3-1-cdb6cab28b41@proton.me Signed-off-by: Alison Schofield <alison.schofield@intel.com>
3 daysdrm/amdgpu/ras: only check bad page for address-based UMC injectionStanley.Yang
UMC error injection on MI300 series is dispatched by the RAS TA using the injection method; only the "coherent" methods are address based, the single-shot/persistent/ac-parity ones ignore the address. The debugfs control path validated the injection address against the bad page list for every UMC injection. On uniras (SMU v13+) devices the address is now validated by the ras_mgr inject handler, so the legacy debugfs bad page check only runs on the legacy RAS path; other ASICs keep injecting by address. In the ras_mgr handler an injection is treated as non address-based only when userspace passes the U64_MAX sentinel address and the method is a non-address method. In that case the address is cleared to 0 and the bad page / range validation is skipped; otherwise the injection address is validated as before. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amdgpu: drop debug_enable_ras_aca debug mask flagCe Sun
drop debug_enable_ras_aca debug mask flag Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amdgpu: use IP version check in sysfs creation conditional logicCe Sun
avoid sysfs node creation faults when performing NPS mode switching Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: move connector state dereference after NULL checkGuangshuo Li
amdgpu_dm_connector_atomic_check() checks whether the old or new connector state returned by the atomic helpers is NULL before using those pointers. However, new_con_state is already dereferenced while initializing crtc, before the NULL check is reached. If drm_atomic_get_new_connector_state() returns NULL, the function can dereference the NULL pointer before the WARN_ON() check can handle it. Declare crtc first and initialize it only after the NULL check has succeeded. Fixes: 1e5e8d672fec ("drm/amd/display: Avoid a NULL pointer dereference") Signed-off-by: Guangshuo Li <lgs201920130244@gmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patch.msgid.link/20260708072751.724400-1-lgs201920130244@gmail.com (ML: adjust for movement to amdgpu_dm_connector.c) Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amdkfd: fix 32-bit overflow in CWSR total size calculationYongqiang Sun
total_cwsr_size was computed in 32-bit before being used as a BO/SVM allocation size. With large ctx_save_restore_area_size and debug_memory_size multiplied by the XCC count, the product can wrap, yielding an undersized CWSR save area that firmware later overruns. Promote total_cwsr_size to u64 and use check_add_overflow()/ check_mul_overflow() in both kfd_queue_acquire_buffers() and kfd_queue_release_buffers(). Signed-off-by: Yongqiang Sun <Yongqiang.Sun@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Test MCCS FreeSync VCP helpersAlex Hung
[WHAT] Add KUnit coverage for dm_helpers_read_mccs_caps and dm_helpers_mccs_vcp_set, including the DP/HDMI/legacy-PCON selection, the i2c VCP request and set packets and the retry-failure paths. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Test I2C, stubs and MST early returnsAlex Hung
[WHAT] Add KUnit coverage for dm_helpers_submit_i2c, dm_helper_dmub_aux_transfer_sync, the empty stub helpers, the MST null-connector early returns, dm_helpers_dmub_outbox_interrupt_control, dm_helpers_mst_enable_stream_features and dm_helpers_enable_periodic_detection. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Test MST start/stop and panel settingsAlex Hung
[WHAT] Add KUnit coverage for dm_helpers_dp_mst_start_top_mgr and dm_helpers_dp_mst_stop_top_mgr, dm_helpers_dp_write_hblank_reduction, get_dsc_max_slices, dm_helpers_init_panel_settings, dm_helpers_override_panel_settings and fill_dc_mst_payload_table_from_drm. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Test DPCD AUX and Synaptics helpersAlex Hung
[WHAT] Add KUnit coverage for DTN logging, DPCD read/write, fused IO and the Synaptics DSC workaround helpers execute_synaptics_rc_command, apply_synaptics_fifo_reset_wa, write_dsc_enable_synaptics_non_virtual_dpcd_mst and dm_helpers_dp_write_dsc_enable. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Test EDID and ACPI/VBIOS readersAlex Hung
[WHAT] Add KUnit coverage for the EDID parsing helpers edid_extract_panel_id, apply_edid_quirks and dm_helpers_parse_edid_caps, together with the ACPI/VBIOS EDID readers dm_helpers_probe_acpi_edid, dm_helpers_read_acpi_edid and dm_helpers_read_vbios_hardcoded_edid. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Re-evaluate cursor mode on plane position/size changeJames Lin
[Why] dm_crtc_get_cursor_mode() only re-evaluates the required cursor mode (native vs overlay) when a top plane changes its scale, pixel format, enable state, or zpos/color pipeline. It does not re-evaluate when a plane changes only its destination rectangle (crtc_x, crtc_y, crtc_w, crtc_h) at a constant scale. A pure move/resize can create or remove a hole under the cursor, which changes whether the native cursor is valid. When a primary plane shrinks and no longer covers the cursor region, the cursor mode stays NATIVE and the cursor is not rendered over the uncovered area, so it becomes invisible there. This is caught by igt@amdgpu/amd_cursor_overlay@non-full, where the test CRC was a constant black value across all cursor positions instead of tracking the reference. [How] In the per-plane loop of dm_crtc_get_cursor_mode(), set consider_mode_change when any of crtc_x, crtc_y, crtc_w or crtc_h differs between the old and new plane state, so a plane move/resize forces re-evaluation of the cursor mode. The driver then correctly promotes the cursor to OVERLAY mode when the primary stops covering the cursor region. Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com> Signed-off-by: James Lin <PingLei.Lin@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: ensure dtbclk clk_src selected before hdmistream_clk_enCharlene Liu
[why] correct a sequence issue by switching to dcn35's dccg sequence: to make sure select dtbclk src first before programming hdmistream_clk_en. Reviewed-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Fix indenting of dpms onDominik Kaszewski
[Why & How] Cleanup for future refactors. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Add MALL status readback support for DCN 4.0.1James Lin
[why] The IGT test igt@amdgpu/amd_mall@static-screen always fails on DCN 4.0.1 because debugfs reports "mall enabled: no" even when MALL is actually active. This is because the DCN 4.0.1 hubbub function table is missing the .get_mall_en callback, so capabilities_show() always sees mall_in_use as false. [how] Reuse hubbub32_get_mall_en() for DCN 4.0.1 since the DCHUBBUB_ARB_MALL_CNTL register layout is identical to DCN 3.2: - Register the DCHUBBUB_ARB_MALL_CNTL register offset in dcn401_resource.h - Add MALL_PREFETCH_COMPLETE and MALL_IN_USE mask/shift definitions in dcn401_hubbub.h - Wire up .get_mall_en = hubbub32_get_mall_en in hubbub4_01_funcs Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com> Signed-off-by: James Lin <PingLei.Lin@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Add DCN42B VID_CRC_CONTROL and HBLANK_CONTROL registersMatthew Stewart
[why] These registers are needed by our existing code. [how] Add the missing register defines to dcn42b_resource.c. Remove DCN42B variant of HP_DP_STREAM_ENC_REG_LIST_RI as it is now the same as the DCN42B one, when these registers are included. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: add null pointer access checkCharlene Liu
[why] need to add null pointer access check Reviewed-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Add KUnit tests for ismAlex Hung
Add KUnit coverage for the following ISM functions: - dm_ism_next_state(): state transitions for running, busy, hysteresis-wait, optimized-idle, and aborted states - dm_ism_get_sso_delay(): null stream, zero frames, 1080p60 3-frame, and 4k60 1-frame calculations - dm_ism_get_idle_allow_delay(): null stream, zero filter/entry/delay frames, short-idle filtering, wrap-around, old history cutoff, mixed durations, and entry count exceeding history size - amdgpu_dm_ism_init(): initial state setup - amdgpu_dm_ism_fini(): cleanup after init - dm_ism_set_last_idle_ts(): timestamp update - dm_ism_insert_record(): basic insert and wrap-around - dm_ism_trigger_event(): valid and invalid transitions Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Fix dc_stream_remove_writeback dropping wrong writeback ↵Bhuvanachandra Pinninti
entries. [why] The matching entry was disabled but still copied during compaction, so a removed pipe could survive and overwrite a valid entry, leaving num_wb_info wrong. [how] Skip every entry matching dwb_pipe_inst and compact only survivors. Covered by test_dc_stream_writeback_drc_and_remove.And added new test cases for coverage. Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by: Bhuvanachandra Pinninti <BhuvanaChandra.Pinninti@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: update memclk clock table read for dcn42Dmytro Laktyushkin
Change memclk table to match dcfclk size to avoid fine grained mapping in dml2.1 Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Add Debug Option To Enable Per-DPM De-rate UsageAustin Zheng
[Why] DML has been updated to use per-DPM derates when provided but per-DPM de-rates have not been finalized. Need to validate to see what values should be stored in the bounding box. [How] Add debug options to set custom derates per DPM (starting at DPM0) and their values Each entry in the custom derate expects the derates to be stored in the following format: bits 0-7: dram_derate_percent_pixel bits 8-15: fclk_derate_percent bits 16-23: dcfclk_derate_percent bits 24-31 are unused. e.g. Using the value 0x414020 will set the following derates for DPM0 DPM0: 0x20, 0x40, 0x41 for dram, fclk, and dcfclk respectively Note that global derate value will be used if the per-DPM derate is 0. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Add KUnit tests for CACP on LinuxChenyu Chen
[Why] The CACP enablement on Linux added panel-type detection and CACP capability logic that was not covered by KUnit tests. [How] Export amdgpu_dm_set_panel_type() and amdgpu_dm_update_cacp_caps() for KUnit via STATIC_IFN_KUNIT/EXPORT_IF_KUNIT and add unit tests covering: - amdgpu_dm_update_cacp_caps(): IP version gating (including the 3.1.6 exclusion), eDP/LVDS signal handling, non-eDP signals, and OLED vs LCD panel types. - amdgpu_dm_set_panel_type(): VSDB OLED/MINILED, DPCD oled/miniled bits, the DID path (OLED and LCD), the vendor luminance heuristic, and the LCD default. Update the should_create_sysfs backlight tests to reflect the new OLED/CACP behavior (OLED with/without CACP and LCD eDP panels). Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Fix dead-code panel type detection from DIDChenyu Chen
[Why] In amdgpu_dm_set_panel_type() the DID fallback branch tested and wrote link->panel_type, while the rest of the function tracked the result in the local variable panel_type. The final assignment unconditionally overwrites link->panel_type from panel_type, so the value derived from DID was always discarded, making the DID branch dead code. [How] Use the local panel_type variable in the DID fallback branch so that the DID result participates in the source priority (VSDB -> DPCD -> DID -> vendor luminance heuristic -> LCD default) and is preserved by the final assignment. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Remove sink usage from DPMSDominik Kaszewski
[Why] stream->sink is optional and can be null, so should always be checked before dereference. Additionally, most of its usage in DPMS sequences is for stream->sink->link, which can be replaced with stream->link, as the two should always be the same. [How] * Replace stream->sink->link in DPMS on/off * Add assert to USB4 BW allocation where sink is required * Avoid inconsistencies in resource access, e.g. don't repeat stream->link after it was already saved to a local variable * Pull out effective VPG calculation to helper getter * Formatting fixes Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: program dither on all OPP heads under ODM combineJames Lin
[why] The IGT test kms_plane_alpha_blend@coverage-vs-premult-vs-constant failed on DCN with ODM 2:1 combine enabled. The test compares the CRC of a coverage-blended plane against a premultiplied-blended plane and expects them to be identical. With ODM combine the whole-frame CRC mismatched (left segment matched, right segment differed). Root cause: dc_stream_set_dither_option() iterated the pipe_ctx array and broke out at the first pipe matching the stream (the OTG master / OPP instance 0), then programmed bit-depth reduction (dither) on that single OPP only. Under ODM combine there is more than one OPP head, so the secondary ODM segment (OPP instance 1) was never reprogrammed. When CRC capture requested dither off, only the left OPP got updated while the right OPP kept its previous dither setting, producing a different CRC for the right segment and thus a whole-frame CRC mismatch. [how] Use resource_get_otg_master_for_stream() and resource_get_opp_heads_for_otg_master() to retrieve every OPP head of the stream, then loop over all of them and call transform_set_pixel_storage_depth() and opp_program_bit_depth_reduction() on each. This keeps all OPP heads in sync under ODM combine, so dither is applied (or cleared) identically across every segment and the CRCs match. Reviewed-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: James Lin <PingLei.Lin@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Check dc_link before applying DSC policySrinivasan Shanmugam
apply_dsc_policy_for_stream() decides whether Display Stream Compression (DSC) should be enabled for a display stream based on display capabilities, link bandwidth and user overrides. Smatch reports that apply_dsc_policy_for_stream() dereferences aconnector->dc_link before checking whether it is NULL. Add an early NULL check for aconnector->dc_link before the first dereference and remove the later redundant NULL check in the HDMI_FRL path. Fixes: 0e967e086e75 ("drm/amd/display: Extract connector and encoder code to amdgpu_dm_connector") Reported-by: Dan Carpenter <error27@gmail.com> Cc: Roman Li <roman.li@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: George Zhang <george.zhang@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Add passive dongle handling in force_to_use_aux caseMatthew Stewart
[why] Need special handling for passive HDMI dongles with I2C over AUX. Reviewed-by: Aurabindo Pillai <Aurabindo.Pillai@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Enable zstate support and fix seamless bootGabe Teeger
[Why & How] Port seamless boot fix from DCN42 to DCN42B and enable zstate support for DCN42B. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Fix DCN42B null registers & register masksMatthew Stewart
[why] DCN42B is missing some register masks, which are causing errors in dmesg. [how] Make DCN42B reuse the DCN42 register lists, and add the missing defines manually. Fixes: 64142f9d51af ("drm/amd/display: Fix DCN42 null registers & register masks") Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Enable IPS support for DCN4 VariantGabe Teeger
[Why] DCN4 variant had IPS completely disabled via ips_support = false and dc->config.disable_ips = DMUB_IPS_DISABLE_ALL. Enabling IPS for D3 allows DMUB to manage idle power savings when the display subsystem is inactive, reducing platform power without affecting active display operation. [How] In DCN4 variant resource construct: - Set dc->caps.ips_support = true - Remove dc->config.disable_ips = DMUB_IPS_DISABLE_ALL override This enables DMUB to dynamically manage IPS entry/exit during D3 power state transitions. Also enable zstate by default. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amdgpu/gfx12: fix IP dump alloc orderingAlex Deucher
If gfx sysfs init fails, we may leak the ip dump allocations. Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amdgpu/gfx11: fix IP dump alloc orderingAlex Deucher
If gfx sysfs init fails, we may leak the ip dump allocations. Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amdgpu/gfx10: fix IP dump alloc orderingAlex Deucher
If gfx sysfs init fails, we may leak the ip dump allocations. Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amdgpu/gfx9: fix IP dump alloc orderingAlex Deucher
If gfx sysfs init fails, we may leak the ip dump allocations. Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amdgpu/gfx12.1: Add ip dump supportAlex Deucher
Add support for dumping IP register state. v2: fixes suggested by Mukul Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amdgpu: Change system_unbound_wq with system_dfl_wqMarco Crivellari
system_wq (per-CPU) and system_unbound_wq (unbound) are the older workqueue name, replaced by system_{percpu|dfl}_wq. The new workqueues have been introduced by: 128ea9f6ccfb ("workqueue: Add system_percpu_wq and system_dfl_wq") Usage of older workqueues will now trigger a pr_warn_once() because they are marked as deprecated as per commit: 64d8eae3f895 ("workqueue: Add warnings and fallback if system_{unbound}_wq is used") So change the used workqueue with the newer, keeping the same behavior. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Suggested-by: Tejun Heo <tj@kernel.org> Signed-off-by: Marco Crivellari <marco.crivellari@suse.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Enable PSR and Replay on DCN4 variant [Part 2]Gabe Teeger
[Why] Enable PSR and Panel Replay on a DCN4 variant for display power savings. [How] Enable PSR and Replay in the DCN4 variant panel config defaults. Fixes: 68737239e891 ("drm/amd/display: Enable PSR and Replay on DCN4 variant and fix AUX instance") Reviewed-by: George Zhang <george.zhang@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Enable CACP on LinuxChenyu Chen
[Why] Enable OLED panels to save more power on the Linux platform by enabling CACP support on Linux. [How] Update abm_feature_support() to return ABM_CACP_SUPPORT for OLED panels. Enable ABM property for all eDP panels including OLED to support CACP via set_abm_level. Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Generalize DMUB memory flushes from hostDillon Varone
[WHY&HOW] Add DMUB service context to aid in platform abstraction when flushing memory from the host. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amd/display: Fix KUnit backlight tests for CACPAlex Hung
[WHY] A change was added in amdgpu_dm_should_create_sysfs() to check link->panel_type instead of caps->aux_support, and removed the OLED exclusion from the ABM property attach path in amdgpu_dm_setup_backlight_device(). This broke three KUnit tests: - dm_test_should_create_sysfs_no_backlight_index and dm_test_should_create_sysfs_pwm_backlight returned false because kzalloc zeroes panel_type but PANEL_TYPE_LCD is 1. - dm_test_setup_backlight_device_oled_success crashed with a NULL pointer dereference in drm_object_attach_property since abm_level_property was NULL. [WHY] Set panel_type to PANEL_TYPE_LCD in the two sysfs tests and skip the ABM property attach path in the OLED setup test by setting amdgpu_dm_abm_level to 0. Cc: Chenyu Chen <chen-yu.chen@amd.com> Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amdgpu/discovery: Fix device family for DCN42Roman Li
GC 11.7.0 and 11.7.1 should map to AMDGPU_FAMILY_GC_11_5_4 for DCN42. Fixes: cf591e67c095 ("drm/amdgpu: add support for GC IP version 11.7.0") Fixes: a928d8d81ec5 ("drm/amdgpu: add support for GC IP version 11.7.1") Signed-off-by: Roman Li <Roman.Li@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysdrm/amdgpu: update mmhub 4.2.0 client listAlex Deucher
Update to the proper client list for mmhub 4.2.0. v2: fix typo (Alex) Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 daysMerge branch 'i2c/i2c-fixes' into i2c/i2c-nextAndi Shyti
3 daysi2c: mediatek: fix WRRD for SoCs without auto_restart optionRoman Vivchar
MediaTek mt65xx family SoCs have no auto restart, however, they still support the WRRD mode in the hardware. Because auto_restart is set to 0, the WRRD mode will be never enabled, leading to read errors. Fix this by removing auto_restart check from the WRRD enable path. Fixes: b49218365280 ("i2c: mediatek: fix potential incorrect use of I2C_MASTER_WRRD") Signed-off-by: Roman Vivchar <rva333@protonmail.com> Cc: <stable@vger.kernel.org> # v6.18+ Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20260709-6572-6595-i2c-v2-1-b2fb8510d1d3@protonmail.com
4 daysMerge branch 'i2c/i2c-fixes' into i2c/i2c-nextAndi Shyti
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