From b43aa6a6ebe8ca8bdd75ee688e1eb2d0d16a888e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 9 Sep 2026 19:58:46 +0200 Subject: arm64: dts: renesas: r8a779f0: Add GICv3 ITS and update PCIe nodes This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this SoC can use it. Add GIC ITS node into GIC node, update interrupt-map and add msi-map into PCIe controller node. The GIC ITS does have master interface to issue transactions to RAM. The interface does support cacheable transactions, however, it does not support shareable attribute, because the AXI port signals are tied to inactive in this implementation. Therefore, add "dma-noncoherent" DT property into the GIC ITS subnode. The GIC redistributor does not have cacheable/shareable, therefore add "dma-noncoherent" DT property into the GIC node. Signed-off-by: Marek Vasut Tested-by: Koichiro Den Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260909175922.161658-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 34 +++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 1aeafa1b96e2..16a83b1749b4 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -793,6 +793,8 @@ resets = <&cpg 624>; reset-names = "pwr"; max-link-speed = <4>; + msi-parent = <&its 0>; + msi-map = <0x0 &its 0x0 0x10000>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; @@ -803,10 +805,10 @@ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; snps,enable-cdm-check; status = "disabled"; }; @@ -830,6 +832,8 @@ resets = <&cpg 625>; reset-names = "pwr"; max-link-speed = <4>; + msi-parent = <&its 0>; + msi-map = <0x0 &its 0x0 0x10000>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; @@ -840,10 +844,10 @@ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; snps,enable-cdm-check; status = "disabled"; }; @@ -1291,11 +1295,23 @@ gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; - #address-cells = <0>; + #address-cells = <2>; + #size-cells = <2>; interrupt-controller; reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; interrupts = ; + dma-noncoherent; + + ranges = <0x0 0x0 0x0 0xf1000000 0x0 0x200000>; + + its: msi-controller@40000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x40000 0x0 0x20000>; + dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; }; wwdt0: watchdog@ffc90000 { -- cgit v1.2.3