From bc0e6b77cd46abae8a071296464aa9c83d847987 Mon Sep 17 00:00:00 2001 From: Tanmay Kathpalia Date: Tue, 1 Sep 2026 11:48:11 -0700 Subject: arm64: dts: agilex5: add SD/eMMC host controller The Agilex5 HPS includes a Cadence SD6HC that can drive either an SD card or eMMC. It uses separate SDMCLK (CIU) and L4_MP (BIU) clocks, and has three resets for the host controller, Combo PHY, and SDMMC OCP bridge. Signed-off-by: Tanmay Kathpalia Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 2e9844ce1ed4..5f22e6d7ab85 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -311,6 +311,21 @@ }; }; + sdmmc: mmc@10808000 { + compatible = "altr,agilex5-sd6hc", "cdns,sd6hc"; + reg = <0x10808000 0x1000>; + clocks = <&clkmgr AGILEX5_SDMCLK>, <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "ciu", "biu"; + dma-coherent; + interrupts = ; + iommus = <&smmu 5>; + resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>, + <&rst SDMMC_OCP_RESET>; + reset-names = "sdhc-reset", "combophy", "sdmmc-ocp"; + + status = "disabled"; + }; + nand: nand-controller@10b80000 { compatible = "cdns,hp-nfc"; reg = <0x10b80000 0x10000>, -- cgit v1.2.3