From c33862c0a3a9a0c47d4bbaab870a03a0229fa526 Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Tue, 31 Mar 2026 19:24:20 +0530 Subject: dt-bindings: nvmem: qfprom: Add glymur compatible Document compatible string for the QFPROM on Glymur platform. Signed-off-by: Pankaj Patil Reviewed-by: Krzysztof Kozlowski Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 2ab047f2bb69..aad8f5ea6fff 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -19,6 +19,7 @@ properties: - enum: - qcom,apq8064-qfprom - qcom,apq8084-qfprom + - qcom,glymur-qfprom - qcom,ipq5018-qfprom - qcom,ipq5332-qfprom - qcom,ipq5424-qfprom -- cgit v1.2.3 From 512946cf0f32e3c25e973806b013ea1eb87e3a3a Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 8 Apr 2026 16:01:53 -0700 Subject: nvmem: rockchip-otp: alloc clks with main struct Use a flexible array member to simplify allocation slightly. No need for a separate calloc. Signed-off-by: Rosen Penev Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/rockchip-otp.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index 0ec78b5e19e7..2c0feb036f3f 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -78,9 +78,9 @@ struct rockchip_data { struct rockchip_otp { struct device *dev; void __iomem *base; - struct clk_bulk_data *clks; struct reset_control *rst; const struct rockchip_data *data; + struct clk_bulk_data clks[]; }; static int rockchip_otp_reset(struct rockchip_otp *otp) @@ -424,7 +424,7 @@ static int rockchip_otp_probe(struct platform_device *pdev) if (!data) return dev_err_probe(dev, -EINVAL, "failed to get match data\n"); - otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp), + otp = devm_kzalloc(&pdev->dev, struct_size(otp, clks, data->num_clks), GFP_KERNEL); if (!otp) return -ENOMEM; @@ -436,11 +436,6 @@ static int rockchip_otp_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(otp->base), "failed to ioremap resource\n"); - otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks), - GFP_KERNEL); - if (!otp->clks) - return -ENOMEM; - for (i = 0; i < data->num_clks; ++i) otp->clks[i].id = data->clks[i]; -- cgit v1.2.3 From 7106dcb57aa1bcdd0cc88876275166e7e958a4f1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 19:00:20 +0200 Subject: nvmem: core: Default to read-only if wp-gpios present In case the nvmem DT node contains "wp-gpios" DT property, the device currently defaults to read-write and the force_ro sysfs attribute reads 0. Switch to the default read-only, which is both safer, and aligned with eMMC HW BOOT partition force_ro sysfs attribute behavior, which also defaults to read-only. The adjustment of nvmem->read_only value to read-only in case wp-gpios DT property is present must be done only after the device_add() got called because device_add() does internally call nvmem_bin_attr_get_umode(), which configures the permissions of 'nvmem' bin attr based on the value of nvmem->read_only that is only parsed from DT property 'read-only', without any adjustment. This way, if DT property 'read-only' is present, the 'nvmem' attribute is always read-only. Otherwise, if the device is writeable, then 'nvmem' attribute is writeable, and nvmem->read_only defaults to read-only, but can be switched to read-write at runtime via the 'force_ro' attribute. The updated behavior can be tested as follows: Current content: " $ cat /sys/bus/nvmem/devices/logging7/force_ro 1 $ hexdump -C /sys/bus/nvmem/devices/logging7/nvmem 00000000 66 6f 6f 0a ff ff ff ff " Write into default-read-only device: " $ echo bar > /sys/bus/nvmem/devices/logging7/nvmem bash: echo: write error: Operation not permitted $ cat /sys/bus/nvmem/devices/logging7/force_ro 1 " Unlock and write into device: " $ echo 0 > /sys/bus/nvmem/devices/logging7/force_ro $ cat /sys/bus/nvmem/devices/logging7/force_ro 0 $ echo bar > /sys/bus/nvmem/devices/logging7/nvmem $ hexdump -C /sys/bus/nvmem/devices/logging7/nvmem 00000000 62 61 72 0a ff ff ff ff " Relock and write into device, fails because device is read-only again: " $ echo 1 > /sys/bus/nvmem/devices/logging7/force_ro $ echo baz > /sys/bus/nvmem/devices/logging7/nvmem bash: echo: write error: Operation not permitted $ hexdump -C /sys/bus/nvmem/devices/logging7/nvmem 00000000 62 61 72 0a ff ff ff ff " Reviewed-by: Bartosz Golaszewski Signed-off-by: Marek Vasut Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index e871181751f3..6bcb90760bee 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -1019,6 +1019,10 @@ struct nvmem_device *nvmem_register(const struct nvmem_config *config) if (rval) goto err_remove_dev; + /* If the device has WP GPIO, default to read-only */ + if (nvmem->wp_gpio) + nvmem->read_only = true; + #ifdef CONFIG_NVMEM_SYSFS rval = nvmem_populate_sysfs_cells(nvmem); if (rval) -- cgit v1.2.3 From c896d1c34f2bbb392009abd0f692dca5d0f6be62 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 27 Apr 2026 23:56:18 +0530 Subject: dt-bindings: nvmem: qfprom: qcom: Add Hawi compatible Document compatible string for the QFPROM on Hawi platform. Signed-off-by: Mukesh Ojha Acked-by: Krzysztof Kozlowski Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index aad8f5ea6fff..721c34388746 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -20,6 +20,7 @@ properties: - qcom,apq8064-qfprom - qcom,apq8084-qfprom - qcom,glymur-qfprom + - qcom,hawi-qfprom - qcom,ipq5018-qfprom - qcom,ipq5332-qfprom - qcom,ipq5424-qfprom -- cgit v1.2.3 From e8b84b3fbe1e1d6d75380dceafb486861796083a Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 17 May 2026 21:19:27 -0700 Subject: nvmem: nintendo-otp: Use of_device_get_match_data() Use of_device_get_match_data() to retrieve the devtype data instead of open-coding the OF match lookup and dereferencing match->data. This also replaces the deprecated of_device.h include with of.h. Assisted-by: Codex:GPT-5.5 Signed-off-by: Rosen Penev Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/nintendo-otp.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/nvmem/nintendo-otp.c b/drivers/nvmem/nintendo-otp.c index 355e7f1fc6d5..e45a8a3a9774 100644 --- a/drivers/nvmem/nintendo-otp.c +++ b/drivers/nvmem/nintendo-otp.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #define HW_OTPCMD 0 @@ -74,8 +74,7 @@ MODULE_DEVICE_TABLE(of, nintendo_otp_of_table); static int nintendo_otp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - const struct of_device_id *of_id = - of_match_device(nintendo_otp_of_table, dev); + const struct nintendo_otp_devtype_data *data; struct nvmem_device *nvmem; struct nintendo_otp_priv *priv; @@ -95,8 +94,8 @@ static int nintendo_otp_probe(struct platform_device *pdev) if (IS_ERR(priv->regs)) return PTR_ERR(priv->regs); - if (of_id->data) { - const struct nintendo_otp_devtype_data *data = of_id->data; + data = of_device_get_match_data(dev); + if (data) { config.name = data->name; config.size = data->num_banks * BANK_SIZE; } -- cgit v1.2.3 From 9f902e68cfe33cca93b22f0a73e1052639d3b8f7 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Wed, 1 Apr 2026 02:24:57 +0000 Subject: dt-bindings: nvmem: qfprom: Add Milos compatible Document compatible string for the QFPROM on Milos platform. Signed-off-by: Alexander Koskovich Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 721c34388746..646a0da7e839 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -29,6 +29,7 @@ properties: - qcom,ipq8074-qfprom - qcom,ipq9574-qfprom - qcom,kaanapali-qfprom + - qcom,milos-qfprom - qcom,msm8226-qfprom - qcom,msm8916-qfprom - qcom,msm8917-qfprom -- cgit v1.2.3 From 5a2bba5b742278866ac8afff7766f1a982b114ba Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 15 May 2026 13:59:07 +0200 Subject: dt-bindings: nvmem: lan9662-otpc: Add LAN969x series Unlike LAN966x series which has 8K of OTP space, LAN969x series has 16K of OTP space, so document the compatible. Acked-by: Conor Dooley Signed-off-by: Robert Marko Reviewed-by: Claudiu Beznea Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/nvmem/microchip,lan9662-otpc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/microchip,lan9662-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,lan9662-otpc.yaml index f97c6beb4766..c03e96afe564 100644 --- a/Documentation/devicetree/bindings/nvmem/microchip,lan9662-otpc.yaml +++ b/Documentation/devicetree/bindings/nvmem/microchip,lan9662-otpc.yaml @@ -25,6 +25,7 @@ properties: - const: microchip,lan9662-otpc - enum: - microchip,lan9662-otpc + - microchip,lan9691-otpc reg: maxItems: 1 -- cgit v1.2.3 From 7592c50152619a7e3f7db4778d7c49f3c6b9f2db Mon Sep 17 00:00:00 2001 From: Horatiu Vultur Date: Fri, 15 May 2026 13:59:08 +0200 Subject: nvmem: lan9662-otp: add support for LAN969x Microchip LAN969x provides OTP with the same control logic, only the size differs as LAN969x has 16KB of OTP instead of 8KB like on LAN966x. Signed-off-by: Horatiu Vultur Signed-off-by: Robert Marko Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/Kconfig | 2 +- drivers/nvmem/lan9662-otpc.c | 12 +++++++++--- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 74ddbd0f79b0..78b648e14727 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -138,7 +138,7 @@ config NVMEM_JZ4780_EFUSE config NVMEM_LAN9662_OTPC tristate "Microchip LAN9662 OTP controller support" - depends on SOC_LAN966 || COMPILE_TEST + depends on SOC_LAN966 || ARCH_LAN969X || COMPILE_TEST depends on HAS_IOMEM help This driver enables the OTP controller available on Microchip LAN9662 diff --git a/drivers/nvmem/lan9662-otpc.c b/drivers/nvmem/lan9662-otpc.c index 56fc19f092a7..62d1d6381bf8 100644 --- a/drivers/nvmem/lan9662-otpc.c +++ b/drivers/nvmem/lan9662-otpc.c @@ -27,7 +27,6 @@ #define OTP_OTP_STATUS_OTP_CPUMPEN BIT(1) #define OTP_OTP_STATUS_OTP_BUSY BIT(0) -#define OTP_MEM_SIZE 8192 #define OTP_SLEEP_US 10 #define OTP_TIMEOUT_US 500000 @@ -176,7 +175,6 @@ static struct nvmem_config otp_config = { .word_size = 1, .reg_read = lan9662_otp_read, .reg_write = lan9662_otp_write, - .size = OTP_MEM_SIZE, }; static int lan9662_otp_probe(struct platform_device *pdev) @@ -196,6 +194,7 @@ static int lan9662_otp_probe(struct platform_device *pdev) otp_config.priv = otp; otp_config.dev = dev; + otp_config.size = (uintptr_t) device_get_match_data(dev); nvmem = devm_nvmem_register(dev, &otp_config); @@ -203,7 +202,14 @@ static int lan9662_otp_probe(struct platform_device *pdev) } static const struct of_device_id lan9662_otp_match[] = { - { .compatible = "microchip,lan9662-otpc", }, + { + .compatible = "microchip,lan9662-otpc", + .data = (const void *) SZ_8K, + }, + { + .compatible = "microchip,lan9691-otpc", + .data = (const void *) SZ_16K, + }, { }, }; MODULE_DEVICE_TABLE(of, lan9662_otp_match); -- cgit v1.2.3 From ac0a5d17aa3ccac3d10a0c8d1e70ae0b9fdf204a Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 8 May 2026 00:30:32 +0530 Subject: dt-bindings: nvmem: qcom,qfprom: Add Shikra compatible Document compatible string for the QFPROM on Qualcomm Shikra SoC. Signed-off-by: Komal Bajaj Acked-by: Rob Herring (Arm) Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 646a0da7e839..8134ddb54e13 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -51,6 +51,7 @@ properties: - qcom,sdm630-qfprom - qcom,sdm670-qfprom - qcom,sdm845-qfprom + - qcom,shikra-qfprom - qcom,sm6115-qfprom - qcom,sm6350-qfprom - qcom,sm6375-qfprom -- cgit v1.2.3 From 68628e84bc61e020624d2ca05e43d918ff0c5c74 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 19 May 2026 17:28:05 +0200 Subject: dt-bindings: nvmem: airoha: add SMC eFuses schema Add Airoha SMC eFuses schema to document new Airoha SoC AN7581/AN7583 way of accessing the 2 eFuse bank via the SMC command. Each eFuse bank expose 64 eFuse cells of 32 bit used to give information on HW Revision, PHY Calibration, Device Model, Private Key and all kind of other info specific to the SoC or the running system. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) Signed-off-by: Srinivas Kandagatla --- .../bindings/nvmem/airoha,smc-efuses.yaml | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/airoha,smc-efuses.yaml diff --git a/Documentation/devicetree/bindings/nvmem/airoha,smc-efuses.yaml b/Documentation/devicetree/bindings/nvmem/airoha,smc-efuses.yaml new file mode 100644 index 000000000000..c52f8d4bec39 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/airoha,smc-efuses.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/airoha,smc-efuses.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha SMC eFuses + +description: | + Airoha new SoC AN7581 expose banks of eFuse accessible + via specific SMC commands. + + 2 different bank of eFuse or 64 cells of 32 bit are exposed + read-only used to give information on HW Revision, PHY Calibration, + Device Model, Private Key... + +maintainers: + - Christian Marangi + +properties: + compatible: + enum: + - airoha,an7581-efuses + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + '^efuse-bank@[0-1]$': + type: object + + allOf: + - $ref: nvmem.yaml# + + properties: + reg: + description: Identify the eFuse bank. + enum: [0, 1] + + required: + - reg + + unevaluatedProperties: false + +required: + - compatible + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + efuse { + compatible = "airoha,an7581-efuses"; + #address-cells = <1>; + #size-cells = <0>; + + efuse-bank@0 { + reg = <0>; + }; + }; + +... -- cgit v1.2.3 From b13e7886c2e1648b7afb792a0b3ca57fc6fa8bf1 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 19 May 2026 17:28:06 +0200 Subject: nvmem: airoha: Add support for SMC eFUSE Add support for SMC eFUSE on AN7581 SoC. The SoC have 2 set of 2048 bits of eFUSE that are used to read calibration value for PCIe, Thermal, USB and other specific info of the SoC like revision and HW device present. eFuse value are taken by sending SMC command. ATF is responsible of validaing the data and rejecting reading protected data (like Private Key). In such case the SMC command will return non-zero value on a0 register. Signed-off-by: Christian Marangi Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/Kconfig | 13 ++++ drivers/nvmem/Makefile | 2 + drivers/nvmem/airoha-smc-efuses.c | 125 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 140 insertions(+) create mode 100644 drivers/nvmem/airoha-smc-efuses.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 78b648e14727..77ff62d1cd01 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -28,6 +28,19 @@ source "drivers/nvmem/layouts/Kconfig" # Devices +config NVMEM_AIROHA_SMC_EFUSES + tristate "Airoha SMC eFuse support" + depends on ARCH_AIROHA || COMPILE_TEST + depends on HAVE_ARM_SMCCC + default ARCH_AIROHA + help + Say y here to enable support for reading eFuses on Airoha AN7581 + SoCs. These are e.g. used to store factory programmed + calibration data required for the PCIe or the USB-C PHY or Thermal. + + This driver can also be built as a module. If so, the module will + be called nvmem-airoha-smc-efuses. + config NVMEM_AN8855_EFUSE tristate "Airoha AN8855 eFuse support" depends on COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 7252b8ec88d4..f6f2bc51dee1 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -10,6 +10,8 @@ nvmem_layouts-y := layouts.o obj-y += layouts/ # Devices +obj-$(CONFIG_NVMEM_AIROHA_SMC_EFUSES) += nvmem-airoha-smc-efuses.o +nvmem-airoha-smc-efuses-y := airoha-smc-efuses.o obj-$(CONFIG_NVMEM_AN8855_EFUSE) += nvmem-an8855-efuse.o nvmem-an8855-efuse-y := an8855-efuse.o obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o diff --git a/drivers/nvmem/airoha-smc-efuses.c b/drivers/nvmem/airoha-smc-efuses.c new file mode 100644 index 000000000000..e56a99f4aa1f --- /dev/null +++ b/drivers/nvmem/airoha-smc-efuses.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Author: Christian Marangi + */ + +#include +#include +#include +#include +#include +#include +#include + +#define AIROHA_SMC_EFUSE_FID 0x82000001 +#define AIROHA_SMC_EFUSE_SUB_ID_READ 0x44414552 + +#define AIROHA_EFUSE_CELLS 64 + +struct airoha_efuse_bank_priv { + u32 bank_index; +}; + +static int airoha_efuse_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct regmap *regmap = context; + + return regmap_bulk_read(regmap, offset, + val, bytes / sizeof(u32)); +} + +static int airoha_efuse_reg_read(void *context, unsigned int offset, + unsigned int *val) +{ + struct airoha_efuse_bank_priv *priv = context; + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(AIROHA_SMC_EFUSE_FID, + AIROHA_SMC_EFUSE_SUB_ID_READ, + priv->bank_index, offset, 0, 0, 0, 0, &res); + + /* check if SMC reported an error */ + if (res.a0) + return -EIO; + + *val = res.a1; + return 0; +} + +static int airoha_efuse_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int ret; + + for_each_child_of_node_scoped(dev->of_node, child) { + struct nvmem_config nvmem_config = { + .size = AIROHA_EFUSE_CELLS * sizeof(u32), + .stride = sizeof(u32), + .word_size = sizeof(u32), + .reg_read = airoha_efuse_read, + }; + struct regmap_config regmap_config = { + .reg_read = airoha_efuse_reg_read, + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + }; + struct airoha_efuse_bank_priv *priv; + struct nvmem_device *nvmem; + struct regmap *regmap; + const char *name; + u32 bank; + + ret = of_property_read_u32(child, "reg", &bank); + if (ret) + return ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + name = devm_kasprintf(dev, GFP_KERNEL, "airoha-efuse-%u", + bank); + if (!name) + return -ENOMEM; + + priv->bank_index = bank; + + regmap_config.name = name; + regmap = devm_regmap_init(dev, NULL, priv, + ®map_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + nvmem_config.name = name; + nvmem_config.priv = regmap; + nvmem_config.dev = dev; + nvmem_config.id = bank; + nvmem_config.of_node = child; + nvmem = devm_nvmem_register(dev, &nvmem_config); + if (IS_ERR(nvmem)) + return PTR_ERR(nvmem); + } + + return 0; +} + +static const struct of_device_id airoha_efuse_of_match[] = { + { .compatible = "airoha,an7581-efuses", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_efuse_of_match); + +static struct platform_driver airoha_efuse_driver = { + .probe = airoha_efuse_probe, + .driver = { + .name = "airoha-efuse", + .of_match_table = airoha_efuse_of_match, + }, +}; +module_platform_driver(airoha_efuse_driver); + +MODULE_AUTHOR("Christian Marangi "); +MODULE_DESCRIPTION("Driver for Airoha SMC eFUSEs"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 18f2b79951a9ec6b022503b50c437fd4d44f3311 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Apr 2026 09:01:01 +0200 Subject: nvmem: qcom: Unify user-visible "Qualcomm" name Various names for Qualcomm as a company are used in user-visible config options: QCOM, Qualcomm and Qualcomm Technologies. Switch to unified "Qualcomm" so it will be easier for users to identify the options when for example running menuconfig. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 77ff62d1cd01..730d71642214 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -275,7 +275,7 @@ config NVMEM_S32G_OCOTP Programmable memory pages. config NVMEM_QCOM_QFPROM - tristate "QCOM QFPROM Support" + tristate "Qualcomm QFPROM Support" depends on ARCH_QCOM || COMPILE_TEST depends on HAS_IOMEM help @@ -286,7 +286,7 @@ config NVMEM_QCOM_QFPROM will be called nvmem_qfprom. config NVMEM_QCOM_SEC_QFPROM - tristate "QCOM SECURE QFPROM Support" + tristate "Qualcomm SECURE QFPROM Support" depends on ARCH_QCOM || COMPILE_TEST depends on HAS_IOMEM depends on OF -- cgit v1.2.3 From d5bd22d9d203260c0adc8cde137e63be7e3b0927 Mon Sep 17 00:00:00 2001 From: Julian Braha Date: Tue, 31 Mar 2026 13:04:59 +0100 Subject: nvmem: cleanup dead code in Kconfig There is already an 'if NVMEM' condition wrapping NVMEM_RCAR_EFUSE, making the 'depends on' statement a duplicate dependency (dead code). I propose leaving the outer 'if NVMEM...endif' and removing the individual 'depends on' statement. This dead code was found by kconfirm, a static analysis tool for Kconfig. Signed-off-by: Julian Braha Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 730d71642214..e10f7ff725ff 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -316,7 +316,6 @@ config NVMEM_RAVE_SP_EEPROM config NVMEM_RCAR_EFUSE tristate "Renesas R-Car Gen4 E-FUSE support" depends on (ARCH_RENESAS && ARM64) || COMPILE_TEST - depends on NVMEM help Enable support for reading the fuses in the E-FUSE or OTP non-volatile memory block on Renesas R-Car Gen4 SoCs. @@ -496,4 +495,4 @@ config NVMEM_QORIQ_EFUSE This driver can also be built as a module. If so, the module will be called nvmem_qoriq_efuse. -endif +endif # NVMEM -- cgit v1.2.3 From a3122a19f00b75a8b98b96efb4e25e3e0bfb7365 Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Tue, 19 May 2026 22:19:25 +0200 Subject: nvmem: layouts: u-boot-env: check earlier for ethaddr length Unfortunately the ethaddr value in U-Boot environment might be enclosed in single/double quotes or be something completely different. This can make it different than MAC_ADDR_STR_LEN, which results in EINVAL returned by ethaddr post process. Move the check for length earlier, to skip post processing, so nvmem could still present ethaddr value as a string if the value doesn't match MAC_ADDR_STR_LEN. Signed-off-by: Tomasz Maciej Nowak Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/layouts/u-boot-env.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/nvmem/layouts/u-boot-env.c b/drivers/nvmem/layouts/u-boot-env.c index f27f387bb52a..33ec2350386f 100644 --- a/drivers/nvmem/layouts/u-boot-env.c +++ b/drivers/nvmem/layouts/u-boot-env.c @@ -38,9 +38,6 @@ static int u_boot_env_read_post_process_ethaddr(void *context, const char *id, i { u8 mac[ETH_ALEN]; - if (bytes != MAC_ADDR_STR_LEN) - return -EINVAL; - if (!mac_pton(buf, mac)) return -EINVAL; @@ -75,7 +72,7 @@ static int u_boot_env_parse_cells(struct device *dev, struct nvmem_device *nvmem info.offset = data_offset + value - data; info.bytes = strlen(value); info.np = of_get_child_by_name(dev->of_node, info.name); - if (!strcmp(var, "ethaddr")) { + if (!strcmp(var, "ethaddr") && info.bytes == MAC_ADDR_STR_LEN) { info.raw_len = strlen(value); info.bytes = ETH_ALEN; info.read_post_process = u_boot_env_read_post_process_ethaddr; -- cgit v1.2.3