From ee60be8929c7badf1194e3149a8aef930cfd77b8 Mon Sep 17 00:00:00 2001 From: "Miquel Raynal (DAVE)" Date: Fri, 29 May 2026 18:29:56 +0200 Subject: mtd: rawnand: pl353: Update timings at the right moment If several CE are wired, we would write the registers for every chip one after the other, and reselect the correct timings for the first chip the use wants to use after probe. This is not exactly efficient and could slightly be improved since we already have a helper that applies the configuration if there is a chip change. Instead of programming the registers in ->setup_interface(), let's just drop the pointer to the chip and let the nand_select_target() helper do its magic. Cc: Olivier Sobrie Signed-off-by: Miquel Raynal (DAVE) Acked-by: Olivier Sobrie Tested-by: Olivier Sobrie Acked-by: Michal Simek Signed-off-by: Miquel Raynal --- drivers/mtd/nand/raw/pl35x-nand-controller.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/pl35x-nand-controller.c b/drivers/mtd/nand/raw/pl35x-nand-controller.c index 06f8f1e14b9c..7dd71bd69deb 100644 --- a/drivers/mtd/nand/raw/pl35x-nand-controller.c +++ b/drivers/mtd/nand/raw/pl35x-nand-controller.c @@ -862,8 +862,11 @@ static int pl35x_nfc_setup_interface(struct nand_chip *chip, int cs, PL35X_SMC_NAND_TAR_CYCLES(tmgs.t_ar) | PL35X_SMC_NAND_TRR_CYCLES(tmgs.t_rr); - writel(plnand->timings, nfc->conf_regs + PL35X_SMC_CYCLES); - pl35x_smc_update_regs(nfc); + /* + * Reset nfc->selected_chip so the next command will cause the timing + * registers to be updated in ->*_select_target(). + */ + nfc->selected_chip = NULL; return 0; } -- cgit v1.2.3