kernel/git/stable/linux-stable.git/arch/arm, branch linux-2.6.37.y

ARM: Keep exit text/data around for SMP_ON_UP

2011-02-24T22:54:37+00:00

commit a9ad21fed09cb95d34af9474be0831525b30c4c6 upstream. When SMP_ON_UP is used and the spinlocks are inlined, we end up with inline spinlocks in the exit code, with references from the SMP alternatives section to the exit sections. This causes link time errors. Avoid this by placing the exit sections in the init-discarded region. Tested-by: Dave Martin Signed-off-by: Russell King Signed-off-by: Greg Kroah-Hartman

ARM: Ensure predictable endian state on signal handler entry

2011-02-24T22:54:37+00:00

commit 53399053eb505cf541b2405bd9d9bca5ecfb96fb upstream. Ensure a predictable endian state when entering signal handlers. This avoids programs which use SETEND to momentarily switch their endian state from having their signal handlers entered with an unpredictable endian state. Acked-by: Dave Martin Signed-off-by: Russell King Signed-off-by: Greg Kroah-Hartman

ARM: 6606/1: sa1100: Fix platform device registration

2011-02-24T22:54:25+00:00

commit 4f444e2b59dd4255d121b57ec41a4a8c5d6bce46 upstream. Since commit 7a5b4e16c880f8350d255dc188f81622905618c1, simpad devices don't boot anymore, since platform devices are registered too early. Fix by moving the registration from map_io to arch_initcall as done on other sa1100 boards. Signed-off-by: Jochen Friedrich Acked-by: Kristoffer Ericson Signed-off-by: Russell King Signed-off-by: Greg Kroah-Hartman

ARM: oprofile: Fix backtraces in timer mode

2011-02-17T23:15:10+00:00

commit d14dd7e20d5e526557f5d3cfef4046a642f80924 upstream. Always allow backtraces when using oprofile on ARM, even if a PMU isn't present. Restores functionality originally introduced in commit 1b7b56982fdcd9d85effd76f3928cf5d6eb26155 ("oprofile: Always allow backtraces on ARM") by Richard Purdie. It is not that obvious, but there is now only one oprofile_arch_init() function. So the .backtrace callback is available also in timer mode. Implemented by removing code and using stubs for oprofile_perf_{init, exit} provided by . This allows cleaning of other architecture specific implementations too. Signed-off-by: Ari Kauppi Acked-by: Will Deacon Signed-off-by: Robert Richter Signed-off-by: Greg Kroah-Hartman

ARM: smp_on_up: allow non-ARM SMP processors

2011-02-17T23:14:44+00:00

commit e98ff0f55a0232b578c9aa7f1c245868277ac7bc upstream. Allow non-ARM SMP processors to use the SMP_ON_UP feature. CPUs supporting SMP must have the new CPU ID format, so check for this first. Then check for ARM11MPCore, which fails the MPIDR check. Lastly check the MPIDR reports multiprocessing extensions and that the CPU is part of a multiprocessing system. Reported-and-Tested-by: Stephen Boyd Acked-by: Will Deacon Signed-off-by: Russell King Signed-off-by: Greg Kroah-Hartman

ARM: SMP: use more sane register allocation for __fixup_smp_on_up

2011-02-17T23:14:43+00:00

commit 0eb0511d176534674600a1986c3c766756288908 upstream. Use r0,r3-r6 rather than r0,r3,r4,r6,r7, which makes it easier to understand which registers can be modified. Also document which registers hold values which must be preserved. Signed-off-by: Russell King Signed-off-by: Greg Kroah-Hartman

ARM: initrd: disable initrd if passed address overlaps reserved region

2011-02-17T23:14:35+00:00

commit b0a2679d27408d97ce31e5f800b44227d3388b84 upstream. Disable the initrd if the passed address already overlaps the reserved region. This avoids oopses on Netwinders when NeTTrom tells the kernel that an initrd is located at mem+4MB, but this overlaps the BSS, resulting in the kernels in-use BSS being freed. This should be applied to v2.6.37-stable. Signed-off-by: Russell King Signed-off-by: Greg Kroah-Hartman

ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

2011-02-17T23:14:35+00:00

commit a50eb1c7680973f5441ca20ac4da0af2055d0d87 upstream. This patch is applied according to the commit 1a8e41cd672f894bbd74874eac601e6cedf838fb (ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register). Actually, S5PV310 has same cache controller(PL310). Following is from Catalin Marinas' commit. Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Changhwan Youn Cc: Catalin Marinas Cc: Russell King Signed-off-by: Kukjin Kim Signed-off-by: Greg Kroah-Hartman

Merge branch 'fix' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6

2011-01-03T22:55:21+00:00

ARM: pxa: fix page table corruption on resume

2011-01-03T15:18:59+00:00

Before this patch, the following error would sometimes occur after a resume on pxa3xx: /path/to/mm/memory.c:144: bad pmd 8040542e. The problem was that a temporary page table mapping was being improperly restored. The PXA3xx resume code creates a temporary mapping of resume_turn_on_mmu to avoid a prefetch abort. The pxa3xx_resume_after_mmu code requires that the r1 register holding the address of this mapping not be modified, however, resume_turn_on_mmu does modify it. It is mostly correct in that r1 receives the base table address, but it may also get other bits in 13:0. This results in pxa3xx_resume_after_mmu restoring the original mapping to the wrong place, corrupting memory and leaving the temporary mapping in place. Signed-off-by: Matt Reimer Signed-off-by: Eric Miao