kernel/git/stable/linux-stable.git/drivers/phy, branch master

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2026-08-26T18:14:30+00:00

Pull clk updates from Stephen Boyd: "Mostly the usual clk driver updates and new SoC additions plus non-critical data fixes for things that weren't used yet. One thing that's new here in the core is SSC spread spectrum support (SSC) in the clk provider API. The idea is that DT authors will configure SSC for certain clks and they'll be configured at clk provider registration time or when a consumer device is probed, similar to how we handle assigned clk rates or parents. On the clk driver side we have Qualcomm adding almost half the diff because they add support for 4 different SoCs and then a long tail of other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more SoC support this time around. Luckily it's mostly clk data for these new SoCs because the actual clk_ops are already there. Beyond the new drivers we get all the little fixups for more compilation coverage or usage of more modern APIs. That all looks normal. Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to help out with maintaining the clk subsystem. The current working model is already semi-distributed in that silicon vendors typically take care of their drivers and send me pull requests but I'm becoming a bottleneck for new drivers and core framework review because this has become a 100% volunteer effort on my part. Mike is stepping down after all these years (thanks Mike!) and that jump started the conversation around finding co-maintainers. Brian and Jerome have graciously offered to help me with the work load, meaning in the future they'll be sending pull requests and committing directly to the clk.git tree. They've both been around on the list for a while, I've met them both in person, and they've been making changes to the core clk framework along with helping review patches so I'm pretty confident this will work well. Core: - devm_clk_bulk_get_enable() consumer API - devm_clk_hw_register_composite_pdata() provider API - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs - Divider clk rounding improved (and tested) New Drivers: - Cix Sky1 audio subsystem (AUDSS) - UltraRISC DP1000 - MediaTek MT8173 MFG_TOP - Si549 - Aspeed AST2700 PECI - Airoha EN7523 PCIe - Rockchip RV1106 - Mobileye EyeQ7H - Qualcomm Maili GCC, TCSR, RPMh, and video clks - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks - Qualcomm Nord display and graphics clks - Qualcomm Glymur camera and EVA clks - Qualcomm Hawi video clks - Amlogic A9 AO and peripheral clks - Renesas R-Car X5H (R8A78000) CPG" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: samsung: Don't include clk: at91: Read "reg" with helper clk: renesas: Add R-Car X5H CPG driver clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator ...

Merge tag 'char-misc-7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

2026-08-25T16:38:50+00:00

Pull char/misc/IIO/etc driver updates from Greg KH: "Here is the big set of char, misc, iio, counter, fpga, and other small driver subsystems for 7.3-rc1. Overall, due to some driver removals we only added a bit more code than removed, which was a nice change. Highlights in this merge request are: - Loads of IIO driver updates and additions - binder driver updates (more on that below...) - Removal of the SGI XP and GRU drivers as they are not used anymore and turn out to be pretty insecure overall - Removal of the obsolete ibmasm driver as it's not being used anymore - Coresight driver updates and additions - Mei driver udpates - Counter driver updates - FPGA driver updates - ICC driver updates - lots and lots of other tiny driver updates to resolve reported issues All of these have been in linux-next for a while" * tag 'char-misc-7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (513 commits) iio: chemical: atlas-sensor: use iio_trigger_poll_nested() to fix remove UAF iio: adc: pac1921: fix wrong channel used in trigger handler read iio: light: gp2ap002: re-enable irq if runtime suspend fails iio: light: gp2ap002: Fix unbalanced runtime PM on repeated event writes iio: light: apds9306: fix PM reference leak in apds9306_read_data() iio: gyro: mpu3050: fix sign of raw angular velocity readings iio: srf04: fix pm_runtime handling on probe error path iio: adc: ad4080: configure backend data size iio: adc: adi-axi-adc: add data size support for AD408X backend iio: chemical: atlas-sensor: fix PM reference leak in buffer postenable iio: dac: ad5446: fix OF module device table iio: light: opt4001: Fix reversed GENMASK() arguments in fault count mask iio: light: opt4001: Reject integration times with a non-zero seconds part iio: light: opt4001: Fix incompatible pointer type passed to div_u64_rem() iio: light: opt4001: Fix power down clearing bits of the wrong register iio: light: opt4060: Fix incorrect register name in threshold read error message iio: light: opt4060: Fix pointer type passed to div_u64_rem() iio: light: opt4060: Reject integration times with a non-zero seconds part iio: light: ltrf216a: fix runtime PM reference leak in error path iio: pressure: dps310: fix NULL pointer dereference on ACPI probe ...

Merge tag 'phy-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2026-08-24T19:19:23+00:00

Pull phy updates from Vinod Koul: "As usual bunch of new device and driver support and updates to existing drivers and addition of Manivannan to help with reviews. New Support: - Mediatek MT8196 DSI PHY support - Renesas RZ/G3L usb2 support - Qualcomm SM8475 QMP USB PHY and PCIe phy, IPQ9650 QMP PCIe PHY, QUSB2 Phy for Shikra SoC, Hawi support for QMP PCIe phy and UFS PHY. Glymur QMP PCIe Multi-PHY driver and multiple link-mode support, ipq5210 PCIe phy support - Spacemit USB3/PCIe comb PHY driver Updates: - Samsung hdptx driver improvements for modernizing the register access and code cleanup - Qualcomm drop duplicate v8 DP headers, improved runtime handling for qmp drivers - Rockchip clock lane phase tuning and 2500 Mbps support and TMDS rate handling - Freescale imx8mq improvements for runtime pm, pd handling" * tag 'phy-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (76 commits) MAINTAINERS: Add Manivannan Sadhasivam as the Reviewer for Generic PHY Framework phy: rockchip-samsung-dcphy: fix out-of-range max_register phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY phy: rockchip: samsung-hdptx: Consistently use bitfield macros phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16() phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling phy: rockchip: samsung-hdptx: Consolidate consumer_put on error path phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL phy: rockchip: samsung-hdptx: Guard against clk rate integer underflow phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc phy: qcom: qmp-combo: Drop qmp_v4_calibrate_dp_phy phy: qcom: qmp-combo: Correct pre-emphasis table for QMP v4 DP PHYs phy: renesas: rcar-gen3-usb2: Ignore missing VBUS regulator phy: qcom: qmp-pcie: Add support for SM8475 Gen3x1 PCIe0 port phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHY ...

Merge tag 'gpio-updates-for-v7.3-rc1-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux

2026-08-19T16:10:07+00:00

Pull gpio updates from Bartosz Golaszewski: "GPIO core: - extend the gpio-regmap abstraction layer with more features allowing users to override configuration setting, translate register values and masks and enable/disable interrupts - extend GPIO kunit tests with suites verifying probe ordering by software node devlink support and software node hogs - shrink GPIO kunit initialization code - coding style updates (remove commas from sentinels where applicable) - with all users now converted treewide to using real firmware node links for software node GPIO lookup: remove the deprecated label-matching mechanism from from GPIO core - drop redundant return value check of nonseekable_open() in gpiolib-cdev - use IRQ trigger helpers where applicable Driver updates: - refactor error paths and logging in gpio-nomadik - use more modern interfaces for getting resources in gpio-rockchip, gpio-bt8xx and gpio-pca9570 - add missing MODULE_DEVICE_TABLE() to gpio-sifive and gpio-vf610 - drop unused FILONOFF macro from gpio-rcar - extend build coverage of ioport GPIO drivers with COMPILE_TEST=y - only enable the gpio-rtd driver by default with ARCH_REALTEK=y to avoid bloating the build - refactor coding style in several drivers - use correct endianess translation in gpio-pcf85x - add wake-up interrupt support to gpio-mvebu - apply initial value in direction output setter in gpio-by-pinctrl Misc: - replace linux/gpio.h inclusions treewide with linux/gpio/legacy.h which now exports all the deprecated APIs - select GPIOLIB_LEGACY in Kconfig where required treewide - use software nodes for gpio-keys in MFD drivers Devicetree bindings: - describe the realtek rtd1625 GPIO controller - document new models for gpio-pca95xx and gpio-cadence - document new property in gpio-rockchip" * tag 'gpio-updates-for-v7.3-rc1-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (61 commits) gpio: gpio-by-pinctrl: Apply initial value in direction output wrapper dt-bindings: gpio: rockchip,gpio-bank: Add rockchip,grf property gpio: Use IRQ trigger mask helpers gpio: allow COMPILE_TEST for IOPORT drivers gpio: realtek: Add driver for Realtek DHC RTD1625 SoC gpio: regmap: Add IRQ enable/disable helpers gpio: regmap: Add set_config callback gpio: regmap: Add value_xlate callback gpio: regmap: Add gpio_regmap_operation to extend reg_mask_xlate callback gpio: regmap: Order kernel-doc descriptions with the actual appearance gpio: regmap: Apply default resource callbacks for regmap IRQ chip gpio: regmap: Provide default IRQ resource request and release callbacks Revert "gpio: realtek: Add driver for Realtek DHC RTD1625 SoC" gpib: gpio: replace linux/gpio.h inclusion Input: matrix_keyboard - replace linux/gpio.h inclusion phy: replace linux/gpio.h inclusions pcmcia: replace linux/gpio.h inclusions ASoC: replace linux/gpio.h inclusions mfd: replace linux/gpio.h inclusions sh: replace linux/gpio.h inclusions ...

Merge tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2026-08-19T02:40:29+00:00

Pull SoC driver updates from Arnd Bergmann: "The SoC driver changes once more consist of many small fixes and cleanups, that are to a large part the result of automated testing. On platform specific drivers, this includes SoC specific code for xilinx, freescale/nxp, qualcomm, TI, aspeed, omap, tegra, samsung, rockchip, renesas, ixp4xx. In firmware drivers, we see a similar picture for SCMI and qcomtee. Aside from these, we see actual new hardware support in a few areas: - The Apple platform gets a new driver for low power states - Updates to Qualcomm platform drivers add several new hardware specific features and additional SoCs. - Amlogic SoC support for A1 and T7 is added - The Mediatek MMSYS driver is refactored as a cleanup" * tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (157 commits) soc: qcom: make QCOM_PDR_MSG selectable soc: qcom: ubwc: Fix missing include soc: qcom: ubwc: Fix link error when QCOM_SMEM=n media: iris: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM drm/msm: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDM 850 firmware: xilinx: Clear firmware notifiers across kexec transitions firmware: xilinx: Release all peripheral devices from firmware firmware: xilinx: Add support to clear EL3 PM state firmware: xilinx: Propagate actual error from feature check firmware: xilinx: Use TF-A feature check for TF-A-specific APIs bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data soc: fsl: qe: check platform_driver_register() in qe_ic_of_init() phy: lynx-10g: use RCW override procedure for dynamic protocol change soc: fsl: guts: implement the RCW override procedure dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region soc: fsl: guts: make fsl_soc_data available after fsl_guts_init() soc: fsl: guts: make it easier to determine on which SoC we are running soc: fsl: guts: add a central fsl_guts_read() function soc: fsl: guts: add a global structure to hold state ...

Merge tag 'v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next

2026-08-18T12:21:04+00:00

Linux 7.2

Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile

2026-08-17T16:27:10+00:00

Pull clk patches picked up by Brian Masney: Here's various improvements and fixes for the clk subsystem that was posted prior to the opening of the last merge window. - Add spread spectrum clock (SSC) support to the clk framework, including a new assigned-clock-sscs devicetree property and clk_hw_set_spread_spectrum() API with KUnit tests (Peng Fan) - Add SCMI clock OEM extensions for the i.MX95 clock driver and introduce a common SCMI clock header (Peng Fan) - Add clock, reset, and devicetree bindings for the ESWIN EIC7700 HSP clock and reset generator (Xuyang Dong) - Add clk_determine_rate_noop() helper for clock drivers that can do any rate, and convert existing open-coded implementations across hisilicon, imx, qcom, renesas, rp1, samsung, scpi, sprd, mediatek phy, and mediatek pmdomain drivers (Brian Masney) - Add kernel-doc documentation for struct clk_core and the core clock flags, and wire up clk identifiers into the documentation build (Brian Masney) - Fix clk_divider_bestdiv() returning the minimum rate instead of the maximum rate for large rate requests, with KUnit tests (Lad Prabhakar) - Fix Nuvoton MA35D1 PLL frequency calculation including ignored div_u64 return values, incorrect PLL_CTL1_FRAC bit field width, and broken determine_rate logic (Joey Lu) - Support unique clock names for multi-socket Tegra platforms (Jon Hunter) - Allow COMPILE_TEST builds for HiSilicon clock drivers (Rosen Penev) - Various fixes and cleanups from Akari Tsuyukusa, Alexander A. Klimov, Brian Masney, David Carlier, David Laight, Min zhang, Myeonghun Pak, Pavel Löbl, Randy Dunlap, Rob Herring, Rosen Penev, Uwe Kleine-König, William Theesfeld, Xuyang Dong, and Yu-Chun Lin Signed-off-by: Brian Masney [sboyd@kernel.org: Fix allmodconfig modpost failure in scmi] * tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux: (53 commits) pmdomain: mediatek: mtk-mfg: use clk_determine_rate_noop() pmdomain: mediatek: airoha: use clk_determine_rate_noop() phy: mediatek: phy-mtk-hdmi-mt2701: use clk_determine_rate_noop() clk: sprd: use clk_determine_rate_noop() clk: scpi: use clk_determine_rate_noop() clk: samsung: acpm: use clk_determine_rate_noop() clk: rp1: use clk_determine_rate_noop() clk: renesas: rzg2l-cpg: use clk_determine_rate_noop() clk: qcom: smd-rpm: use clk_determine_rate_noop() clk: qcom: rpmh: use clk_determine_rate_noop() clk: qcom: rpm: use clk_determine_rate_noop() clk: imx: scu: use clk_determine_rate_noop() clk: hisilicon: hi3660-stub: use clk_determine_rate_noop() clk: add clk_determine_rate_noop() clk: imx: scu: drop redundant init.ops variable assignment clk: test: convert constants to use HZ_PER_MHZ docs: clk: include some identifiers to keep documentation up to date clk: add kernel docs for struct clk_core clk: add kernel docs for the core flags clk: hisilicon: allow COMPILE_TEST builds ...

phy: rockchip-samsung-dcphy: fix out-of-range max_register

2026-08-11T16:54:03+00:00

The PHY register block is 64KB, so with a register stride of 4 the last accessible register sits at offset 0xfffc. max_register names 0x10000, one register past the end of the mapping: dumping the registers through the regmap debugfs interface reads beyond the ioremapped region and oopses on the unmapped page. The oops fires with the regmap lock held, so later PHY operations deadlock. Fixes: b2a1a2ae7818 ("phy: rockchip: Add Samsung MIPI D-/C-PHY driver") Cc: stable@vger.kernel.org Signed-off-by: Jason Yang Assisted-by: Claude:claude-opus-5 Reviewed-by: Sebastian Reichel Link: https://patch.msgid.link/20260811-dcphy-maxreg-v1-v1-1-aa63f6a63a64@gmail.com Signed-off-by: Vinod Koul

phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver

2026-08-11T16:54:03+00:00

Some QMP PCIe PHY hardware blocks support multiple link topologies (e.g. x8 or x4+x4) selected via a TCSR register. The existing single-instance QMP PCIe PHY driver has no way to model this: it assumes a single cfg per DT node and instantiates exactly one PHY. Add a dedicated driver for this class of PHY. Match data carries a per-mode cfg table; qmp_pcie_multiphy_probe() reads the current link mode from the TCSR register pointed to by "qcom,link-mode", looks up the corresponding cfg array, and instantiates one qmp_pcie per sub-PHY required by that link mode, registering the clock and #phy-cells = <1> phy providers so consumers can address individual sub-PHYs by index. The driver inherits the phy setting and link-mode programmed by firmware, so only the no_csr reset is used and no phy setting tables are provided. Add the first match data and compatible, qcom,glymur-qmp-gen5x8-pcie-phy, for the Glymur Gen5 PCIe PHY that can bifurcate into two x4 links or operate as a single x8 link. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu Link: https://patch.msgid.link/20260807-glymur_linkmode_0807-v9-2-dd1c7e236e29@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: rockchip: samsung-hdptx: Consistently use bitfield macros

2026-08-11T16:54:03+00:00

Make the code more robust and improve readability by using the available bitfield macros (e.g. FIELD_PREP, FIELD_GET) whenever possible, instead of open coding the related bit operations. Tested-by: Thomas Niederprüm Tested-by: Simon Wright Tested-by: Diederik de Haas # NanoPC-T6 LTS Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260811-hdptx-clk-fixes-v6-10-75bca0ee5753@collabora.com Signed-off-by: Vinod Koul