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2026-07-02Merge branch 'topic/config_prep_api' into nextVinod Koul
2026-07-02dt-bindings: dma: mediatek,uart-dma: add support for MT8189 SoCLouis-Alexis Eyraud
Add the compatible string for the APDMA IP found in MT8189 SoC, that supports 35-bits addressing as MT6985 SoC. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260701-mt8189-dt-bindings-uart-dma-v1-1-c7106216a40d@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-02docs: watchdog: Fix bracketsManuel Ebner
Add missing brackets ')'. Signed-off-by: Manuel Ebner <manuelebner@mailbox.org> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20260627091707.29688-2-manuelebner@mailbox.org Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2026-07-02Documentation: bootconfig: document build-time cmdline renderingBreno Leitao
Add a section describing CONFIG_CMDLINE_FROM_BOOTCONFIG: what it does (renders the embedded "kernel" subtree to a flat cmdline at build time so early_param() handlers see the values), what it requires (BOOT_CONFIG_EMBED, a non-empty BOOT_CONFIG_EMBED_FILE, CONFIG_CMDLINE to be empty, and ARCH_SUPPORTS_CMDLINE_FROM_BOOTCONFIG -- currently x86 only), the bootconfig opt-in semantics, the initrd-vs-embedded precedence, and the soft-error overflow behavior. This addresses feedback from the Sashiko AI review and Masami Hiramatsu to document the CONFIG_CMDLINE requirement, which is enforced at the Kconfig level but was not mentioned in the documentation, potentially confusing users who might satisfy all other requirements but still find the option hidden in menuconfig if CONFIG_CMDLINE is non-empty. Link: https://lore.kernel.org/all/20260626-bootconfig_using_tools-v7-6-24ab72139c29@debian.org/ Signed-off-by: Breno Leitao <leitao@debian.org> Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
2026-07-01Documentation/bpf: make it clear that kfuncs should be non-staticJP Kobryn
The kfunc documentation mentions how the macro __bpf_kfunc prevents inlining for static functions. This makes it sound like static kfuncs are acceptable. Although static kfuncs may happen to work, it is by chance that the compiler chose not to rename these functions and BTF resolution still succeeds. Make it clear in the documentation why kfuncs should not be declared static. First, remove wording that makes it sound like static is ok. Then point out the external naming needed for BTF resolution. Finally point out that sparse may warn on unreferenced kfuncs and that this warning can be ignored. Signed-off-by: JP Kobryn <jp.kobryn@linux.dev> Acked-by: Roman Gushchin <roman.gushchin@linux.dev> Acked-by: Yonghong Song <yonghong.song@linux.dev> Link: https://lore.kernel.org/r/20260626172026.7327-1-jp.kobryn@linux.dev Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2026-07-01dt-bindings: remoteproc: qcom: Document pas for SoCCP on Hawi and Maili SoCMukesh Ojha
Document SoCCP remote processor used on Qualcomm Hawi and Maili SoC which is fully compatible with Kaanapali. Co-developed-by: Yijie Yang <yijie.yang@oss.qualcomm.com> Signed-off-by: Yijie Yang <yijie.yang@oss.qualcomm.com> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260623-knp-soccp-v7-4-1ec7bb5c9fec@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-01dt-bindings: remoteproc: qcom: Document pas for SoCCP on Kaanapali and ↵Jingyi Wang
Glymur platforms Document the component used to boot SoCCP on Kaanapali SoC and add compatible for Glymur SoCCP which could fallback to Kaanapali. Extend the "qcom,smem-states", "qcom,smem-state-names" in the pas-common and add maxItems constraints for SMEM properties in the documents that reference to pas-common. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260623-knp-soccp-v7-3-1ec7bb5c9fec@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-01dt-bindings: remoteproc: qcom: move interrupts and interrupt-names list out ↵Jingyi Wang
of pas-common Move interrupts and interrupt-names list out of pas-common since they will be redefined differently for Kaanapali SoCCP. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260623-knp-soccp-v7-2-1ec7bb5c9fec@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-01dt-bindings: remoteproc: qcom: cleanup qcom,adsp.yamlJingyi Wang
Items in qcom,adsp.yaml has common clock and interrupt properties, move these out of the allOf section to avoid list the compatible repeatly. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260623-knp-soccp-v7-1-1ec7bb5c9fec@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-01dt-bindings: sram: qcom,imem: Narrow allowed reboot modesKrzysztof Kozlowski
Only few Qualcomm IMEM devices actually provide interface for setting reboot modes, but top-level schema allows "reboot-mode" child for everyone. Narrow this to specific compatibles. syscon-reboot-mode schema allows arbitrary "mode-.* properties but only a subset actually makes sense and is valid. Provide negative look-ahead pattern to disallow any modes not supported by the device, which tightens the binding even more. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260701105832.197036-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-07-01Documentation: sound: tas675x: Fix temperature range and impedance documentationSen Wang
Two corrections against the TRM (SLOU589A): - Corrected channel temperature range - Corrected conversion formula for global temperature Fixes: ba46edca354e ("Documentation: sound: Add TAS675x codec mixer controls documentation") Signed-off-by: Sen Wang <sen@ti.com> Link: https://patch.msgid.link/20260630183126.2588322-4-sen@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-07-01dt-bindings: iio: ti,tmp117: add binding for the TMP119Romain Gantois
The TMP119 has the same register layout as the TMP117, and a better local sensor accuracy. Add a compatible for it. Use ti,tmp117 as a fallback compatible for ti,tmp119. Signed-off-by: Romain Gantois <romain.gantois@bootlin.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2026-07-01dt-bindings: pinctrl: s32g2-siul2: describe GPIO and EIRQ resourcesKhristine Andreea Barbulescu
Extend the S32G2 SIUL2 pinctrl binding to describe the GPIO data and external interrupt resources present in the same SIUL2 hardware block. Besides the MSCR and IMCR registers used for pin multiplexing and pad configuration, SIUL2 also contains PGPDO and PGPDI registers for GPIO data and EIRQ registers for external interrupt control. Add GPIO controller properties because the SIUL2 block also provides GPIO functionality, and gpio-ranges are needed to describe the mapping between GPIO lines and pin controller pins. Document the interrupt controller properties. The SIUL2 block contains EIRQ hardware as part of the same register space. IRQ support itself will be added in a follow-up patch series. Update the example accordingly to show the complete SIUL2 register layout, including the GPIO data and EIRQ register windows. Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-07-01dt-bindings: dma: xilinx: Fix "xlnx,irq-delay" typeRob Herring (Arm)
"xlnx,irq-delay" programs an 8-bit delay field in the DMA control register, and the driver stores and reads it as a byte. The binding described the property as a uint32 cell, which made the helper type check report the driver as wrong. Document "xlnx,irq-delay" as uint8 so the generated schema reflects the hardware field width and the existing driver access. Assisted-by: Codex:gpt-5-5 Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://patch.msgid.link/20260612215226.1887726-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-01dt-bindings: dma: xlnx,axi-dma: Restore xlnx,flush-fsync as u32Suraj Gupta
The DT schema conversion incorrectly changed xlnx,flush-fsync from a u32 property to a boolean. The original binding documented values 1, 2, and 3 to select which VDMA channel(s) flush on frame sync. Restore the uint32 type with the documented enum values and fix the example accordingly. Fixes: 2d5c2952b972 ("dt-bindings: dma: xlnx,axi-dma: Convert to DT schema") Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260625161016.1249570-1-suraj.gupta2@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-07-01dt-bindings: i2c: Describe SA8255pPraveen Talari
Add DT bindings for the QUP GENI I2C controller on sa8255p platforms. SA8255p platform abstracts resources such as clocks, interconnect and GPIO pins configuration in Firmware. SCMI power and perf protocol are utilized to request resource configurations. SA8255p platform does not require the Serial Engine (SE) common properties as the SE firmware is loaded and managed by the TrustZone (TZ) secure environment. Co-developed-by: Nikunj Kela <quic_nkela@quicinc.com> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20260617-enable-i2c-on-sa8255p-v7-1-ad736dbeab57@oss.qualcomm.com
2026-07-01dt-bindings: i2c: convert altera i2c to dt-schemaChaitanya Sabnis
Convert the Altera SoftIP I2C Controller bindings from legacy text format to modern dt-schema (YAML). The hardware constraints and properties remain identical. The example node was updated to use a standard 32-bit address space to clear compilation warnings. Signed-off-by: Chaitanya Sabnis <chaitanya.msabnis@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20260505053201.5795-1-chaitanya.msabnis@gmail.com
2026-07-01dt-bindings: i2c: convert axxia i2c to dt-schemaChaitanya Sabnis
Convert the LSI Axxia I2C Controller bindings from legacy text format to modern dt-schema (YAML). During the conversion, the obsolete `device_type = "i2c"` property was dropped from the example, as it is deprecated and not utilized by the driver. The `clock-names` property is enforced as required matching the driver probe behavior. The example node address was also updated to a standard 32-bit address. Signed-off-by: Chaitanya Sabnis <chaitanya.msabnis@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20260505100854.5258-1-chaitanya.msabnis@gmail.com
2026-07-01dt-bindings: pinctrl: qcom: Describe Maili TLMM blockJingyi Wang
The Top Level Mode Multiplexer (TLMM) in the Qualcomm Maili SoC provides GPIO and pinctrl functionality for UFS, SDC and 226 GPIO pins. Add a DeviceTree binding to describe the TLMM block on Qualcomm's Maili SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Acked-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20260622-maili-pinctrl-v3-1-9724e1000471@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-06-30ksmbd: doc: update feature support status for durable handles and compressionNamjae Jeon
Update ksmbd.rst to reflect the current implementation status of SMB features. Durable handles (v1, v2) and SMB3.1.1 Compression are now fully supported in ksmbd, so update their status from "Planned for future" to "Supported". Signed-off-by: Namjae Jeon <linkinjeon@kernel.org> Signed-off-by: Steve French <stfrench@microsoft.com>
2026-06-30media: dt-bindings: rc: Sync keymap list with latest listSean Young
The list is out of sync, so add missing entries, remove obsolete entries and sort. Signed-off-by: Sean Young <sean@mess.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2026-06-30dt-bindings: PCI: imx6q-pcie: Add i.MX95 optional intr/aer/pme interruptsRichard Zhu
The i.MX95 PCIe controller introduces three additional dedicated hardware interrupt lines for specific events: - intr: general controller events - aer: Advanced Error Reporting events - pme: Power Management Events These interrupts are optional on i.MX95. PCIe basic functionality (enumeration, configuration, and data transfer) works correctly without them, as the controller can operate using only the existing MSI interrupt. Earlier i.MX PCIe variants (imx6q, imx6sx, imx6qp, imx7d, imx8mm, imx8mp, imx8mq, imx8q) do not have these three dedicated interrupt lines. Update the binding to allow up to 5 interrupts for i.MX95, while restricting earlier variants to a maximum of 2 interrupts using conditional constraints (if/then schema). This ensures the schema accurately reflects the hardware capabilities of each SoC variant. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260618092100.3669556-2-hongxing.zhu@oss.nxp.com
2026-06-30ASoC: dt-bindings: Convert cirrus,cs35l36 to DT schemaDavid Heidelberg
Convert CS35L36 Speaker Amplifier to yaml. Changes: - maintainers email to the generic Cirrus email - Both the codec and downstream worked just fine without VP-supply provided. Align with datasheet for similar models. - add dai-common.yaml to cover for '#sound-dai-cells', 'sound-name-prefix' - updated not yet implemented: cirrus,weak-fet-delay -> cirrus,classh-wk-fet-delay-ms (in both definition and example) cirrus,weak-fet-thld -> cirrus,weak-fet-thld-millivolt (only in the example) - added two required properties: cirrus,boost-ctl-millivolt cirrus,boost-peak-milliamp Assisted-by: OpenAI:gpt-4 Reviewed-by: David Rhodes <David.Rhodes@cirrus.com> Co-developed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260624-dt-cirrus-cs35l36-v3-1-ec451d5a2908@ixit.cz Signed-off-by: Mark Brown <broonie@kernel.org>
2026-06-30spi: dt-bindings: snps,dw-apb-ssi: add 'power-domains' propertyWolfram Sang
This SPI controller likely belongs to a power domain for all the SoCs listed. For sure, it belongs to one on the Renesas RZ/N1 SoC, so enable the property to be able to describe its power domain in DTs. Suggested-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Herve Codina <herve.codina@bootlin.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260626180326.9593-3-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-06-30spi: dt-bindings: snps,dw-apb-ssi: drop superfluous RZ/N1 entryWolfram Sang
Commit 164c05f03ffa ("spi: Convert DW SPI binding to DT schema") added an RZ/N1 entry which was not in the original txt-file. It doesn't follow the usual "<soc entry>, <soc family entry>" style for Renesas SoCs which was properly added later with commit 029d32a892a8 ("spi: dw-apb-ssi: Integrate Renesas RZ/N1 SPI controller"). In that commit, removing the bogus entry was overlooked and is finally done now. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260626180326.9593-2-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-06-30dt-bindings: gpu: img,powervr-*: Remove Matt Coster as maintainerMatt Coster
I'm leaving Imagination; remove myself as a maintainer. A separate patch leaves a personal forwarding address in the .mailmap. Acked-by: Matt Coster <opensource@mtcoster.net> Acked-by: Alessio Belle <alessio.belle@imgtec.com> Link: https://patch.msgid.link/20260629-goodbye-v1-2-3bab53a80c53@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-06-30riscv: kexec_file: Add support for crashkernel CMA reservationJinjie Ruan
Commit 35c18f2933c5 ("Add a new optional ",cma" suffix to the crashkernel= command line option") and commit ab475510e042 ("kdump: implement reserve_crashkernel_cma") added CMA support for kdump crashkernel reservation. This allows the kernel to dynamically allocate contiguous memory for crash dumping when needed, rather than permanently reserving a fixed region at boot time. So extend crashkernel CMA reservation support to riscv. The following changes are made to enable CMA reservation: - Parse and obtain the CMA reservation size along with other crashkernel parameters. - Call reserve_crashkernel_cma() to allocate the CMA region for kdump. - Include the CMA-reserved ranges for kdump kernel to use, which was already done in of_kexec_alloc_and_setup_fdt(). - Exclude the CMA-reserved ranges from the crash kernel memory to prevent them from being exported through /proc/vmcore, which was already done in the crash core. Update kernel-parameters.txt to document CMA support for crashkernel on riscv architecture. Cc: Paul Walmsley <pjw@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexandre Ghiti <alex@ghiti.fr> Acked-by: Baoquan He <bhe@redhat.com> Acked-by: Mike Rapoport (Microsoft) <rppt@kernel.org> Acked-by: Paul Walmsley <pjw@kernel.org> # arch/riscv Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Link: https://patch.msgid.link/20260629094746.191843-11-ruanjinjie@huawei.com Signed-off-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
2026-06-30arm64: kexec_file: Add support for crashkernel CMA reservationJinjie Ruan
Commit 35c18f2933c5 ("Add a new optional ",cma" suffix to the crashkernel= command line option") and commit ab475510e042 ("kdump: implement reserve_crashkernel_cma") added CMA support for kdump crashkernel reservation. Crash kernel memory reservation wastes production resources if too large, risks kdump failure if too small, and faces allocation difficulties on fragmented systems due to contiguous block constraints. The new CMA-based crashkernel reservation scheme splits the "large fixed reservation" into a "small fixed region + large CMA dynamic region": the CMA memory is available to userspace during normal operation to avoid waste, and is reclaimed for kdump upon crash—saving memory while improving reliability. So extend crashkernel CMA reservation support to arm64. The following changes are made to enable CMA reservation: - Parse and obtain the CMA reservation size along with other crashkernel parameters. - Call reserve_crashkernel_cma() to allocate the CMA region for kdump. - Include the CMA-reserved ranges for kdump kernel to use. - Exclude the CMA-reserved ranges from the crash kernel memory to prevent them from being exported through /proc/vmcore, which is already done in the crash core. Update kernel-parameters.txt to document CMA support for crashkernel on arm64 architecture. Tested-by: Breno Leitao <leitao@debian.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Baoquan He <bhe@redhat.com> Acked-by: Mike Rapoport (Microsoft) <rppt@kernel.org> Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Link: https://patch.msgid.link/20260629094746.191843-10-ruanjinjie@huawei.com Signed-off-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
2026-06-30dt-bindings: arm: xen: Convert to DT schemaTejas Mutalikdesai
Convert the Xen ARM device tree binding documentation from the legacy plain-text format (Documentation/devicetree/bindings/arm/xen.txt) to the DT schema format, as required by the modern DT binding process. The "hypervisor" node is named without a unit-address. The name is part of the Xen ABI and is matched verbatim by the kernel using strcmp() in arch/arm/xen/enlighten.c and arch/arm64/kernel/acpi.c. Allow a unit-address so this can be addressed and the dtc warnings can be avoided in the example. Signed-off-by: Tejas Mutalikdesai <tejasmutalikdesai@gmail.com> Link: https://patch.msgid.link/20260618151147.9438-1-tejasmutalikdesai@gmail.com [robh: Allow a unit-address] Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-06-30dt-bindings: PCI: renesas,r9a08g045-pcie: Add RZ/V2H(P) supportLad Prabhakar
Add support for the PCIe controller found on the Renesas RZ/V2H(P) SoC. The RZ/V2H(P) controller is similar to the RZ/G3E variant but includes additional registers and configuration bits for PCIe lane control. It supports multilink operation configured as either a single x4 link or two independent x2 link controllers. Unlike earlier SoCs supported by this driver which only feature a single PCIe controller, the RZ/V2H(P) SoC implements two controllers. Both instances rely on the system controller (SYSC) for configuration, but the required registers reside at different offsets for each controller. To correctly identify the controller instance and map the corresponding system controller registers, update the "renesas,sysc" property to a phandle-array. For the RZ/V2H(P) SoC, require an accompanying cell to specify the controller instance index (0 or 1). For all earlier SoCs, strictly restrict the property to a single phandle with zero argument cells. Additionally, make the "num-lanes" property mandatory for this SoC and restrict its values according to the hardware capabilities. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260629220932.861445-2-prabhakar.mahadev-lad.rj@bp.renesas.com
2026-06-30dt-bindings: pinctrl: qcom,pmic-gpio: Document PMG1110 GPIO supportFenglin Wu
Update the binding documentation to include the compatible string for PMG1110 PMIC which is used on Maili platform. Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20260610-pmg1110-gpio-v1-1-a9c50cd8b5d9@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-06-30dt-bindings: Drop incorrect usage of double '::'Krzysztof Kozlowski
There is no use of double colon '::' in YAML. OTOH, the literal style block, e.g. using '|' treats all characters as content [1] therefore single use of ':' in descriptions is perfectly fine, whenever '|' is used. Cleanup existing code, so the confusing style won't be re-used in new contributions. Link: https://yaml.org/spec/1.2.2/#literal-style [1] Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patch.msgid.link/20260623054842.21831-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-06-30dt-bindings: clock: Drop incorrect usage of double '::'Krzysztof Kozlowski
There is no use of double colon '::' in YAML. OTOH, the literal style block, e.g. using '|' treats all characters as content [1] therefore single use of ':' in descriptions is perfectly fine, whenever '|' is used. Cleanup existing code, so the confusing style won't be re-used in new contributions. Link: https://yaml.org/spec/1.2.2/#literal-style [1] Acked-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Andi Shyti <andi.shyti@kernel.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://patch.msgid.link/20260623054842.21831-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-06-30Merge drm/drm-next into drm-intel-nextJani Nikula
Sync with v7.2-rc1. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-06-30dt-bindings: pinctrl: aspeed,ast2700-soc1: Add JTAGM1TRST groupBilly Tsai
The TRST signal of the JTAG master is optional and may not be wired on every design, but it is only selectable as part of the JTAGM1 group, which forces the D12 ball to be muxed whenever the JTAG master is used. Add a separate JTAGM1TRST group so boards can enable TRST independently of the other JTAG master signals. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-30regulator: rtq2208: Remove the unnecessary MTP_SEL propertyMark Brown
ChiYuan Huang <cy_huang@richtek.com> says: This patch series remove the 'richtek,mtp-sel-high' property usage. Link: https://patch.msgid.link/cover.1782444299.git.cy_huang@richtek.com
2026-06-30regulator: dt-bindings: rtq2208: Label mtp-sel-high property as deprecatedChiYuan Huang
Since it can be identified by hardware register, label the unnecessary property 'richtek,mtp-sel-high' as deprecated. Signed-off-by: ChiYuan Huang <cy_huang@richtek.com> Link: https://patch.msgid.link/594ebe167b33ca885c040984624e4b5d1382c0e2.1782444299.git.cy_huang@richtek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-06-30dmaengine: Add API to combine configuration and preparation (sg and single)Frank Li
Previously, configuration and preparation required two separate calls. This works well when configuration is done only once during initialization. However, in cases where the burst length or source/destination address must be adjusted for each transfer, calling two functions is verbose and requires additional locking to ensure both steps complete atomically. Add a new API dmaengine_prep_config_single() and dmaengine_prep_config_sg() and callback device_prep_config_sg() that combines configuration and preparation into a single operation. If the configuration argument is passed as NULL, fall back to the existing implementation. Tested-by: Niklas Cassel <cassel@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260521-dma_prep_config-v7-1-1f73f4899883@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-30dt-bindings: PCI: qcom,pcie-ipq9574: Add IPQ5210 compatibleVaradarajan Narayanan
Add the IPQ5210 compatible using IPQ9574 as fallback. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> [mani: commit log] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260610-ipq9650_pcie_binding-v2-2-69e27a1fbf1c@oss.qualcomm.com
2026-06-30dt-bindings: PCI: qcom,pcie-ipq9574: Add IPQ9650 compatibleKathiravan Thirumoorthy
Add the IPQ9650 PCIe compatible to the IPQ9574 binding, as the IPQ9650 controller is compatible with IPQ9574 and uses it as the fallback. While at it, make the global interrupt as required for IPQ9650. Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260610-ipq9650_pcie_binding-v2-1-69e27a1fbf1c@oss.qualcomm.com
2026-06-30dt-bindings: clock: renesas,versaclock7: Update maintainerBiju Das
Alex' email is bouncing. Update the maintainers list with my contact details to take over the schema maintenance. While at it, extend the entry in MAINTAINERS to the Versaclock 3 clock driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250905143441.7082-1-biju.das.jz@bp.renesas.com Link: https://patch.msgid.link/20260623162039.153291-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-30dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H familyJohn Madieu
RZ/V2H, RZ/V2N, and RZ/G3E support two optional external audio clock inputs (AUDIO_CLKB and AUDIO_CLKC) that can be used by the Audio Clock Generator (ADG) to derive internal audio clocks. The third ADG input (AUDIO_CLKA) is fed internally by the AUDIO_EXTAL pin and does not need a separate binding entry. Update the bindings to allow these optional clocks for all RZ/V2H family SoCs. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260525110603.4018170-2-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-30Merge drm/drm-next into drm-misc-nextThomas Zimmermann
Backmerging to get drm-misc-next to v7.2-rc1. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2026-06-30dt-bindings: iio: dac: ad5686: rework on power suppliesRodrigo Alencar
Add supplies for VDD, VLOGIC and VREF input voltage pins. The vcc-supply property is deprecated, once it does not really exist as none of the devices describe any power input with that name. VCC is also misleading as it sounds like the input power supply, but it is being used as an external voltage reference, which should be called VREF. Certain devices require vref-supply to be available once an internal reference voltage is absent. For correct operation vdd and vlogic supplies are required. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2026-06-30dt-bindings: iio: dac: ad5686: add reset/ldac/gain supportRodrigo Alencar
Add GPIO property for RESET, LDAC and GAIN pin. RESET is active-low, LDAC is used to load DAC channels with values from input registers and GAIN can double the voltage in output channels. The gain-gpios property is not available to all supported parts. The adi,range-double property indicates that GAIN pin is hardwired to high in case gain-gpios is not set, otherwise it sets the initial value for the gain setting. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2026-06-30dt-bindings: iio: dac: ad5696: rework on power suppliesRodrigo Alencar
Add supplies for VDD, VLOGIC and VREF input voltage pins. The vcc-supply property is deprecated, once it does not really exist as none of the devices describe any power input with that name. VCC is also misleading as it sounds like the input power supply, but it is being used as an external voltage reference, which should be called VREF. Certain devices require vref-supply to be available once an internal reference voltage is absent. For correct operation vdd and vlogic supplies are required. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2026-06-30dt-bindings: iio: dac: ad5696: add reset/ldac/gain supportRodrigo Alencar
Add GPIO property for RESET, LDAC and GAIN pin. RESET is active-low, LDAC is used to load DAC channels with values from input registers and GAIN can double the voltage in output channels. The gain-gpios property is not available to all supported parts. The adi,range-double property indicates that GAIN pin is hardwired to high in case gain-gpios is not set, otherwise it sets the initial value for the gain setting. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2026-06-30dt-bindings: iio: magnetometer: add QST QMC5883L SensorSiratul Islam
Add devicetree binding for the QST QMC5883L 3-Axis Magnetic Sensor connected via I2C. Used enum so that more devices could use this binding Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Siratul Islam <siratul.islam@linux.dev> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2026-06-30dt-bindings: add entry for qstcorpSiratul Islam
Add an entry for QST Corporation Limited Link: https://www.qstcorp.com/ Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Siratul Islam <siratul.islam@linux.dev> Link: https://www.qstcorp.com/ Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2026-06-30Documentation: ABI: testing: iio: minor cleanupManuel Ebner
Add parenthesis and dashes. Signed-off-by: Manuel Ebner <manuelebner@mailbox.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-22 16:47:07 +0000