summaryrefslogtreecommitdiff
path: root/Documentation
AgeCommit message (Collapse)Author
2026-05-13dt-bindings: arm: qcom: Add Microsoft Surface Pro 12inHarrison Vanderbyl
Document the compatible string for the Microsoft Surface Pro 12-inch, 1st Edition with Snapdragon, based on the Qualcomm X1P42100 SoC. Signed-off-by: Harrison Vanderbyl <harrison.vanderbyl@gmail.com> Link: https://lore.kernel.org/r/627a1e2506fbed99e971250dbba64902af54232c.1778498477.git.harrison.vanderbyl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13dt-bindings: clock: qcom: Add Hawi global clock controllerVivek Aknurwar
Add device tree bindings for the global clock controller on the Qualcomm Hawi SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Mike Tipton <mike.tipton@oss.qualcomm.com> Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260506-clk-hawi-v3-3-530b538679f1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13dt-bindings: clock: qcom: Add Hawi TCSR clock controllerVivek Aknurwar
Add bindings documentation for TCSR clock controller on the Qualcomm Hawi SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Mike Tipton <mike.tipton@oss.qualcomm.com> Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260506-clk-hawi-v3-2-530b538679f1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for HawiVivek Aknurwar
Update documentation for the RPMH clock controller on the Qualcomm Hawi SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Mike Tipton <mike.tipton@oss.qualcomm.com> Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260506-clk-hawi-v3-1-530b538679f1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13dt-bindings: soc: qcom,aoss-qmp: Document the Hawi AOSS side channelMukesh Ojha
Document the Always-on Subsystem side channel on Qualcomm Hawi SoC. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427181609.3648384-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13dt-bindings: soc: qcom: qcom,pmic-glink: Add Hawi compatible stringFenglin Wu
Hawi is a mobile platform that is compatible with Kaanapali platform with respect to pmic-glink support. Add the Hawi compatible string with Kaanapali as a fallback. Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260419-hawi-pmic-glink-v1-1-a26908c468fc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13dt-bindings: firmware: qcom,scm: Document SCM on Hawi SoCMukesh Ojha
Document SCM compatible for the Qualcomm Hawi SoC. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260401123825.589452-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13dt-bindings: cache: qcom,llcc: Document Hawi SoCFrancisco Munoz Ruiz
Add documentation for the Last Level Cache Controller (LLCC) bindings to support Hawi SoC where the System Cache Table (SCT) is programmed by firmware outside of Linux. Introduce a property that specifies the base address of the shared memory region from which the driver should read SCT descriptors provided by firmware. Signed-off-by: Francisco Munoz Ruiz <francisco.ruiz@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260407-external_llcc_changes2set-v2-1-b5017ce2020b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13dt-bindings: display: imx: add deprecated property 'port' and 'display-timings'Frank Li
Add deprecated property 'port' and 'display-timings' for i.MX5 SoCs (over 15 years) to fix below CHECK_DTBS warnings: arm/boot/dts/nxp/imx/imx51-apf51dev.dtb: disp1 (fsl,imx-parallel-display): 'display-timings', 'port' do not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/display/imx/fsl,imx-parallel-display.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260511220924.1905571-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-05-13dt-bindings: display/msm: qcom,eliza-mdss: Correct DPU and DP ranges in exampleKrzysztof Kozlowski
VBIF register range is 0x3000 long. DisplayPort block has few too short ranges and misses four more address spaces. Similarly first part of DSI space should be 0x300 long. No practical impact, except when existing code is being re-used in new contributions. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/716460/ Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-5-34f4024c65dc@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-05-13dt-bindings: display/msm: sm8750-mdss: Correct DPU and DP ranges in exampleKrzysztof Kozlowski
VBIF register range is 0x3000 long. DisplayPort block has few too short ranges and misses four more address spaces. No practical impact, except when existing code is being re-used in new contributions. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/716453/ Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-4-34f4024c65dc@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-05-13dt-bindings: display/msm: sm8650: Correct VBIF range in exampleKrzysztof Kozlowski
VBIF register range is 0x3000 long, so correct the example. No practical impact, except when existing code is being re-used in new contributions. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/716454/ Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-3-34f4024c65dc@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-05-13dt-bindings: display/msm: dp-controller: Allow DAI on SM8650 and othersKrzysztof Kozlowski
DisplayPort on Qualcomm SoCs like SM8650 and compatible SM8750 supports audio and there is already DTS having cells and sound-name-prefix. The "else:" clause for non-EDP and non-aux-bus cases already requires '#sound-dai-cells', so it should actually reference the dai-common.yaml for other properties, as pointed out by dtbs_check warnings like: sm8650-hdk-display-card-rear-camera-card.dtb: displayport-controller@af54000 (qcom,sm8650-dp): Unevaluated properties are not allowed ('sound-name-prefix' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/716452/ Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-2-34f4024c65dc@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-05-13dt-bindings: display/msm: dp-controller: Correct SM8650 IO rangeKrzysztof Kozlowski
DP on Qualcomm SM8650 come with nine address ranges, so describe the remaining ones as optional to keep ABI backwards compatible. Driver also does not need them to operate correctly. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/716450/ Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-1-34f4024c65dc@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-05-13dt-bindings: interrupt-controller: Document PDC for Qualcomm Nord SoCShawn Guo
Document Power Domain Controller on Qualcomm Nord SoC. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260504080703.825328-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-05-13dt-bindings: arm: cpus: Add compatible qcom,oryon-1-5Shawn Guo
Qualcomm Oryon 1-5 is found on Nord SoC. Add compatible for it. $ cat /proc/cpuinfo ... CPU implementer : 0x51 CPU architecture: 8 CPU variant : 0x5 CPU part : 0x001 CPU revision : 4 Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260427004619.229843-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-05-13Documentation/gpu/rfc: fix toctreeJani Nikula
Just one toctree is enough. The .rst suffixes are superfluous in the toctree. Fix indent. Add missing newline at the end of the file. Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Link: https://patch.msgid.link/c9678a78749a71cf86941f37116232dbc7c23b5f.1778238671.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-13Documentation/gpu: add some tables of contents to large documentsJani Nikula
Some of the GPU documentation pages are quite long, with various levels of details. Add document internal tables of contents to the larger documents to make them easier to navigate. The index.rst in the sub-directories have toctrees, which provide similar overviews. Fix one missing newline at the end of drm-uapi.rst while at it, primarily because rst should have it, and secondarily because my editor rst mode refuses to save the file without it. Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Link: https://patch.msgid.link/e3f9357c0e8198cc48e69e2a3b8ca072c7ab92ca.1778238671.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-13Documentation/gpu: limit main toctree depth to 2Jani Nikula
The main GPU documentation toctree has no limit to the toctree depth, which means the main GPU index page recursively includes all the headings in all of GPU documentation in the single table of contents. This makes getting any kind of overview of the documentation really difficult. Limit the main toctree depth to 2 i.e. show at most two levels of headings. Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Link: https://patch.msgid.link/cddd2d11c104132801510e3ab4e4b9ef3ea9cb6d.1778238671.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-13dt-bindings: gpio: Add EIO GPIO compatible to gpio-zynqShubhrajyoti Datta
EIO (Extended IO) GPIO is a Xilinx IP block that exposes multiplexed I/O pins through an EIO interface. The EIO GPIO block has 2 banks with 26 GPIOs each (52 total). The GPIO width cannot be determined from the hardware registers, the driver relies on the compatible string to select the correct bank/pin configuration. A new compatible is therefore required. The block is currently present on xa2ve3288 silicon. The compatible string uses version 1.0 matching the IP core version. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Link: https://patch.msgid.link/20260512060917.2096456-3-shubhrajyoti.datta@amd.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-05-13dt-bindings: gpio: zynq: Sort compatible strings alphabeticallyShubhrajyoti Datta
Sort the compatible string alphabetically. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Link: https://patch.msgid.link/20260512060917.2096456-2-shubhrajyoti.datta@amd.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-05-12dpll: add fractional frequency offset to pin-parent-deviceIvan Vecera
Add both fractional-frequency-offset (PPM) and fractional-frequency-offset-ppt (PPT) attributes to the pin-parent-device nested attribute set, alongside the existing top-level pin attributes. Both carry the same measurement at different precisions. Introduce enum dpll_ffo_type and struct dpll_ffo_param to distinguish FFO contexts: DPLL_FFO_PORT_RXTX_RATE for the RX vs TX symbol rate offset reported at the top level, and DPLL_FFO_PIN_DEVICE for the pin vs parent DPLL offset reported in the pin-parent-device nest. Add a supported_ffo bitmask to struct dpll_pin_ops so drivers declare which FFO types they support. The core only calls ffo_get for types the driver has opted into, eliminating the need for per-driver NULL pointer guards. Validate at pin registration time that supported_ffo is not set without an ffo_get callback. Update mlx5 (DPLL_FFO_PORT_RXTX_RATE) and zl3073x (DPLL_FFO_PORT_RXTX_RATE) drivers to use the new API. Add documentation for both FFO types to dpll.rst. Changes v3 -> v4: - Replace dpll=NULL overloading with enum dpll_ffo_type and struct dpll_ffo_param (Jakub Kicinski) - Add supported_ffo opt-in bitmask in dpll_pin_ops for fail-close driver validation (Jakub Kicinski) - Add WARN_ON in dpll_pin_register for supported_ffo without ffo_get callback Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ivan Vecera <ivecera@redhat.com> Link: https://patch.msgid.link/20260511155816.99936-2-ivecera@redhat.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-05-12dt-bindings: clock: qcom,sm6125-dispcc: reference qcom,gcc.yamlBiswapriyo Nath
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. This also adds the '#reset-cells' property which is permitted for the SM6125 SoC clock controllers, but not listed as a valid property. Fixes: bb4d28e377cf ("arm64: dts: qcom: sm6125: Add missing MDSS core reset") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202603150629.GYoouFwZ-lkp@intel.com/ Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-2-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-12Merge branch ↵Bjorn Andersson
'20260106-qcom_ipq5332_cmnpll-v2-2-f9f7e4efbd79@oss.qualcomm.com' into clk-for-7.2 Merge the introduction of qcom,ipq5332-cmn-pll DeviceTree binding through a topic branch, to make it available to DeviceTree source tree as well.
2026-05-12dt-bindings: clock: qcom: Add CMN PLL support for IPQ5332 SoCLuo Jie
Add device tree bindings for the CMN PLL block in IPQ5332 SoC, which shares similarities with IPQ9574 but has different output clock frequencies. Add a new header file to export CMN PLL output clock specifiers for IPQ5332 SoC. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106-qcom_ipq5332_cmnpll-v2-2-f9f7e4efbd79@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-12dt-bindings: PCI: Add UltraRISC DP1000 PCIe controllerJia Wang
Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: squash MAINTAINERS to driver commit update to touch only once] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com
2026-05-12Documentation: kvm: update links in the references section of AMD Memory ↵Ninad Naik
Encryption Replace non-working links in the reference section with the working ones. Signed-off-by: Ninad Naik <ninadnaik07@gmail.com> Link: https://patch.msgid.link/20260511174302.811918-1-ninadnaik07@gmail.com/ Reviewed-by: Liam Merwick <liam.merwick@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-05-12dt-bindings: clock: qcom,kaanapali-gxclkctl: Correctly use additionalPropertiesKrzysztof Kozlowski
The binding does not reference any other schema, thus should use "additionalProperties: false" to disallow any undocumented properties. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260404105436.138110-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-12Documentation: security-bugs: clarify requirements for AI-assisted reportsWilly Tarreau
AI tools are increasingly used to assist in bug discovery. While these tools can identify valid issues, reports that are submitted without manual verification often lack context, contain speculative impact assessments, or include unnecessary formatting. Such reports increase triage effort, waste maintainers' time and may be ignored. Reports where the reporter has verified the issue and the proposed fix typically meet quality standards. This documentation outlines specific requirements for length, formatting, and impact evaluation to reduce the effort needed to deal with these reports. Cc: Greg KH <gregkh@linuxfoundation.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Leon Romanovsky <leon@kernel.org> Signed-off-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20260509094755.2838-4-w@1wt.eu>
2026-05-12Documentation: security-bugs: explain what is and is not a security bugWilly Tarreau
The use of automated tools to find bugs in random locations of the kernel induces a raise of security reports even if most of them should just be reported as regular bugs. This patch is an attempt at drawing a line between what qualifies as a security bug and what does not, hoping to improve the situation and ease decision on the reporter's side. It defers the enumeration to a new file, threat-model.rst, that tries to enumerate various classes of issues that are and are not security bugs. This should permit to more easily update this file for various subsystem-specific rules without having to revisit the security bug reporting guide. Cc: Greg KH <gregkh@linuxfoundation.org> Cc: Leon Romanovsky <leon@kernel.org> Suggested-by: Leon Romanovsky <leon@kernel.org> Suggested-by: Greg KH <gregkh@linuxfoundation.org> Reviewed-by: Leon Romanovsky <leon@kernel.org> Reviewed-by: Shuah Khan <skhan@linuxfoundation.org> Signed-off-by: Willy Tarreau <w@1wt.eu> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20260509094755.2838-3-w@1wt.eu>
2026-05-12Documentation: security-bugs: do not systematically Cc the security teamWilly Tarreau
With the increase of automated reports, the security team is dealing with way more messages than really needed. The reporting process works well with most teams so there is no need to systematically involve the security team in reports. Let's suggest to keep it for small lists of recipients and new reporters only. This should continue to cover the risk of lost messages while reducing the volume from prolific reporters. Cc: Greg KH <gregkh@linuxfoundation.org> Cc: Leon Romanovsky <leon@kernel.org> Reviewed-by: Leon Romanovsky <leon@kernel.org> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20260509094755.2838-2-w@1wt.eu>
2026-05-12net: shaper: reject handle IDs exceeding internal bit-widthJakub Kicinski
net_shaper_parse_handle() reads the user-supplied handle ID via nla_get_u32(), accepting the full u32 range. However, the xarray key is built by net_shaper_handle_to_index() using FIELD_PREP(NET_SHAPER_ID_MASK, handle->id), where NET_SHAPER_ID_MASK is GENMASK(25, 0) - only 26 bits wide. FIELD_PREP silently masks off the upper bits at runtime. A user-supplied NODE id like 0x04000123 becomes id 0x123. Additionally, a user-supplied id equal to NET_SHAPER_ID_UNSPEC (0x03FFFFFF, which is NET_SHAPER_ID_MASK itself) would collide with the sentinel used internally by the group operation to signal "allocate a new NODE id". Reject user-supplied IDs >= NET_SHAPER_ID_MASK (i.e., >= 0x03FFFFFF) in the policy. Fixes: 4b623f9f0f59 ("net-shapers: implement NL get operation") Signed-off-by: Jakub Kicinski <kuba@kernel.org> Link: https://patch.msgid.link/20260510192904.3987113-9-kuba@kernel.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2026-05-12tools: ynl: add scope qualifier for definitionsJakub Kicinski
Using definitions in kernel policies is awkward right now. On one hand we want defines for max values and such. On the other we don't have a way of adding kernel-only defines. Adding unnecessary defines to uAPI is a bad idea, we won't be able to delete them. And when it comes to policy user space should just query it via the policy dump, not use hard coded defines. Add a "scope" property to definitions, which will let us tell the codegen that a definition is for kernel use only. Support following values: - uapi: render into the uAPI header (default, today's behavior) - kernel: render to kernel header only - user: same as kernel but for the user-side generated header Definitions may have a header property (definition is "external", provided by existing header). Extend the scope to headers, too. If definition has both scope and header properties we will only generate the includes in the right scope. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Link: https://patch.msgid.link/20260510192904.3987113-8-kuba@kernel.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2026-05-12Merge tag 'renesas-r9a08g046-dt-binding-defs-tag2' into renesas-dts-for-v7.2Geert Uytterhoeven
Renesas RZ/G3L DT Pin Control Binding Definitions Pin Control DT bindings and binding definitions for the Renesas RZ/G3L (R9A08G046) SoC, shared by driver and DT source files.
2026-05-12Merge tag 'renesas-r8a7740-dt-binding-defs-tag1' into renesas-dts-for-v7.2Geert Uytterhoeven
Renesas R-Mobile A1 Coresight Clock DT Binding Definitions ZT trace bus and ZTR trace clock DT binding definitions for the Renesas R-Mobile A1 (R8A7740) SoC, shared by driver and DT source files.
2026-05-11docs: acpi: dsd: add Motorcomm yt8xxx PHY propertieschunzhi.lin
Document Motorcomm yt8xxx PHY ACPI _DSD properties consumed by the motorcomm PHY driver. Describe property placement, UUID usage, and reference the DT binding for value constraints and defaults. Signed-off-by: chunzhi.lin <linchunzhi0@gmail.com> Changes in v2: - Keep dsd/ entries sorted in Documentation/firmware-guide/acpi/index.rst Link: https://patch.msgid.link/20260507040221.3679454-3-linchunzhi0@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-05-11dt-bindings: PCI: intel,lgm-pcie: Add 'atu' resourceFlorian Eckert
The 'atu' information is already set in the dwc core, if it is specified in the devicetree. The driver uses its own default, if not set in the devicetree. This information is hardware-specific and should therefore be maintained in the devicetree rather than in the source. To be backward compatible, this field is not mandatory. If 'atu' resource is not specified in the devicetree, the driver’s default value is used. Signed-off-by: Florian Eckert <fe@dev.tdt.de> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260417-pcie-intel-gw-v5-7-0a2b933fe04f@dev.tdt.de
2026-05-11dt-bindings: qcom: add IPQ9650 boardsKathiravan Thirumoorthy
Document the new IPQ9650 SoC/board device tree bindings. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-3-62742b49c991@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-11Merge branch ↵Bjorn Andersson
'20260507-ipq9650_boot_to_shell-v3-1-62742b49c991@oss.qualcomm.com' into arm64-for-7.2 Merge the QCS9650 GCC DeviceTree binding from topic branch, to get access to clock and reset constants.
2026-05-11Merge branch ↵Bjorn Andersson
'20260507-ipq9650_boot_to_shell-v3-1-62742b49c991@oss.qualcomm.com' into clk-for-7.2 Merge the IPQ9650 GCC DeviceTree binding, to allow constants to be made available to DeviceTree source tree as well.
2026-05-11dt-bindings: clock: add Qualcomm IPQ9650 GCCKathiravan Thirumoorthy
Add binding for the Qualcomm IPQ9650 Global Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-ipq9650_boot_to_shell-v3-1-62742b49c991@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-11docs: proc: add documentation about mount restrictionsAlexey Gladkov
procfs has a number of mounting restrictions that are not documented anywhere. Signed-off-by: Alexey Gladkov <legion@kernel.org> Link: https://patch.msgid.link/e7cb804df3c1759ee17cf9df1dc4c211d63d7a5f.1777278334.git.legion@kernel.org Reviewed-by: Aleksa Sarai <aleksa@amutable.com> Signed-off-by: Christian Brauner <brauner@kernel.org>
2026-05-11Merge branch 'ib-mux-pinctrl' into develLinus Walleij
2026-05-11dt-bindings: pinctrl: mediatek,mt65xx: Add MT6392 pinctrlLuca Leonardo Scorcia
Add a compatible for the pinctrl device of the MT6392 PMIC, a variant of the already supported MT6397. Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-11dt-bindings: pinctrl: mediatek: mt8188: allow gpio hogsIcenowy Zheng
Add gpio hogs subnode rules to the MT8188 pinctrl binding. Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-11dt-bindings: pinctrl: Add aspeed,ast2700-soc0-pinctrlBilly Tsai
Add a device tree binding for the pin controller found in the ASPEED AST2700 SoC0. The controller manages various peripheral functions such as eMMC, USB, VGA DDC, JTAG, and PCIe root complex signals. Describe the AST2700 SoC0 pin controller using standard pin multiplexing and configuration properties. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-11Documentation/amdgpu: Add documentation for Peak Tops Limiter (PTL) sysfs ↵Perry Yuan
interface The PTL (Peak Tops Limiter) feature exposes per-GPU sysfs files under /sys/class/drm/cardX/device/ptl/ to allow users to enable or disable PTL, configure preferred data formats, and query supported formats. The usage of these sysfs files is not always obvious, so add documentation to describe their purpose and provide concrete usage examples. V3 changes: * format show will display preferred formats instead of N/A (Alex) Signed-off-by: Perry Yuan <perry.yuan@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11dt-bindings: mmc: spacemit,sdhci: add pinctrl support for voltage switchingIker Pedrosa
Document pinctrl properties to support voltage-dependent pin configuration switching for UHS-I SD card modes. Add optional pinctrl-names property with two states: - "default": For 3.3V operation with standard drive strength - "state_uhs": For 1.8V operation with optimized drive strength These pinctrl states allow the SDHCI driver to coordinate voltage switching with pin configuration changes, ensuring proper signal integrity during UHS-I mode transitions. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Iker Pedrosa <ikerpedrosam@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-05-11dt-bindings: serial: snps-dw-apb-uart: Add UltraRISC DP1000 UARTJia Wang
UltraRISC DP1000 integrates a Synopsys DesignWare APB UART, but it does not provide the standard CPR and UCV registers. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260429-ultrarisc-serial-v7-3-e475cce9e274@ultrarisc.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-05-11dt-bindings: mmc: renesas,sdhi: Document R-Car M3Le supportMarek Vasut
Document support for the SD Card/MMC Interface in the Renesas R-Car M3Le (R8A779MD) SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-20 05:35:22 +0000