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2026-07-19arm64: dts: apple: t60xx: jxxx: Add device-specific SMC hwmon sensorsJames Calligeros
Add the device-specific hwmon sensors for select T60xx-based devices Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-12-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19arm64: dts: apple: t8112: jxxx: Add device-specific SMC hwmon sensorsJames Calligeros
Add the device-specific hwmon sensors for select T8112-based devices Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-11-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19arm64: dts: apple: t8103: jxxx: Add device-specific SMC hwmon sensorsJames Calligeros
Add the device-specific hwmon sensors for select T8103-based devices Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-10-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19arm64: dts: apple: t602x: Add common SMC hwmon sensorsJames Calligeros
Add the SMC hwmon sensors common to all SoCs Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-9-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19arm64: dts: apple: t600x: Add common SMC hwmon sensorsJames Calligeros
Add the SMC hwmon sensors common to all SoCs Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-8-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19arm64: dts: apple: t8112: Add common SMC hwmon sensorsJames Calligeros
Add the SMC hwmon sensors common to all SoCs Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-7-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19arm64: dts: apple: t8103: Add common SMC hwmon sensorsJames Calligeros
Add the SMC hwmon sensors common to all SoCs Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-6-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19arm64: dts: apple: Add common SMC hwmon infrastructureJames Calligeros
Apple's System Management Controller exposes the readings from numerous sensors scattered around the SoC and elsewhere in the machine. Some of these sensors are reliably common on all devices, whereas others are exposed at SMC keys specific to either the SoC or even the particular device. To account for this and expose the right sensors for the right device without tedious Devicetree duplication, we can include fragments of increasing specificity in the per-device .dts files such that the individual keys (of which there are potentially hundreds) do not need to be copied in for every device. Add the initial set of SMC hwmon sensors that are common to multiple devices so that they can be included in the per-device Devicetrees. Co-developed-by: Janne Grunau <j@jannau.net> Signed-off-by: Janne Grunau <j@jannau.net> Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-5-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19arm64: dts: apple: t602x: Add SMC hwmon nodeJames Calligeros
Add the SMC hwmon subdevice Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-4-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19arm64: dts: apple: t600x: Add SMC hwmon nodeJames Calligeros
Add the SMC hwmon subdevice Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-3-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19arm64: dts: apple: t8103: Add SMC hwmon nodeJames Calligeros
Add the SMC hwmon subdevice Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-2-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19arm64: dts: apple: t8112: Add SMC hwmon nodeJames Calligeros
Add the SMC hwmon subdevice Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-1-13fa78873121@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-19alpha: enable lockdep hardirq state trackingMagnus Lindholm
Alpha masks interrupts through the PAL IPL state, so lockdep cannot infer hardirq state transitions from generic code alone. Add explicit hardirq on/off annotations to the low-level entry and return paths so lockdep's IRQ state follows the hardware IPL state. Annotate the PAL IPL transitions and the shared return-to-user/kernel paths where interrupts become enabled or disabled. With the preceding irqflags, raw-lock, sysfs, and ftrace return-address preparations in place, select LOCKDEP_SUPPORT and TRACE_IRQFLAGS_SUPPORT for Alpha. This keeps CONFIG_PROVE_LOCKING usable on Alpha instead of disabling debug_locks due to IRQ-state mismatches. Reviewed-by: Matt Turner <mattst88@gmail.com> Tested-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Magnus Lindholm <linmag7@gmail.com> Link: https://lore.kernel.org/r/20260706170019.2941459-7-linmag7@gmail.com Signed-off-by: Magnus Lindholm <linmag7@gmail.com>
2026-07-19alpha: use raw spinlocks for low-level platform locksMagnus Lindholm
Some Alpha platform locks are used as low-level hardware serialization locks in interrupt-controller and chipset access paths. These paths can run while IRQ state is being changed or while lockdep is tracking that state, so regular spinlock instrumentation is not appropriate once lockdep is enabled. Convert the affected Tsunami and Rawhide platform locks to raw_spinlock_t. This keeps the locks as simple hardware serialization locks and avoids lockdep recursion or IRQ-state mismatches when CONFIG_PROVE_LOCKING is enabled. This is a preparatory change for enabling lockdep hardirq state tracking on Alpha. Reviewed-by: Matt Turner <mattst88@gmail.com> Tested-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Magnus Lindholm <linmag7@gmail.com> Link: https://lore.kernel.org/r/20260706170019.2941459-6-linmag7@gmail.com Signed-off-by: Magnus Lindholm <linmag7@gmail.com>
2026-07-19alpha: provide ftrace return address support for lockdepMagnus Lindholm
Lockdep uses ftrace_return_address() to report useful call sites for lock acquisition and IRQ-state tracking diagnostics. Provide the Alpha architecture hook using the compiler return-address builtin when frame pointers are available. Return zero when frame pointers are disabled, matching the existing fallback behavior of architectures that cannot provide a reliable return address. This is a preparatory change for enabling lockdep support on Alpha. Reviewed-by: Matt Turner <mattst88@gmail.com> Tested-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Magnus Lindholm <linmag7@gmail.com> Link: https://lore.kernel.org/r/20260706170019.2941459-5-linmag7@gmail.com Signed-off-by: Magnus Lindholm <linmag7@gmail.com>
2026-07-19alpha: make irqflags helpers operate on IPL stateMagnus Lindholm
Alpha interrupt masking is controlled by the PAL IPL value, not by the full processor status word. Make arch_local_save_flags() return the current IPL directly, and make arch_local_irq_restore() and arch_irqs_disabled_flags() treat their argument as IPL state. Mask the low IPL bits in the restore and test helpers so callers which still pass a saved PS value continue to behave as expected. This prepares the irqflags helpers for lockdep IRQ-state tracking, where the saved flags value is used to determine whether hard IRQs are enabled or disabled. Reviewed-by: Matt Turner <mattst88@gmail.com> Tested-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Magnus Lindholm <linmag7@gmail.com> Link: https://lore.kernel.org/r/20260706170019.2941459-4-linmag7@gmail.com Signed-off-by: Magnus Lindholm <linmag7@gmail.com>
2026-07-19alpha: add ARCH_STACKWALK-based stacktrace supportMagnus Lindholm
Implement arch_stack_walk() for Alpha using a simple kernel stack scanning walker. Start from regs+1 for current tasks to skip pt_regs and use pcb.ksp for blocked tasks. Filter candidates with __kernel_text_address() and stop at stack bounds via kstack_end(). Enable CONFIG_STACKTRACE_SUPPORT and CONFIG_ARCH_STACKWALK so generic stacktrace users (dump_stack(), /proc/*/stack, SysRq backtraces, etc.) work on Alpha. This provides functional in-kernel stack traces without requiring frame pointer unwinding. Reviewed-by: Matt Turner <mattst88@gmail.com> Tested-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Magnus Lindholm <linmag7@gmail.com> Link: https://lore.kernel.org/r/20260706170019.2941459-3-linmag7@gmail.com Signed-off-by: Magnus Lindholm <linmag7@gmail.com>
2026-07-19alpha: enable regset-based ptrace and core dumpsMagnus Lindholm
Add a user_regset_view for Alpha and switch ELF core dumping to CORE_DUMP_USE_REGSET. General-purpose registers are exported in ELF gregs layout, including callee-saved registers and a correct user stack pointer. The user stack pointer is not preserved in pt_regs on Alpha, so expose it from the PCB, or via rdusp() for the current task, when building the ELF register image. This makes the user stack pointer consistent for core dumps, ptrace regsets, and PTRACE_GET_SYSCALL_INFO. Implement regset get/set callbacks for both NT_PRSTATUS and NT_PRFPREG. The callbacks translate between Alpha's pt_regs/thread state and the ELF-visible register layouts, while the common ptrace regset code handles PTRACE_GETREGSET and PTRACE_SETREGSET iovec semantics. This avoids duplicating subtle short-buffer and oversized-buffer behavior in arch_ptrace(). With these changes Alpha satisfies the requirements for HAVE_ARCH_TRACEHOOK and selects it, enabling generic tracehook and ptrace syscall-info code paths without changing the existing syscall entry ABI. Reviewed-by: Matt Turner <mattst88@gmail.com> Tested-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Magnus Lindholm <linmag7@gmail.com> Link: https://lore.kernel.org/r/20260706170019.2941459-2-linmag7@gmail.com Signed-off-by: Magnus Lindholm <linmag7@gmail.com>
2026-07-19x86/mce: Work around build warning after MSR-interface switchJuergen Gross
The recent switch to 64-bit MSR interfaces introduced a build warning. Work it around with a __maybe_unused annotation. After the full conversion of the APIs we'll be able to address this more robustly by making sure the APIs consume all the values as far the compiler is concerned, so that the compiler doesn't emit such nuisance warnings. [ mingo: Updated the changelog. ] Fixes: cff219368bd0 ("x86/mce: Stop using 32-bit MSR interfaces") Closes: https://lore.kernel.org/oe-kbuild-all/202607031726.ZOwu4snu-lkp@intel.com/ Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://patch.msgid.link/20260703105555.1758819-1-jgross@suse.com
2026-07-18Merge tag 's390-7.2-5' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux Pull s390 fixes from Vasily Gorbik: - Fix checksum lib on machines without the vector facility where the non-vector fallback made csum_partial() calculate the checksum from address 0 instead of the provided buffer - Fix cpum_cf perf event initialization missing speculation barrier for user controlled event numbers used as generic event array indexes * tag 's390-7.2-5' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: s390/perf_cpum_cf: Add missing array_index_nospec() to __hw_perf_event_init() s390/checksum: Fix csum_partial() without vector facility
2026-07-18Merge tag 'arc-7.2-fixes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC fixes from Vineet Gupta: - Misc fixes and config updates * tag 'arc-7.2-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: configs: Drop redundant I2C_DESIGNWARE_PLATFORM arc: validate DT CPU map strings before parsing them
2026-07-18arm64: dts: qcom: glymur: Add CX power domain to GCCAbel Vesa
The GCC GDSCs on Glymur are backed by the RPMh CX power domain. Without describing that parent domain, consumers of GCC-provided GDSCs can enable their local domain without causing the required CX vote to be held. Add the CX power-domain reference to the GCC node so votes from GCC GDSC consumers can propagate to RPMh CX. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260715-glymur-fix-gcc-cx-scaling-v3-3-72eb5adad156@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-18arm64: dts: qcom: glymur: Drop fake PCIe phy 3BKrzysztof Kozlowski
According to user manual / programming guide there is no separate PCIe phy 3A and 3B, but one 8-lane QMP PCIe Gen5 PHY which consists of two 4-lane blocks. This is also visible in memory map, where the 0xf00000 is marked as the main block with additional sub blocks for each 4-lane phys. Describing the sub phys without the rest is not correct from hardware description, even if it works. Link: https://lore.kernel.org/r/20260420-optimistic-unnatural-stingray-80da35@quoll/ Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609141608.354186-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-18arm64: dts: qcom: glymur: add TRNG nodeHarshal Dev
Glymur has a True Random Number Generator, add the node with the correct compatible set. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260424-glymur_trng_enablement-v2-2-0603cbe68440@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-18arm64: dts: qcom: glymur: enable ETR and CTCU devicesJie Gan
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device and the CTCU device serves as the control unit for the ETR device. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260714-add-ctcu-etr-for-glymur-v1-1-791de63c0713@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-18arm64: dts: qcom: glymur: Add PCIe port compatibles and portsKonrad Dybcio
Centrally define the endpoints to let device DTs that describe PCIe devices and/or M.2 connectors refer to them without error-prone duplication. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260716-topic-smb2370_port2-v1-2-83d02b2ba4b0@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-18arm64: dts: qcom: smb2370: Disable SMB2370_2 by defaultKonrad Dybcio
It's absent on laptops that only have 2 type-C ports (the majority so far, including the CRD). Keep it disabled by default, following established practice from the previous generation. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260716-topic-smb2370_port2-v1-1-83d02b2ba4b0@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-17Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf 7.2-rc4Kumar Kartikeya Dwivedi
Cross-merge BPF and other fixes after downstream PR. Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
2026-07-17arm64: kprobes: Allow reentering kprobes while single-steppingPu Hu
A kprobe can be hit while another kprobe is in KPROBE_HIT_SS state. This can happen when tracing or perf code runs from the debug exception path while the first kprobe is preparing or executing its out-of-line single-step instruction. Currently arm64 treats a kprobe hit in KPROBE_HIT_SS as unrecoverable, the same as a hit in KPROBE_REENTER. This is too strict. A hit in KPROBE_HIT_SS is still a one-level reentry and can be handled by saving the current kprobe state and setting up single-step for the new probe, just like reentry from KPROBE_HIT_ACTIVE or KPROBE_HIT_SSDONE. The truly unrecoverable case is hitting another kprobe while already in KPROBE_REENTER, because the reentry save area has already been consumed. Move KPROBE_HIT_SS to the recoverable reentry cases and leave KPROBE_REENTER as the unrecoverable nested reentry case. This change also requires saving saved_irqflag in struct prev_kprobe. When a nested kprobe calls kprobes_save_local_irqflag(), it overwrites kcb->saved_irqflag with the currently masked DAIF value, losing the outer kprobe's original DAIF state. Without this fix, when the outer kprobe's single-step finishes, kprobes_restore_local_irqflag() applies the wrong DAIF mask and leaves interrupts permanently disabled. Extend struct prev_kprobe with a saved_irqflag field and save/restore it alongside kp and status. This ensures the outer kprobe's original interrupt state is preserved across reentry. This mirrors the x86 fix in commit 6a5022a56ac3 ("kprobes/x86: Allow to handle reentered kprobe on single-stepping"). Signed-off-by: Pu Hu <hupu@transsion.com> Signed-off-by: Hongyan Xia <hongyan.xia@transsion.com> Reviewed-by: Masami Hiramatsu (Google) <mhiramat@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
2026-07-17arm64: kprobes: Only handle faults originating from XOL slotPu Hu
kprobe_fault_handler() currently treats any page fault taken while in KPROBE_HIT_SS or KPROBE_REENTER state as a kprobe single-step fault. This assumption does not hold: perf or tracing code may run from the debug exception path during the single-step window and take its own page fault. When the fault is handled as a kprobe fault, the PC is rewritten to the probe address, corrupting the exception recovery context for the real fault. A typical reproducer is running perf with preemptirq tracepoints and dwarf callchains while a kprobe is installed on a frequently executed function. Fix this in two layers: 1. At function entry, bail out immediately for simulated kprobes (ainsn.xol_insn == NULL), since they have no XOL slot and any fault taken during their execution cannot be a single-step fault. 2. For kprobes with an XOL slot, only handle the fault when the faulting PC matches the XOL instruction address. Faults from any other PC are left to the normal page fault handler. This follows the same principle as the x86 fix in commit 6381c24cd6d5 ("kprobes/x86: Fix page-fault handling logic"). Signed-off-by: Pu Hu <hupu@transsion.com> Signed-off-by: Hongyan Xia <hongyan.xia@transsion.com> Reviewed-by: Masami Hiramatsu (Google) <mhiramat@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
2026-07-17Revert "arm64: syscall: Ensure saved x0 is kept in-sync with tracer updates"Will Deacon
This reverts commit e057b94772328221405b067c3a85fe479b915dc8. Sashiko points out that updating 'orig_x0' after secure_computing() has returned is too late to handle the case where a seccomp filter is re-evaluated after initially returning SECCOMP_RET_TRACE. This means that a tracer can manipulate the first argument of the syscall behind seccomp's back. For now, revert the initial fix and we'll have another crack at it soon. Since the incorrect fix was cc'd to stable, do the same here with an appropriate fixes tag. Cc: stable@vger.kernel.org Fixes: e057b9477232 ("arm64: syscall: Ensure saved x0 is kept in-sync with tracer updates") Link: https://sashiko.dev/#/patchset/20260716120640.6590-1-will@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2026-07-17Merge tag 'soc-fixes-7.2-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC fixes from Arnd Bergmann: "There are only three devicetree fixes this time: one critical memory corruption fix for Renesas and three minor corrections for Tegra. The MAINTAINERS file is updated for a new maintainer of the CIX platform and two address changes. The rest is all driver fixes, mostly firmware: - multiple runtime issues in ARM SCMI and FF-A firmware code, dealing with error handling for corner cases in firmware. - multiple fixes for reset drivers, dealing with individual platform specific mistakes and more error handling - minor build and runtime fixes for the Tegra SoC drivers" * tag 'soc-fixes-7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: renesas: ironhide: Describe inline ECC carveouts MAINTAINERS: Update maintainer and git tree for CIX SoC ARM: Don't let ARMv5 platforms select USE_OF MAINTAINERS: Update SpacemiT SoC git tree repository firmware: arm_scmi: Rate-limit queue-full warnings in IRQ context firmware: arm_scmi: Use 64-bit division for clock rate rounding reset: imx7: Correct polarity of MIPI CSI resets on i.MX8MQ reset: sunxi: fix memory region leak on ioremap failure dt-bindings: reset: altr: add COMBOPHY_RESET for Agilex5 reset: spacemit: k3: fix USB2 ahb reset firmware: arm_scmi: Grammar s/may needed/may be needed/ firmware: arm_ffa: Fix NULL dereference in ffa_partition_info_get() firmware: arm_ffa: Respect firmware advertised RX/TX buffer size limits arm64: tegra: Fix CPU1 node unit-address on Tegra264 arm64: tegra: Fix CPU compatible string to cortex-a78ae on Tegra234 MAINTAINERS: .mailmap: update Jens Wiklander's email address soc/tegra: fuse: Fix spurious straps warning on SMCCC platforms soc/tegra: pmc: fix #ifdef block in header drm/tegra: Fix a strange error handling path arm64: tegra: Remove fallback compatible for GPCDMA
2026-07-17ARM: dts: ls1021a-qds: add compatible string "fsl,ls1021aqds-fpga" for on ↵Frank Li
boards FPGA chip Add front compatible string "fsl,ls1021aqds-fpga" for on boards FPGA chip and remove unused property bank-width and device-width, which used for MTD devices and FPGA is not a MTD devices. Fix below CHECK_DTBS warning: rch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0: 'oneOf' conditional failed, one must be fixed: 'bank-width', 'device-width' do not match any of the regexes: '^gpio@[0-9a-f]+$', '^mdio-mux@[a-f0-9,]+$', '^pinctrl-[0-9]+$' /home/lizhi/source/linux-upstream-pci-ep-arm/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0:compatible: 'oneOf' conditional failed, one must be fixed: ['simple-mfd'] is too short arch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'bank-width', 'compatible', 'device-width', 'mdio-mux@54', 'ranges', 'reg' were unexpected) Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17Merge tag 'powerpc-7.2-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Madhavan Srinivasan: - Enable CONFIG_VPA_PMU to be used with KVM - Initialize starttime at boot for native accounting - Set CPU_FTR_P11_PVR for Power11 and later processors - fix memory leak on krealloc failure in papr_init - Misc fixes and cleanups Thanks to Amit Machhiwal, Christophe Leroy (CS GROUP), Ethan Nelson-Moore, Gautam Menghani, Harsh Prateek Bora, Junrui Luo, Mukesh Kumar Chaurasiya (IBM), Ritesh Harjani (IBM), Rosen Penev, Shrikanth Hegde, Thorsten Blum, and Yuhao Jiang * tag 'powerpc-7.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc: Remove dead non-preemption code powerpc/dt_cpu_ftrs: Set CPU_FTR_P11_PVR for Power11 and later processors powerpc/pseries: fix memory leak on krealloc failure in papr_init powerpc/uaccess: correct check for CONFIG_PPC_E500 in mask_user_address() powerpc/vtime: Initialize starttime at boot for native accounting powerpc/85xx: Add fsl,ifc to common device ids powerpc/spufs: fix out-of-bounds access in spufs_mem_mmap_access() powerpc/pseries/Kconfig: Enable CONFIG_VPA_PMU to be used with KVM
2026-07-17arm64: dts: imx943-evk: Remove 'supports-clkreq' from PCIe1Richard Zhu
Remove the 'supports-clkreq' property from PCIe1 as the standard PCIe slot on i.MX943 EVK may not have CLKREQ# signal wired, causing compatibility issues with some PCIe cards. Fixes: 9a8f11f6f786 ("arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support") Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: imx91-9x9-qsb: add CAN support overlay fileHaibo Chen
On the i.MX91 9x9 QSB, CAN1 and MICFIL share pins. A TMUX1574RSVR analog mux controls the routing: when SEL is driven high, CAN1 is selected; when SEL is driven low, MICFIL is selected. By default, SEL is kept low. To enable CAN1, SEL must be driven high. This is done via the can_fun function defined in the pinctrl-gpiomux node. CAN1 uses the TJA1057GT/3 PHY. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: imx8qm-var-som: Add support for Variscite Symphony boardStefano Radaelli
Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-MX8 QuadMax system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart, SPI and I2C interfaces - GPIO Expanders - RTC module - TPM module - CAN peripherals - PCIE support Link: https://variscite.com/carrier-boards/symphony-board/ Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: freescale: Add support for Variscite VAR-SOM-MX8 QuadMaxStefano Radaelli
Add device tree support for the Variscite VAR-SOM-MX8 QuadMax system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX8 QuadMax MPU processor - Up to 8GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quadplus/var-som-mx8/ Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: imx8mn-var-som-symphony: Disable internal RTCStefano Radaelli
Disable the internal SNVS RTC on the Symphony carrier board and use the external DS1337 RTC instead. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: imx8mn-var-som-symphony: enable PWM1Stefano Radaelli
Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: imx8mn-var-som-symphony: keep RGB_SEL lowStefano Radaelli
Keep the RGB_SEL line driven low on the Symphony carrier board. This avoids leaving the line floating and ensures the board remains in the expected display configuration. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: imx8mn-var-som-symphony: add wakeup sourcesStefano Radaelli
Mark the Symphony carrier board GPIO keys and capacitive touchscreen as wakeup sources. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: imx8mn-var-som-symphony: Enable I2C4Stefano Radaelli
Enable I2C4 on the Symphony carrier and add pinctrl configuration, including GPIO-based bus recovery support. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: imx8mn-var-som-symphony: Add TPM2 supportStefano Radaelli
Add support for the TPM2 device on the VAR-SOM Symphony carrier board. The ST33K TPM2 is connected over I2C, and A PCA6408 GPIO expander is used to control the reset signal required to release the TPM from reset. Add the PCA6408 GPIO expander and the ST33K TPM2 device node. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interfaceStefano Radaelli
Enable the FlexSPI controller on the VAR-SOM-MX8MN and add the corresponding pin multiplexing configuration. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: freescale: imx8mn-var-som: drop duplicate USB OTG nodeStefano Radaelli
The VAR-SOM-MX8MN module does not provide an onboard USB connector. The complete USB OTG description, including the Type-C role switch configuration, is already provided by the Symphony carrier board device tree. Remove the duplicate USB OTG node from the SOM dtsi to avoid describing the same hardware in two places. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy dtsStefano Radaelli
The VAR-SOM-MX8MN currently integrates the NXP IW61x wireless module, providing WiFi over SDIO and Bluetooth over UART. Move the wireless module configuration out of the base imx8mn-var-som.dtsi and provide dedicated variant includes. The IW61x configuration is moved to imx8mn-var-som-wifi-bt-iw61x.dtsi and used by the Symphony evaluation board device tree. A separate imx8mn-var-som-wifi-brcm-legacy.dtsi include is added to keep the configuration for the legacy Broadcom SDIO WiFi module used on earlier SOM revisions. To preserve compatibility with older SOM revisions, add a separate imx8mn-var-som-symphony-legacy.dtb, which disables the IW61x setup and applies the Broadcom-specific configuration. The Broadcom-based SOM revision is no longer in production, but support is kept for existing users. This keeps the VAR-SOM-MX8MN support aligned with the existing VAR-SOM-MX8MM implementation. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: freescale: imx8mn-var-som: Add MCP251xFD CAN controllerStefano Radaelli
Add support for the Microchip MCP251xFD CAN-FD controller connected to the SPI bus on the i.MX8MN VAR-SOM. The controller uses a 40 MHz external oscillator and requires an interrupt line and a dedicated RX interrupt GPIO. Add the fixed clock, the MCP251xFD device node with the required properties, and the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codecStefano Radaelli
The VAR-SOM-MX8MN can integrate the WM8904, a high-performance ultra-low-power stereo codec optimized for portable audio applications. Add the WM8904 device to the appropriate I2C bus, enable the SAI peripheral, and introduce the sound node to expose the sound card to the system. Add I2C3 recovery gpio properties. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: freescale: imx8mn-var-som: Update FEC support with MaxLinear PHYStefano Radaelli
Update the FEC Ethernet controller on the i.MX8MN VAR-SOM to match the latest SOM hardware revision using the integrated MaxLinear MXL86110 PHY. Add the PHY VDDIO supply regulator and adjust reset timings. The PHY LED signals originate on the SOM, but the actual LEDs are part of the carrier implementation (RJ45 connector). Move the LED configuration to the Symphony carrier device tree, matching the evaluation board LED wiring. Wake-on-LAN via magic packet is not supported at the VAR-SOM level and is therefore not enabled in the SOM device tree nor in the official evaluation carrier board configuration (symphony). Designs requiring WoL support may enable it in their own carrier-specific device trees if properly integrated at the hardware level. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-22 20:39:06 +0000