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2026-07-17arm64: dts: freescale: imx8mn-var-som: Align fsl,pins tablesStefano Radaelli
Reformat the fsl,pins tables in the i.MX8MN VAR-SOM device tree to use consistent column alignment across all pinctrl groups. Align the entries to match the formatting already used in the pinctrl_fec1 group, which contains the longest pin definitions, for improved readability and consistency. No functional changes intended. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: freescale: imx8mn-var-som: move uSD support to carrier boardsStefano Radaelli
The VAR-SOM-MX8MN module does not provide an onboard SD card slot. USDHC2 is routed to the SD card slot on the carrier boards. Move the USDHC2 node and pinctrl configuration from the SOM device tree to imx8mn-var-som-symphony.dts and imx8mn-rve-gateway.dts, keeping the SOM dtsi limited to hardware present on the module itself. Add the required off-on-delay-us property for the USDHC2 regulator on the Symphony carrier board. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17arm64: dts: freescale: imx8mn-var-som: Move UART4 description to SymphonyStefano Radaelli
The VAR-SOM-MX8MN module does not provide an onboard debug console. UART4 is routed and exposed only on the Symphony carrier board, while custom carrier designs may choose to expose a different UART. Move the UART4 node from the SOM device tree to the imx8mn-var-som-symphony.dts, keeping the SOM dtsi limited to hardware present on the module itself. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-17MIPS: BCM47XX: Convert buttons to software nodesDmitry Torokhov
Convert the legacy gpio-keys platform device on BCM47XX boards to use software nodes/properties. This allows us to describe the GPIO keys and their GPIO bindings using software nodes, so that support for platform data can eventually be removed from the gpio-keys driver. Detect the active bus type (BCMA or SSB) and reference the corresponding GPIO controller's software node (bcma_gpio_swnode or ssb_gpio_swnode) in the button properties. Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Assisted-by: Antigravity:gemini-3.5-flash Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17MIPS: ip22-gio: Drop #include of <linux/mod_devicetable.h>Uwe Kleine-König (The Capable Hub)
That header doesn't use any device id provided by <linux/mod_devicetable.h>. Also the users of <asm/gio_device.h> (i.e. arch/mips/sgi-ip22/ip22-gio.c and drivers/video/console/newport_con.c) don't use any of them and they compile fine in a mips allmodconfig. So drop the unused include that only yields unnecessary recompilations when a device id struct changes. Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17MIPS: TXX9: Clean up txx9_iocled_init()Geert Uytterhoeven
The sole caller already uses dynamic GPIO base allocation, so drop support for static allocation. While at it, drop the no longer used "lowactive" parameter. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17MIPS: TXX9: Convert gpio_txx9 to dynamic GPIO base allocationGeert Uytterhoeven
Static allocation of GPIO base is deprecated, use dynamic allocation. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17MIPS: TXX9: Drop GPIOLIB_LEGACY selectGeert Uytterhoeven
TXx has been converted away from the old-style gpiolib interfaces. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17MIPS: TXX9: Use GPIO lookup table for iocled LEDsGeert Uytterhoeven
Convert iocled LED description from legacy GPIO numbers to GPIO descriptors using a GPIO lookup table. For now, just ignore the "lowactive" parameter, and force GPIO_ACTIVE_LOW, as that is what the sole caller wants. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17MIPS: TXX9: Reduce TXX9_IOCLED_MAXLEDS to 3Geert Uytterhoeven
The number of available GPIOs and LEDs on the TXx9 IOC FPGA depends on the platform. Since commit 455481fc9a807798 ("MIPS: Remove TX39XX support"), the only remaining platform (rbtx4927) supports just three. Hence reduce the maximum number, to reduce allocation size. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17MIPS: TXX9: rbtx4927: Use GPIO lookup table for TXx9 LEDsGeert Uytterhoeven
Convert TXx9 LED description from legacy GPIO numbers to GPIO descriptors using a GPIO lookup table. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17MIPS: TXX9: rbtx4927: Use GPIO lookup table for SIO DTRGeert Uytterhoeven
Convert SIO DTR handling from legacy GPIO calls to GPIO descriptors using a GPIO lookup table. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17MIPS: TXX9: Remove txx9_7segled_*() forward declarationsGeert Uytterhoeven
The actual implementation was removed in commit 5a8df9281b052ff3 ("MIPS: TXX9: Remove rbtx4939 board support"). Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17MIPS: TXX9: Remove tx4938_spi_init() and txx9_spi_init()Geert Uytterhoeven
The last user of tx4938_spi_init() was removed in commit 21d638ef9483d8cf ("MIPS: TXX9: Remove rbtx4938 board support"). Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17MIPS: kernel: proc: Use two seq_putc() calls in show_cpuinfo()Markus Elfring
Single line breaks should occasionally be put into a sequence. Thus use the corresponding function “seq_putc”. The source code was transformed by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-07-17x86/featctl: Stop using 32-bit MSR interfacesJuergen Gross
The 32-bit MSR interfaces rdmsr() and rdmsr_safe() are planned to be removed. Use the related 64-bit variants instead. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Link: https://patch.msgid.link/20260703112426.1763049-1-jgross@suse.com
2026-07-17KVM/x86: Stop using 32-bit MSR interfacesJuergen Gross
The 32-bit MSR interfaces rdmsr(), wrmsr() and rdmsr_safe() are planned to be removed. Use the related 64-bit variants instead. No change in functionality intended. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Kiryl Shutsemau <kas@kernel.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Rick Edgecombe <rick.p.edgecombe@intel.com> Cc: Sean Christopherson <seanjc@google.com> Cc: kvm@vger.kernel.org Link: https://patch.msgid.link/20260629060526.3638272-10-jgross@suse.com
2026-07-17x86/mtrr: Stop using 32-bit MSR interfacesJuergen Gross
The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and wrmsr_safe() are planned to be removed. Use the related 64-bit variants instead. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Link: https://patch.msgid.link/20260703112344.1762985-1-jgross@suse.com
2026-07-17acpi: Stop using 32-bit MSR interfacesJuergen Gross
The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and wrmsr_safe() are planned to be removed. Use the related 64-bit variants instead. In processor_throttling.c drop needless initializers. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Acked-by: Rafael J. Wysocki (Intel) <rafael@kernel.org> Link: https://patch.msgid.link/20260629060526.3638272-5-jgross@suse.com
2026-07-17crypto: qce - Mark QCE as BROKENDemi Marie Obenour
This driver is harmful: - It is much slower than the CPU [1] [2]. - It Has a history of bugs [2] [3]. - It does not have exclusive access to the hardware [4], causing races with the secure world. - It register its implementations with too low a cra_priority for them to be actually used [5]. Therefore, disable it to ensure that nobody builds it into kernels they intend to ship. In the future, the driver will be used for processing restricted media content. However, the kernel does not currently support this. Since the driver will have future uses, allow building it if COMPILE_TEST is enabled. [1]: https://lore.kernel.org/r/20250704070322.20692-1-ebiggers@kernel.org/ [2]: https://lore.kernel.org/r/20250615031807.GA81869@sol/ [3]: https://lore.kernel.org/r/20260706-qce-fix-self-tests-v5-0-86f461ff1829@oss.qualcomm.com/ [4]: https://lore.kernel.org/r/20260629-qcom-qce-cmd-descr-v20-0-56f67da84c05@oss.qualcomm.com/ [5]: https://lore.kernel.org/r/20260524204537.GB110177@quark/ Fixes: ec8f5d8f6f76 ("crypto: qce - Qualcomm crypto engine driver") Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com> Acked-by: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2026-07-17crypto: powerpc/aes - use bool for encryption/decryption flagThorsten Blum
Use bool for the CBC encryption/decryption flag passed through p8_aes_cbc_crypt() to aes_p8_cbc_encrypt(). Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Reviewed-by: Breno Leitao <leitao@debian.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2026-07-16arm64: mm: When logging data aborts only decode Xs when ISV=1Mark Brown
When logging the decode of a data abort we currently unconditionally decode and display Xs. Currently the only defined non-RES0 values for this field are for cases where ISV=1, move the decode of Xs into our existing check for ISV=1. This avoids potential confusion if some other use is assigned to these bits for ISV=0 cases in future, or misleading someone into thinking there is a meaningful value there with currently defined architecture. Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
2026-07-16arm64: dts: add tqma9596la-mba95xxcaMarkus Niebel
This adds support for TQMa95xxLA modules, designed to be soldered on a carrier board. MBa95xxCA is a carrier reference board / starter kit design. There is a common device tree for all variants with e.g. reduced CPU core / feature count. Enable the external accessible PCIe controllers as host, add clocking and reset GPIO. While at it, add hogs for GPIO lines from the M.2 slots until M.2 connector driver is available. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-07-16ARM: replace linux/gpio.h inclusionsArnd Bergmann
linux/gpio.h should no longer be used, convert these instead to either linux/gpio/consumer.h or linux/gpio/legacy.h as needed. Reviewed-by: Linus Walleij <linusw@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Cc: soc@lists.linux.dev Link: https://lore.kernel.org/r/20260710211954.1373336-2-arnd@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-07-16Merge tag 'renesas-fixes-for-v7.2-tag1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes Renesas fixes for v7.2 - Fix lock-ups on the Ironhide development board. * tag 'renesas-fixes-for-v7.2-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: ironhide: Describe inline ECC carveouts Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-07-16arm64: fixmap: Allow 256K early_ioremap() at any offsetYu Peng
NR_FIX_BTMAPS is the per-slot page limit for early_ioremap(). Since __early_ioremap() maps the page-aligned physical range, a 256K request can require one extra page when the physical address is not page-aligned. Reserve one extra page per slot so the 256K mapping budget is usable regardless of the initial page offset. Link: https://lore.kernel.org/r/08fd96fa-ee3a-4904-bd11-bb08bd90436f@kylinos.cn Signed-off-by: Yu Peng <pengyu@kylinos.cn> Signed-off-by: Will Deacon <will@kernel.org>
2026-07-16arm64: syscall: Ensure saved x0 is kept in-sync with tracer updatesWill Deacon
When seccomp support was originally added to arm64 in a1ae65b21941 ("arm64: add seccomp support"), seccomp was erroneously called _before_ the ptrace syscall-enter-stop and therefore the tracer could trivially manipulate the syscall register state after the seccomp check had passed. This was subsequently fixed in a5cd110cb836 ("arm64/ptrace: run seccomp after ptrace") by moving the seccomp check after the tracer has run. Unfortunately, a decade later, that fix has been reported to be incomplete. On arm64, both the first argument to a syscall and its eventual return value are allocated to register x0. In order to facilitate syscall restarting and querying of syscall arguments on the syscall exit path, the original value of x0 is stashed in 'struct pt_regs::orig_x0' early during the syscall entry path and is returned for the first argument by syscall_get_arguments(). Unlike 32-bit Arm, this stashed value is not directly exposed via ptrace() and so changes to register x0 made by the tracer on a syscall-enter-stop are not reflected in 'orig_x0'. This means that seccomp, syscall tracepoints and audit can observe a stale value for the register compared to the argument that will be observed by the actual syscall. Re-sync 'orig_x0' from x0 on the syscall entry path following a potential ptrace stop (i.e. PTRACE_EVENTMSG_SYSCALL_ENTRY or SECCOMP_RET_TRACE). This behaviour is limited to native tasks (because compat tasks expose 'orig_r0' to ptrace) where the syscall is not being skipped (because x0 is updated to hold the return value of -ENOSYS in that case). Cc: Kees Cook <kees@kernel.org> Cc: Jinjie Ruan <ruanjinjie@huawei.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: stable@vger.kernel.org Reported-by: Yiqi Sun <sunyiqixm@gmail.com> Link: https://lore.kernel.org/all/20260529065444.1336608-1-sunyiqixm@gmail.com/ Suggested-by: Catalin Marinas <catalin.marinas@arm.com> Fixes: a5cd110cb836 ("arm64/ptrace: run seccomp after ptrace") Reviewed-by: Jinjie Ruan <ruanjinjie@huawei.com> Tested-by: Jinjie Ruan <ruanjinjie@huawei.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-07-16arm64: dts: am62p5-var-som-symphony: add TPM supportStefano Radaelli
Add the ST33KTPM2XI2C TPM device on the Symphony carrier board. The TPM reset signal is driven through a PCAL6408 GPIO expander, so add the corresponding GPIO expander node. Configure the RGB_SEL board signal through a GPIO hog to keep the board in the expected configuration. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Link: https://patch.msgid.link/d3ac1ce507b48f8debc8857814be00600b5a14f9.1782680023.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: am62p5-var-som-symphony: add touchscreen supportStefano Radaelli
Add support for the capacitive touchscreen on the Symphony carrier board. Describe the FT5x06 touchscreen controller, configure its interrupt, and mark it as a wakeup source. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Link: https://patch.msgid.link/eaf0479114137e4472b4adb3df82a5bcf78405a2.1782680023.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: var-som-am62p: update audio codec configurationStefano Radaelli
Update the WM8904 audio codec configuration on the VAR-SOM-AM62P. Set the audio reference clock rate to 12 MHz and add the codec DRC, GPIO and DMIC configuration required by the board. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Link: https://patch.msgid.link/76e49b33e7810b7cf6452cf827d88b5d0f04ba3b.1782680023.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: var-som-am62p: fix Ethernet PHY configurationStefano Radaelli
Fix the Ethernet device tree description on the VAR-SOM-AM62P. Enable the CPSW Ethernet controller and correct the Ethernet PHY description by modelling the PHY power supply and adding the required board-specific PHY properties. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Link: https://patch.msgid.link/4d1ba0d1b9bd4957224213cf17dca93392788e03.1782680023.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: var-som-am62: Add support for Variscite Symphony BoardStefano Radaelli
Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-AM62 system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart interfaces - OV5640 Camera support - GPIO Expander and TPM - CAN, I2C and general purpose interfaces - Capacitive touch controller Link: https://www.variscite.it/product/single-board-computers/symphony-board/ Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Link: https://patch.msgid.link/42decef4f84db8fc0474675a23e157b68b3b1a1b.1783864932.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: Add support for Variscite VAR-SOM-AM62Stefano Radaelli
Add device tree support for the Variscite VAR-SOM-AM62 system on module. This SOM is designed to be used with various carrier boards. The module includes: - AM62x Sitara MPU processor - Up to 4GB of DDR4-3733 memory - Up to 128GB eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices - Audio codec wm8904 - Resistive touch panel interface controller - I2C, UART and SPI interfaces - Bluetooth 5.2 + WiFi single or dual band Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/ti-sitara-am62x/var-som-am62/ Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Link: https://patch.msgid.link/0a7bdfda80309eaa207b5b369d72f4bcb16e0604.1783864932.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: k3-am69-aquila: Add Toradex OV5640 CSI camerasVitor Soares
Add device tree overlays for the Toradex OV5640 CSI cameras on Aquila CSI_1 and CSI_2. Two variants are supported for each interface: the current CSI Camera Set 5MP OV5640 with a 27 MHz oscillator and the legacy CSI Module 5MP OV5640 with a 24 MHz oscillator. On the Aquila AM69 Development Board, CSI_1 is exposed on connector J70 and CSI_2 is exposed on connector J71. Link: https://developer.toradex.com/hardware/accessories/cameras/csi-camera-module-5mp-ov5640-arducam Link: https://developer.toradex.com/hardware/legacy-products/other/csi-camera-module-5mp-ov5640/ Signed-off-by: Vitor Soares <vitor.soares@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://patch.msgid.link/20260602115123.1324474-16-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: k3-am69-aquila: Add Toradex Capacitive Touch Display 7" DSIVitor Soares
Add a device tree overlay for the Toradex Capacitive Touch Display 7" DSI on the Aquila DSI_1 interface. Used on the Clover Board (J12), where DSI_1 is exposed via a FFC/FPC connector. The display includes an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT70HSLNWCA0 7" WSVGA IPS TFT LCD panel. Touch input is provided by an Ilitek ILI2132 capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi Signed-off-by: Vitor Soares <vitor.soares@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://patch.msgid.link/20260602115123.1324474-15-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: k3-am69-aquila: Add Toradex Capacitive Touch Display 10.1" DSIVitor Soares
Add a device tree overlay for the Toradex Capacitive Touch Display 10.1" DSI on the Aquila DSI_1 interface. Used on the Clover Board (J12), where DSI_1 is exposed via a FFC/FPC connector. The display includes an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT101HVLNWC00 10.1" WXGA IPS TFT LCD panel. Touch input is provided by an Ilitek ILI2132 capacitive touch controller. The overlay is also combined with the Aquila AM69 Clover carrier board device tree to provide a ready-to-use DTB. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi Signed-off-by: Vitor Soares <vitor.soares@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://patch.msgid.link/20260602115123.1324474-14-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: k3-am69-aquila: Add Toradex Capacitive Touch Display 7" DSI ↵Vitor Soares
with adapter Add a device tree overlay for the Toradex Capacitive Touch Display 7" DSI used with the Toradex DSI Display Adapter on the Aquila Development Board. On this board, DSI_1 is exposed on connector J44 through a Samtec LSS-130 connector, and the adapter converts it to an FFC/FPC connector. The display includes an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT70HSLNWCA0 7" WSVGA IPS TFT LCD panel. Touch input is provided by an Ilitek ILI2132 capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter Signed-off-by: Vitor Soares <vitor.soares@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://patch.msgid.link/20260602115123.1324474-13-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: k3-am69-aquila: Add Toradex Capacitive Touch Display 10.1" ↵Vitor Soares
DSI with adapter Add a device tree overlay for the Toradex Capacitive Touch Display 10.1" DSI used with the Toradex DSI Display Adapter on the Aquila Development Board. On this board, DSI_1 is exposed on connector J44 through a Samtec LSS-130 connector, and the adapter converts it to an FFC/FPC connector. The display includes an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT101HVLNWC00 10.1" WXGA IPS TFT LCD panel. Touch input is provided by an Ilitek ILI2132 capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter Signed-off-by: Vitor Soares <vitor.soares@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://patch.msgid.link/20260602115123.1324474-12-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: k3-am69-aquila: Add DSI to LVDS adapter with 10.1" displayVitor Soares
Add a device tree overlay for the Toradex DSI to LVDS Adapter with the Toradex Capacitive Touch Display 10.1" LVDS. Used on Development Board (J44), where DSI_1 is exposed via a Samtec LSS-130 connector. The adapter is based on the Texas Instruments SN65DSI84 DSI-to-LVDS bridge and drives a LogicTechno LT170410-2WHC 10.1" WXGA LVDS panel. Touch input is provided by an Atmel MaxTouch capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds Signed-off-by: Vitor Soares <vitor.soares@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://patch.msgid.link/20260602115123.1324474-11-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: k3-am69-aquila: Add Toradex DSI to HDMI AdapterVitor Soares
Add a device tree overlay for the Toradex DSI to HDMI Adapter on the Aquila AM69 DSI_1 interface. Used on Aquila Development Board (J44), where DSI_1 is exposed via a Samtec LSS-130 connector. The adapter is based on the Lontium LT8912B DSI-to-HDMI bridge. Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-hdmi-adapter Signed-off-by: Vitor Soares <vitor.soares@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://patch.msgid.link/20260602115123.1324474-10-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: k3-am642-tqma64xxl-mbax4xxl: add icssg1 ti,pa-statsAlexander Feilke
Add missing ti,pa-stats syscon phandle. In addition to providing additional ethtool stats, this avoids a "icssg-prueth icssg1-eth: couldn't get ti,pa-stats syscon regmap" error message. Signed-off-by: Alexander Feilke <Alexander.Feilke@ew.tq-group.com> [Nora Schiffer: edited commit description] Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com> Link: https://patch.msgid.link/a03189aa138f74955a03b9fe6018a17bf7e2ce8c.1783348781.git.nora.schiffer@ew.tq-group.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16arm64: dts: ti: k3-am642-tqma64xxl: add ospi0 vcc-supplyAlexander Feilke
Add missing vcc-supply to ospi0 flash. Signed-off-by: Alexander Feilke <Alexander.Feilke@ew.tq-group.com> Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com> Link: https://patch.msgid.link/aaec2ddf7cecb58ca0af37d4f03afec571804757.1783348781.git.nora.schiffer@ew.tq-group.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-07-16KVM: SVM: Bump asid_generation on CPU online to avoid ASID collision after ↵Nikunj A Dadhania
hotplug If a vCPU stays scheduled out (or blocked) while the last pCPU it ran on goes through a hotplug cycle (online->offline->online), and the vCPU then resumes execution on the same pCPU, then it is possible for it to run with an ASID that has now been assigned to a different vCPU, resulting in stale TLB translations being used. svm_enable_virtualization_cpu() resets asid_generation to 1 and sets next_asid to max_asid + 1 on every CPU online event, including hotplug cycles. Because next_asid starts beyond the pool boundary, the first call to new_asid() after an online event always wraps the pool, incrementing asid_generation to 2 and assigning ASIDs starting from min_asid. Consider two vCPUs from different VMs, vCPU-A pinned to CPU-X holding asid_generation=2 and ASID=N from before the hotplug event: 1. CPU-X goes offline and back online: asid_generation resets to 1, next_asid = max_asid + 1. 2. One or more vCPUs migrate to CPU-X and call new_asid(), wrapping the pool and consuming ASIDs starting from min_asid. Eventually vCPU-B from a different VM is assigned asid_generation=2, ASID=N — the same ASID that vCPU-A held before the hotplug. 3. vCPU-A enters pre_svm_run() on CPU-X: current_vmcb->cpu is unchanged so the migration branch is skipped. Its saved asid_generation=2 matches sd->asid_generation=2, so the generation check silently passes and vCPU-A continues running with ASID=N — the same ASID just freshly assigned to vCPU-B. Both vCPUs from different VMs now run on CPU-X with the same ASID, causing them to share NPT TLB entries and producing stale translations. The collision manifests as a KVM internal error (Suberror: 1, emulation failure). The NPT page fault reports a faulting GPA far outside the VM's physical memory range — a sign of stale TLB translations being used. KVM falls back to instruction emulation, which fails on FPU/XSave instructions (XRSTOR, STMXCSR) that the emulator does not implement. Fix this by incrementing asid_generation instead of resetting it to 1 in svm_enable_virtualization_cpu(). On module load, asid_generation starts at 0 (memset) and the increment produces 1, identical to the old behaviour. On subsequent hotplug cycles the generation advances beyond any value a vCPU previously observed on this CPU, so the generation check in pre_svm_run() reliably forces new_asid() on every vCPU after every hotplug cycle. Fixes: 774c47f1d78e ("[PATCH] KVM: cpu hotplug support") Reported-by: Chandrakanth Silveru <Chandrakanth.Silveru@amd.com> Tested-by: Srikanth Aithal <Srikanth.Aithal@amd.com> Reviewed-by: K Prateek Nayak <kprateek.nayak@amd.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Nikunj A Dadhania <nikunj@amd.com> Message-ID: <20260715063506.672432-1-nikunj@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2026-07-16arm64: dts: realtek: Add GPIO support for RTD1625Yu-Chun Lin
Add the GPIO node for the Realtek RTD1625 SoC. Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
2026-07-16arm64: dts: realtek: Add EL2 virtual timer interruptMarc Zyngier
The ARMv8.2 based CPUs used in a number of Realtek SoCs are missing the EL2 virtual timer interrupt. Add it. Furthermore, the "kent" platform appears to assign PPI9 to both the EL2 virtual timer and the GIC Maintenance Interrupt, which can't be right. Attempt a fix by setting the former to PPI12, as PPI9 is traditionally wired to the GIC itself. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
2026-07-15arm64: dts: qcom: eliza-mtp: Enable touchscreenAbel Vesa
The Eliza MTP uses a Goodix GT9916 touchscreen controller connected over SPI. Describe the controller, its power supply, interrupt and reset GPIOs to enable touchscreen support. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260708-dts-qcom-eliza-mtp-enable-ts-v1-1-372020a7a86b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: purwa-iot-som: enable videoWangao Wang
Enable video nodes on the purwa-iot-som board. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260713-enable_iris_on_purwa-v9-2-633d7b87f0c9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: purwa: Override Iris clocks and operating pointsWangao Wang
The Iris block on X1P differs from SM8550/X1E in its clock configuration and requires a dedicated OPP table. The node inherited from the X1E cannot be reused directly, and the fallback compatible "qcom,sm8550-iris" cannot be applied. Override the inherited clocks, clock-names, and operating points, and replaces them with the X1P42100-specific definitions. A new OPP table is provided to support the correct performance levels on this platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260713-enable_iris_on_purwa-v9-1-633d7b87f0c9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sm8450: Add mode-switch property to qmpphyEsteban Urrutia
USB QMP PHY is a possible handler of altmode switching, so add this property. Signed-off-by: Esteban Urrutia <esteuwu@proton.me> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260711-sm8450-qol-dts-v2-2-5eb2e86468c5@proton.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-15arm64: dts: qcom: sm8450: Remove unneeded reserved memory nodesEsteban Urrutia
These nodes are not present on downstream device trees and only take memory away from the AP. No crashes occur without these nodes, so remove them. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Esteban Urrutia <esteuwu@proton.me> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260711-sm8450-qol-dts-v2-1-5eb2e86468c5@proton.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-22 20:38:46 +0000