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2026-06-06riscv: module: Use generic cmp_int() instead of custom cmp_3way()Florian Schmaus
The module-sections.c file defines a custom cmp_3way() macro to perform 3-way comparisons during relocation sorting. Instead of maintaining our own implementation, use the generic cmp_int() macro provided by the already included <linux/sort.h>. This removes redundant code and relies on standard kernel interfaces. Signed-off-by: Florian Schmaus <florian.schmaus@codasip.com> Link: https://patch.msgid.link/20260512063231.708256-1-florian.schmaus@codasip.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06riscv: Fix ftrace_graph_ret_addr() to use the correct task pointerRui Qi
The walk_stackframe() function is used to unwind the stack of a given task. When function graph tracing is enabled, ftrace_graph_ret_addr() is called to resolve the original return address if it was modified by the tracer. The current code incorrectly passes 'current' instead of 'task' to ftrace_graph_ret_addr(). This causes incorrect return address resolution when unwinding a stack of a different task (e.g., when the task is blocked in __switch_to). Fix this by passing 'task' instead of 'current' to match the behavior of other architectures (arm64, loongarch, powerpc, s390, x86). Signed-off-by: Rui Qi <qirui.001@bytedance.com> Link: https://patch.msgid.link/20260408092915.46408-1-qirui.001@bytedance.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06riscv: Implement ARCH_HAS_CC_CAN_LINKThomas Weißschuh
The generic CC_CAN_LINK detection relies on -m32/-m64 compiler flags. These are not supported by riscv compilers. Use architecture-specific logic using -mabi instead. Prefer the 'd' ABI variant when possible as todays toolchains are most likely to provide a libc for that one. Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Link: https://patch.msgid.link/20260316-cc-can-link-riscv-v4-1-64c072b456dd@linutronix.de Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06riscv: propagate insert_resource result from add_resourceThorsten Blum
Currently, add_resource() returns 1 on success, even though its callers only check for negative values. Instead, propagate the insert_resource() result from add_resource() to align with standard kernel return-value conventions (0 on success, negative errno on failure). Use %pR to print the full resource range while at it. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Link: https://patch.msgid.link/20260512172034.328405-4-thorsten.blum@linux.dev Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06riscv: use sysfs_emit in cpu_show_ghostwriteThorsten Blum
Replace sprintf() with sysfs_emit() in cpu_show_ghostwrite(), which is preferred for formatting sysfs output because it provides safer bounds checking. While the current code only emits fixed strings that fit easily within PAGE_SIZE, use sysfs_emit() to follow secure coding best practices. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Link: https://patch.msgid.link/20260510165420.109453-3-thorsten.blum@linux.dev Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06riscv: pi: replace strlcat with strscpy in get_early_cmdlineThorsten Blum
Use the return value of strscpy() instead of calling strlen(fdt_cmdline) again and return early on string truncation. Drop the explicit size argument since early_cmdline has a fixed length, which strscpy() determines using sizeof() when the argument is omitted. Replace strlcat() with strscpy() to append CONFIG_CMDLINE. Also remove the unnecessary fdt_cmdline NULL initialization. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Link: https://patch.msgid.link/20260504154924.141566-3-thorsten.blum@linux.dev Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06riscv: ptdump: Replace unbounded sprintf() in dump_prot()Thorsten Blum
Replace the unbounded sprintf("%s", ...) with the faster and safer strscpy(). Replace all other sprintf() calls with the safer snprintf(). Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Link: https://patch.msgid.link/20260127110543.436242-1-thorsten.blum@linux.dev Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06riscv/purgatory: add asm/purgatory.hThorsten Blum
Add arch/riscv/include/asm/purgatory.h and provide the purgatory() prototype via the architecture header, mirroring the x86 layout. Remove the workaround from arch/riscv/purgatory/purgatory.c. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Link: https://patch.msgid.link/20260509073850.44595-4-thorsten.blum@linux.dev [pjw@kernel.org: drop superfluous extern in header file] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06riscv/purgatory: return bool from verify_sha256_digestThorsten Blum
Change the function's return type from int to bool and return the result of memcmp() directly to simplify the code. While at it, cast ->start to 'const u8 *' to better match the expected type. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Link: https://patch.msgid.link/20260509073850.44595-3-thorsten.blum@linux.dev Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06riscv: cfi: reject unknown flags in PR_SET_CFIRichard Patel
prctl(PR_SET_CFI,PR_CFI_BRANCH_LANDING_PADS) silently ignored unknown control values. Only PR_CFI_{ENABLE,DISABLE,LOCK} should be permitted. This changes the behavior of the uABI (fails previously accepted bits with EINVAL). Fixes: 08ee1559052b ("prctl: cfi: change the branch landing pad prctl()s to be more descriptive") Signed-off-by: Richard Patel <ripatel@wii.dev> Link: https://patch.msgid.link/20260518183918.322545-1-ripatel@wii.dev [pjw@kernel.org: change the patch description to note that although this is a uABI change, it does not break the uABI] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06riscv: Fix fast_unaligned_access_speed_key not getting initializedNam Cao
The static key fast_unaligned_access_speed_key is supposed to be initialized after check_unaligned_access_all_cpus() has been completed. However, check_unaligned_access_all_cpus() has been moved to late_initcall while setting fast_unaligned_access_speed_key still happens at arch_initcall_sync, thus the static key does not get properly initialized. fast_unaligned_access_speed_key can still be initialized in CPU hotplug events, but that cannot be relied on. Move fast_unaligned_access_speed_key's initialization into check_unaligned_access_all_cpus() to fix this issue. This also prevent someone from moving one initcall while forgetting the other in the future. Fixes: 6455c6c11827 ("riscv: Clean up & optimize unaligned scalar access probe") Reported-by: Michael Neuling <mikey@neuling.org> Closes: https://lore.kernel.org/linux-riscv/CAEjGV6y0=bSLp_wrS0uHFj1S2TCRtz4GKzaU5O-L1VV-EL7Nnw@mail.gmail.com/ Signed-off-by: Nam Cao <namcao@linutronix.de> Link: https://patch.msgid.link/20260407120639.4006031-1-namcao@linutronix.de Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06riscv/ptrace: Use USER_REGSET_NOTE_TYPE for REGSET_CFIAndreas Schwab
Fixes a warning while dumping core: [54983.546369][ C7] WARNING: [!note_name] fs/binfmt_elf.c:1771 at elf_core_dump+0x910/0xf68, CPU#7: abort01/31982 Fixes: 2af7c9cf021c ("riscv/ptrace: expose riscv CFI status and state via ptrace and in core files") Signed-off-by: Andreas Schwab <schwab@suse.de> Link: https://patch.msgid.link/87y0hcxuh5.fsf@igel.home Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-06Merge tag 'rust-fixes-7.1-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/ojeda/linux Pull Rust fixes from Miguel Ojeda: "Toolchain and infrastructure: - Fix 'rustc-option' (the Makefile one) when cross-compiling that leads to build or boot failures in certain configs - Work around a Rust compiler bug (already fixed for Rust 1.98.0) thats lead to boot failures in certain configs due to missing 'uwtable' LLVM module flags - Support a Rust compiler change (starting with Rust 1.98.0) in the unstable target specification JSON files - Forbid Rust + arm + KASAN configs, which do not build 'kernel' crate: - Fix NOMMU build by adding a missing helper" * tag 'rust-fixes-7.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ojeda/linux: rust: x86: support Rust >= 1.98.0 target spec rust: arm64: set uwtable llvm module flag for CONFIG_UNWIND_TABLES rust: helpers: add is_vmalloc_addr wrapper for NOMMU builds rust: kasan/kbuild: fix rustc-option when cross-compiling ARM: Do not select HAVE_RUST when KASAN is enabled
2026-06-06vfs: uapi: retire octal and hex numbers in favor of (1 << n) for O_ flagsJori Koolstra
A recent build failure[1] exposed the diffculty of working with the current octal and hex definitions of O_ flags when trying to find a gap for a new flag. This difficulty is compounded by the fact that O_ flags may have architectural specific values. Replace the hex/octal #defines, which are hard to parse when looking for free bits, with explicit bit shifts like (1 << 11). Also, add comments that identify which architectures redefine some of the seemingly free ("cursed") bits in uapi/asm-generic/fcntl.h. These should not be used to define new O_ flags (for now, at least). The translastion was done with Claude Opus 4.8, and verified with a (non-AI) gawk script. The accounting of which architectures claim which bit-gaps in uapi/asm-generic/fcntl.h is also done by hand. [1]: https://lore.kernel.org/all/agruPPybCx8q2XcJ@sirena.org.uk/ Assisted-by: Claude:Opus 4.8 Signed-off-by: Jori Koolstra <jkoolstra@xs4all.nl> Link: https://patch.msgid.link/20260604222405.5382-1-jkoolstra@xs4all.nl Signed-off-by: Christian Brauner (Amutable) <brauner@kernel.org>
2026-06-05kconfig: Remove the architecture specific config for PropellerRong Xu
The CONFIG_PROPELLER_CLANG option currently depends on ARCH_SUPPORTS_PROPELLER_CLANG, but this dependency seems unnecessary. Remove ARCH_SUPPORTS_PROPELLER_CLANG and allow users to control Propeller builds solely through CONFIG_PROPELLER_CLANG. This simplifies the kconfig and avoids potential confusion. Move the .llvm_bb_addr_map sections grouping to include/asm-generic/vmlinux.lds.h. The Propeller documentation has been updated to reflect the most recent tool location and now includes instructions for arm64. Contributor Acknowledgments: * SPE instructions: Daniel Hoekwater <hoekwater@google.com> Signed-off-by: Rong Xu <xur@google.com> Suggested-by: Will Deacon <will@kernel.org> Suggested-by: Nathan Chancellor <nathan@kernel.org> Tested-by: Yabin Cui <yabinc@google.com> Reviewed-by: Kees Cook <kees@kernel.org> Link: https://patch.msgid.link/20260604195612.3757860-3-xur@google.com Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2026-06-05kconfig: Remove the architecture specific config for AutoFDORong Xu
The CONFIG_AUTOFDO_CLANG option currently depends on ARCH_SUPPORTS_AUTOFDO_CLANG, but this dependency seems unnecessary. Remove ARCH_SUPPORTS_AUTOFDO_CLANG and allow users to control AutoFDO builds solely through CONFIG_AUTOFDO_CLANG. This simplifies the kconfig and avoids potential confusion. Expand the AutoFDO documentation to include instructions for arm64. Contributor acknowledgments: * SPE instructions: Daniel Hoekwater <hoekwater@google.com> * ETM instructions: Yabin Cui <yabinc@google.com> Signed-off-by: Rong Xu <xur@google.com> Suggested-by: Will Deacon <will@kernel.org> Tested-by: Yabin Cui <yabinc@google.com> Reviewed-by: Kees Cook <kees@kernel.org> Link: https://patch.msgid.link/20260604195612.3757860-2-xur@google.com Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2026-06-05bpf, riscv: inline bpf_get_current_task() and bpf_get_current_task_btf()Varun R Mallya
On RISC-V, the current task pointer is stored in the thread pointer register (tp). Emit a single `mv a5, tp` instead of a full helper call for BPF_FUNC_get_current_task and BPF_FUNC_get_current_task_btf. Register bpf_jit_inlines_helper_call() entries for both helpers so the verifier treats them as inlined, and add the expected `mv a5, tp` annotation to the riscv64 selftests. The following show changes before and after this patch. Before patch: auipc t1,0x817a # load upper PC-relative address jalr -2004(t1) # call bpf_get_current_task helper mv a5,a0 # move return value to BPF_REG_0 After patch: mv a5,tp # directly: a5 = current (tp = thread pointer) Benchmark (bpf_prog_test_run wrapping bpf_get_current_task in loop, batch=100, 10s, QEMU RISC-V): | runs/sec | helper-calls/sec | ns/call -------------+-----------+------------------+--------- Before patch | 173,490 | 17,349,090 | 57 After patch | 320,497 | 32,049,780 | 31 -------------+-----------+------------------+--------- Improvement | +84.7% | +84.7% | -45.6% Signed-off-by: Varun R Mallya <varunrmallya@gmail.com> Acked-by: Björn Töpel <bjorn@kernel.org> Link: https://lore.kernel.org/r/20260602205847.102825-3-varunrmallya@gmail.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2026-06-05Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
Pull kvm fixes from Paolo Bonzini: "arm64: - Correctly drop the ITS translation cache reference when it actually gets invalidated - Take the SRCU lock for SW page table walks - Restore POR_EL0 access to host EL0, avoiding POR_EL0 becoming inaccessible from EL0 after running a guest - Reassign nested_mmus array behind mmu_lock, ensuring that vcpu init and MMU notifiers are mutually exclusive - Correctly handle FEAT_XNX at stage-2 s390: - More fixes for the new page table management and nested virtualization x86: - More fixes for GHCB issues: - Read start/end indices of page size change requests exactly once per vmexit - Unmap and unpin the GHCB as needed on vCPU free" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (23 commits) KVM: arm64: Correctly identify executable PTEs at stage-2 KVM: arm64: nv: Fix handling of XN[0] when !FEAT_XNX KVM: arm64: Reassign nested_mmus array behind mmu_lock KVM: arm64: Restore POR_EL0 access to host EL0 KVM: arm64: Take the SRCU lock for page table walks in fault injection and AT emulation KVM: arm64: vgic-its: Drop the translation cache reference only for the erased entry KVM: SEV: Unmap and unpin the GHCB as needed on vCPU free KVM: SEV: Decouple the need to sync the GHCB SA from the need to free the SA KVM: SEV: Move sev_free_vcpu() down below sev_es_unmap_ghcb() KVM: Don't WARN if memory is dirtied without a vCPU when the VM is dying KVM: SEV: Read start/end indices of PSC requests exactly once per #VMGEXIT KVM: SEV: Add an anonymous "psc" struct to track current PSC metadata KVM: SEV: Make it more obvious when KVM is writing back the current PSC index KVM: s390: Remove ptep_zap_softleaf_entry() KVM: s390: Fix possible reference leak in fault-in code KVM: s390: Prevent memslots outside the ASCE range KVM: s390: Lock pte when making page secure KVM: s390: Fix fault-in code KVM: s390: vsie: Fix rmap handling in _do_shadow_crste() KVM: s390: Fix guest / virtual address confusion in _essa_clear_cbrl() ...
2026-06-05arm64: defconfig: Enable DP83822 PHY driverStefan Wahren
Enable DP83822 PHY driver as a module to support the Ethernet PHY, which is placed on phyCORE-i.MX93 SOM. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx{91,93}-phyboard-segin: Add peb-av-18 overlaysFlorijan Plohl
Add overlay for the PHYTEC Audio/Video adapter module PEB-AV-18 on phyBOARD-Segin-i.MX91/93 boards. The supported AC220 display is Powertip PH800480T032-ZHC19 panel with a backlight and Ilitek touch-screen controller. Signed-off-by: Florijan Plohl <florijan.plohl@norik.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx93-var-som-symphony: enable ADCStefano Radaelli
Enable ADC1 on the Symphony carrier board and describe its 1.8 V reference supply. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx93-var-som-symphony: enable TPM3 PWMStefano Radaelli
Enable TPM3 on the Symphony carrier board and add the pinctrl states for the PWM output and sleep configuration. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx93-var-som-symphony: keep RGB_SEL lowStefano Radaelli
Keep the RGB_SEL line driven low on the Symphony carrier board. This avoids leaving the line floating and ensures the board remains in the expected display configuration. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx93-var-som-symphony: enable UART7Stefano Radaelli
Enable UART7 on the Symphony carrier board and add its pinctrl configuration. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx93-var-som-symphony: add TPM supportStefano Radaelli
Add the ST33KTPM2XI2C TPM device on the Symphony carrier board. The TPM reset line is driven through a PCAL6408 GPIO expander, so add the expander on the I2C bus and describe the TPM reset GPIO. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx91-var-som-symphony: fix RGB_SEL handlingStefano Radaelli
RGB_SEL is a board-level signal driven by the PCAL6408 GPIO expander on the Symphony carrier board. The signal needs to be driven high on the i.MX91 variant to keep the board in the expected display configuration. Move the handling of this line from a fixed regulator tied to the PCAL6408 supply to a GPIO hog on the correct GPIO expander. Fixes: b3292129dcef ("arm64: dts: imx91-var-som: Add support for Variscite Symphony board") Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: freescale: fsl-ls1028a-tqmls1028a-mbls1028a: switch mmc aliasesNora Schiffer
All modern TQ-Systems boards follow the convention that mmc0 is the eMMC and mmc1 is the SD-card when both interfaces exist, reducing differences between boards for both documentation and U-Boot code (which uses the same Device Trees). Adjust the recently added MBLS1028A Device Tree accordingly. Fixes: 0538ca1f102d ("arm64: dts: ls1028a: Add mbls1028a and mbls1028a-ind devicetrees") Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx943-evk-sdwifi: add a new dtso to support SDIW612 WiFiSherry Sun
Add a new imx943-evk-sdwifi.dtso to support SDIW612 WiFi chip on imx943-evk board, the default imx943-evk.dtb is used to support PCIE AW693 WiFi. Use separate dts for SDIW612 and PCIe AW693 WiFi to avoid the shared regulator between SDIO and PCIe buses, the random probe order between the two buses may break the PCIe initialization sequence which cause AW693 has probability of failing to detect. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx8mp-kontron: Fix GPIO for display power switchFrieder Schrempf
The GPIO that controls the power supply for the LVDS display connector has changed between early prototypes and the current production design of the hardware. Reflect this change in the devicetree to properly switch on the panel supply. This was working before even with the wrong GPIO due to the bidirectional level shifter used on the board which drives the EN signal high even when the input has a (weak) pull down configured as reset condition of the SoC pad. As a result the display was working but the supply was always on. Tested on BL i.MX8MP to show the correct voltage level on the level shifter input. Fixes: 946ab10e3f40 ("arm64: dts: Add support for Kontron OSM-S i.MX8MP SoM and BL carrier board") Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: freescale: imx95-aquila: Add Clover carrier boardAntoine Gouby
Add support for the Aquila i.MX95 SoM mated with the Clover carrier board. Clover is a low-cost carrier board for the Aquila family featuring a small form factor (Nano-ITX 120mm x 120mm) and built for volume production. Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/clover Signed-off-by: Antoine Gouby <antoine.gouby@toradex.com> Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: freescale: add Aquila iMX95 supportJoão Paulo Gonçalves
Add support for the Toradex Aquila iMX95 and its development carrier board. The module consists of an NXP i.MX95 family SoC, up to 16GB LPDDR5 RAM, up to 128GB of storage, a USB 3.2 OTG and USB 2.0 Host, a Gigabit Ethernet PHY, a 10 Gigabit Ethernet interface, an I2C EEPROM and Temperature Sensor, an RX8130 RTC, one Quad lane CSI interface, one Quad lane DSI or CSI interface, one LVDS interface (one or two channels), and some optional addons: DisplayPort (through a DSI-DP bridge), TPM 2.0, and a WiFi/BT module. Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com> Co-developed-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Co-developed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Co-developed-by: Antoine Gouby <antoine.gouby@toradex.com> Signed-off-by: Antoine Gouby <antoine.gouby@toradex.com> Co-developed-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com> Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com> Co-developed-by: Franz Schnyder <franz.schnyder@toradex.com> Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: tqma8mpql-mba8mpxl: configure sai clock in audio codec as wellAlexander Stein
With deferrable card binding the sound card driver tries to get the mclk configuration before it is setup in sai3 node. Fix this by setting the sai clock config for the audio codec as well. Fixes: d8f9d8126582 ("arm64: dts: imx8mp: Add analog audio output on i.MX8MP TQMa8MPxL/MBa8MPxL") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: freescale: add i.MX95 19x19 FRDM PRO board dtsJoseph Guo
NXP i.MX95 19x19 FRDM PRO is cost-effective with extensive expansion capabilities based on the i.MX95 19x19 SoC. It is designed for AI and robotic situation. Difference with i.MX95 15x15 FRDM: - Use i.MX95 19x19 package - Support 2 KEY-M M.2 PCIE - 10G ETH interface - Secure Element interface Add device tree for this board. Including: - LPUART1 and LPUART5 - NETC - USB - 2 M-Key M.2 PCIe - uSDHC1, uSDHC2 and uSDHC3 - FlexCAN1 and FlexCAN3 (CAN1 is reserved by M7) - LPI2C3, LPI2C4 and their child nodes - Watchdog3 - SAI, MQS, MICFIL Signed-off-by: Joseph Guo <qijian.guo@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: s32g: add PWM support for s32g2 and s32g3Khristine Andreea Barbulescu
Add PWM0 and PWM1 for S32G2 and S32G3 SoCs Reviewed-by: Enric Balletbo i Serra <eballetb@redhat.com> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: s32g3: Fix SWT8 watchdog addressKrzysztof Kozlowski
Add missing hex annotation to fix the SWT8 watchdog address in 'reg' property, as reported by dtc W=1: s32g3.dtsi:863.27-869.5: Warning (simple_bus_reg): /soc@0/watchdog@40500000: simple-bus unit address format error, expected "269fb20" Lack of hex '0x' meant address would be interpreted as decimal thus completely different value used as this device MMIO. If device was enabled this could lead to corruption of other device address space and broken boot. Cc: stable@vger.kernel.org Fixes: 6db84f042745 ("arm64: dts: s32g3: Add the Software Timer Watchdog (SWT) nodes") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Daniel Lezcano <daniel.lezcano@oss.qualcomm.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx95-var-dart-sonata: add CAN controllerStefano Radaelli
Add the MCP251xFD CAN controller connected to LPSPI7 chip select 1 on the Sonata carrier board. Add the second SPI chip select GPIO and describe the CAN interrupt and pinctrl configuration. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx95-var-dart-sonata: add TPM reset GPIOStefano Radaelli
Add the reset GPIO for the TPM device on the Sonata carrier board and label the node accordingly. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoardJosua Mayer
Add support for the SolidRun i.MX8DXL System-on-Module (revision 2.1) and its corresponding evaluation carrier board, the HummingBoard Telematics (revision 2.0). The SoM features: - eMMC - GNSS with 1PPS - V2X DSRC Radio - Secure Element for V2X Applications - Inertial Sensor - Pressure Sensor - Compass The HummingBoard Telematics carrier board features: - Cellular Modem - WiFi & Bluetooth - RTC with backup battery - CAN - 100Base-TX Ethernet - 100Base-T1 Ethernet - Multi-interface I/O connector - Multi-interface add-on board connector The multi-interface I/O connector supplies power and provides basic I/O (Console UART, 100Base-TX, 100Base-T1, CAN, and power-supply logic level GPIOs). The SolidRun Evaluation Kit includes a suitable cable and adapter board that breaks these out into RJ45, USB Type-A, microUSB Console, and Terminal Block connectors. The multi-interface add-on board connector provides additional interfaces (5x 100Base-T1, 2x SGMII, USB 2.0 shared with the cellular modem, CAN, MDIO, SPI, UART, PCIe, I2C, and GPIO). These add-on interfaces are disabled by default in the base device tree and are intended to be enabled and extended via device tree overlays. Note that a few components physically present on the SoM were omitted from this description due to a lack of upstream bindings and drivers: - Pressure Sensor - V2X DSRC Radio - Secure Element Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: Add support for LX2160 Twins board in single configurationJosua Mayer
Add support for the SolidRun LX2160A Twins board in its single cpu configuration. The twins board is designed to host a pair of LX2160A CEX-7 modules, sharing a single PCI-E connector in multi-host mode. It may be assembled in two configurations (different assembly options facilitating signal re-routing), with a single or with dual CEX-7 module. Their marketing names are: - SolidWAN Single LX2160 - SolidWAN Dual LX2160 Add the single configuration, featuring: - 8x SFP (1Gbps) - 8x SFP+ (1/10Gbps) - PCI-E OCP card connector - USB-3.0 front-panel header with single port - microSD - dual hot-swappable power supplies Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: lx2160a-cex7: add usb hubJosua Mayer
LX2160A CEX-7 module provides a total of 4 USB ports to the carrier board, one from first usb controller, and 3 from a hub behind the second controller. Both controllers currently have their status set okay in the module's dtsi file. However devices should be disabled by default when incomplete. The first USB controller is only completed by a carrier board featuring a device or USB connector. The second controller hosts a USB hub and should therefore be active. Add description for the USB hub, and enable the first controller only in the carrier board description. Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: lx2160a-clearfog-itx: move shared includes to dtsJosua Mayer
Originally includes were defined hierarchically: - CEX-7 Module includes SoC - Clearfog-CX & Honeycomb common parts include CEX-7 Module - Boards include common parts This makes it difficult to modify the includes on a per-board level, e.g. when adding a new board based on CEX-7 module but revision 2 SoC (which now has its own soc dtsi). Move includes of both SoC and CEX-7 module out of common parts and into each board dts. Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: lx2160a-clearfog-itx: remove redundant dts version tagJosua Mayer
The dts version tag should only appear in the top level dts file. Since the cex-7 module and clearfog-itx are shared code intended for inclusion, drop their dts version tags. Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: lx2162a-clearfog: specify sfp ports led colour and functionJosua Mayer
The LX2162A Clearfog board has a green LED on each of four SFP ports. Describe in device-tree that their colour is green and function "lan". Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: lx2162a-clearfog: cleanup superfluous status propertiesJosua Mayer
The SoC dtsi has always enabled serdes block 1, enabled dpmac and disabled pcie nodes. Drop the superfluous status properties on these nodes. Further drop crypto alias as SoM dtsi already set it. Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: lx2162a-clearfog: use rev2 SoC dtsiJosua Mayer
LX2160A and LX2162A are different packages of the same silicon. While LX2160A had two revisions, LX2162A was released later based on LX2160A revision 2. Commit a8fe6c8dfc40 ("arm64: dts: fsl-lx2160a: add rev2 support") has added a new soc dtsi for revision 2. Update LX2162A Clearfog description to use revision 2 dtsi. Fixes: 5093b190f9ce ("arm64: dts: freescale: Add support for LX2162 SoM & Clearfog Board") # no-stable Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: lx2160a-rev2: extend 32-bit and add 64-bit pci regionsJosua Mayer
LX2160 SoC PCIe controller supports 64-bit memory regions up to 16GB, 32-bit regions up to 3GB and 16-bit regions up to 64k. For each PCIe controller: - extend the existing 32-bit regions to 3GB size - add 64-bit region See [1] and [2] for boot messages showing ranges before and after. On LX2160A Silicon revision 1, the pcie driver fails to program atu for ranges larger than 4GB [3]. Therefore changes are limited to revision 2. Similar memory allocation with similar flags was tested with UEFI and ACPI on pcie3 and pcie5, on a variety of nxp vendor fork versions. Fixes allocation of large, and 64-bit BARs as requested by many PCI cards especially graphics processors or AI accelerators, e.g.: [ 2.941187] pci 0000:01:00.0: BAR 0: no space for [mem size 0x200000000 64bit pref] [ 2.948834] pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x200000000 64bit pref] [1] example of new allocations (pcie5): [ 1.182745] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges: [ 1.182760] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000 [ 1.182771] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000 [ 1.182778] layerscape-pcie 3800000.pcie: IO 0xa000010000..0xa00001ffff -> 0x0000000000 [ 1.183642] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G [ 1.385429] layerscape-pcie 3800000.pcie: PCIe Gen.3 x8 link up [ 1.385481] layerscape-pcie 3800000.pcie: PCI host bridge to bus 0001:00 [ 1.385484] pci_bus 0001:00: root bus resource [bus 00-ff] [ 1.385488] pci_bus 0001:00: root bus resource [mem 0xa400000000-0xa7ffffffff pref] [ 1.385491] pci_bus 0001:00: root bus resource [mem 0xa040000000-0xa0ffffffff] (bus address [0x40000000-0xffffffff]) [ 1.385494] pci_bus 0001:00: root bus resource [io 0x10000-0x1ffff] (bus address [0x0000-0xffff]) [ 1.385516] pci 0001:00:00.0: [1957:8d80] type 01 class 0x060400 PCIe Root Port [ 1.385538] pci 0001:00:00.0: PCI bridge to [bus 01-ff] [ 1.385544] pci 0001:00:00.0: bridge window [io 0x11000-0x11fff] [ 1.385548] pci 0001:00:00.0: bridge window [mem 0xa040000000-0xa0502fffff] [ 1.385605] pci 0001:00:00.0: supports D1 D2 [ 1.385607] pci 0001:00:00.0: PME# supported from D0 D1 D2 D3hot [ 1.386778] pci 0001:01:00.0: [1002:6995] type 00 class 0x030000 PCIe Legacy Endpoint [ 1.387336] pci 0001:01:00.0: BAR 0 [mem 0xa040000000-0xa04fffffff 64bit pref] [ 1.387368] pci 0001:01:00.0: BAR 2 [mem 0xa050000000-0xa0501fffff 64bit pref] [ 1.387385] pci 0001:01:00.0: BAR 4 [io 0x11000-0x110ff] [ 1.387402] pci 0001:01:00.0: BAR 5 [mem 0xa050200000-0xa05023ffff] [ 1.387418] pci 0001:01:00.0: ROM [mem 0xa050240000-0xa05025ffff pref] [ 1.387493] pci 0001:01:00.0: enabling Extended Tags [ 1.388960] pci 0001:01:00.0: supports D1 D2 [2] example of previous allocations (pcie5): [ 1.716744] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges: [ 1.724060] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa07fffffff -> 0x0040000000 [ 1.733277] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G [ 1.836220] layerscape-pcie 3800000.pcie: PCIe Gen.3 x8 link up [ 1.842186] layerscape-pcie 3800000.pcie: PCI host bridge to bus 0001:00 [ 1.848883] pci_bus 0001:00: root bus resource [bus 00-ff] [ 1.854363] pci_bus 0001:00: root bus resource [mem 0xa040000000-0xa07fffffff] (bus address [0x40000000-0x7fffffff]) [ 1.864892] pci 0001:00:00.0: [1957:8d80] type 01 class 0x060400 PCIe Root Port [ 1.872216] pci 0001:00:00.0: PCI bridge to [bus 01-ff] [ 1.877438] pci 0001:00:00.0: bridge window [io 0x1000-0x1fff] [ 1.883526] pci 0001:00:00.0: bridge window [mem 0xa040000000-0xa0502fffff] [3] error programming atu beyond 4GB: [ 1.716762] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges: [ 1.724080] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000 [ 1.732615] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000 [ 1.741142] layerscape-pcie 3800000.pcie: IO 0xa010000000..0xa01000ffff -> 0x0000000000 [ 1.750379] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G [ 1.759089] layerscape-pcie 3800000.pcie: Failed to set MEM range [mem 0xa400000000-0xa7ffffffff flags 0x2200] [ 1.769089] layerscape-pcie 3800000.pcie: probe with driver layerscape-pcie failed with error -22 [4] pci bootloaderp atching related errors with IORESOURCE_MEM_64 flag: [ 0.967809] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges: [ 0.967830] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000 [ 0.967842] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000 [ 0.967849] layerscape-pcie 3800000.pcie: IO 0xa000010000..0xa00001ffff -> 0x0000000000 [ 1.169315] pci 0000:01:00.0: [8086:1572] type 00 class 0x020000 PCIe Endpoint [ 1.169733] pci 0000:01:00.0: BAR 0 [mem 0x00000000-0x00ffffff 64bit pref] [ 1.169771] pci 0000:01:00.0: BAR 3 [mem 0x00000000-0x00007fff 64bit pref] [ 1.169796] pci 0000:01:00.0: ROM [mem 0x00000000-0x0007ffff pref] [ 1.173389] OF: /soc/pcie@3800000: no msi-map translation for id 0x100 on (null) [ 1.173515] OF: /soc/pcie@3800000: no iommu-map translation for id 0x100 on (null) Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx95: Correct PCIe outbound address space configurationRichard Zhu
Fix the PCIe outbound memory ranges for both pcie0 and pcie1 controllers on i.MX95. The memory window size was incorrectly set to 256MB during initial bring-up, but the hardware supports up to 4GB of outbound address space per controller. Additionally, the ECAM region cannot be mapped as I/O space. Use a memory-mapped region for I/O space instead, and relocate the 1MB I/O region to immediately follow the memory region at offset 0xf0000000 within each window. Update the outbound address space layout per controller as follows: - 3.5GB 64-bit prefetchable memory - 256MB 32-bit non-prefetchable memory - 1MB I/O Fixes: 3b1d5deb29ff ("arm64: dts: imx95: add pcie[0,1] and pcie-ep[0,1] support") Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx91-9x9-qsb: add reset gpios for ethernet PHYsJoy Zou
The PHYs of the EQOS interface is supported to be reset by I2C GPIO expander. So add the support to reset PHYs. Signed-off-by: Joy Zou <joy.zou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx91-11x11-evk: add reset gpios for ethernet PHYsJoy Zou
Both the PHYs of the EQOS interface and the FEC interface are supported to be reset by I2C GPIO expander. So add the support to reset PHYs. Signed-off-by: Joy Zou <joy.zou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx91-11x11-evk: add pinctrl for wdog3 resetJoy Zou
The wdog3 node enables fsl,ext-reset-output to assert an external reset signal upon watchdog timeout, but lacks pinctrl configuration for the physical pad. Without proper pinctrl settings, which could cause the watchdog timeout to fail to reset the board hardware. Add pinctrl configuration to ensure the pin is properly muxed and configured for external watchdog reset functionality. Signed-off-by: Joy Zou <joy.zou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-19 17:35:45 +0000