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2026-06-05arm64: dts: imx91-9x9-qsb: add pinctrl for wdog3 resetJoy Zou
The wdog3 node enables fsl,ext-reset-output to assert an external reset signal upon watchdog timeout, but lacks pinctrl configuration for the physical pad. Without proper pinctrl settings, which could cause the watchdog timeout to fail to reset the board hardware. Add pinctrl configuration to ensure the pin is properly muxed and configured for external watchdog reset functionality. Signed-off-by: Joy Zou <joy.zou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx91-9x9-qsb: remove unused property clock-frequency from mdio nodeJoy Zou
The clock-frequency property is not implemented. Remove it to clean up the device tree. Signed-off-by: Joy Zou <joy.zou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: freescale: add bootph-all to watchdog nodes for i.MX platformsAlice Guo
Add the bootph-all property to ULP watchdog nodes across multiple i.MX SoC device trees, ensuring the watchdog is available during all boot phases. The affected watchdog nodes are: - imx8ulp: wdog3 - imx91/93: wdog3, wdog4, wdog5 - imx94: wdog3 - imx95: wdog3 - imx952: wdog3 Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx94: fix DDR PMU interrupt numberAlice Guo
The DDR Performance Monitor node was added with incorrect interrupt number 91, which actually belongs to the wdog4 watchdog. Fix it to the correct interrupt number 374. Fixes: e918e5f847b3 ("arm64: dts: imx94: add DDR Perf Monitor node") Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Xu Yang <xu.yang_2@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3Khristine Andreea Barbulescu
Add ADC0 and ADC1 for S32G2 and S32G3 SoCs. Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> Reviewed-by: Enric Balletbo i Serra <eballetb@redhat.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx943-evk: Fix PCIe EP vpcie-supplySherry Sun
The vpcie-supply property should reference the regulator that controls the actual M.2 power supply, not the W_DISABLE1# signal. On imx943-evk: - reg_m2_wlan controls M.2 W_DISABLE1# signal - reg_m2_pwr controls the actual M.2 power supply Fix the vpcie-supply to use reg_m2_pwr for proper power control in PCIe endpoint mode. Fixes: 1962c596d51c ("arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support") Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: s32g: add PIT support for s32g2 and s32g3Khristine Andreea Barbulescu
Add PIT0 and PIT1 for S32G2 and S32G3 SoCs Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> Reviewed-by: Enric Balletbo i Serra <eballetb@redhat.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx8mp-kontron: Reduce EERAM SPI clock frequencyFrieder Schrempf
There is an onboard level shifter for the SPI signals that causes additional propagation delay and renders the SPI transmission unreliable at 20 MHz. Reduce the clock frequency to a safe value. Fixes: 946ab10e3f40 ("arm64: dts: Add support for Kontron OSM-S i.MX8MP SoM and BL carrier board") Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx95: Add Root Port node and PERST propertySherry Sun
Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx8dxl/qm/qxp: Add Root Port node and PERST propertySherry Sun
Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx8mq: Add Root Port node and PERST propertySherry Sun
Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx8mp: Add Root Port node and PERST propertySherry Sun
Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx8mm: Add Root Port node and PERST propertySherry Sun
Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05arm64: dts: imx8mp: Add DT overlays for DH i.MX8M Plus DHCOM SoM and boardsMarek Vasut
Add DT overlays to support DH i.MX8M Plus DHCOM SoM variants and carrier board expansion modules. The following DT overlays are implemented: - SoM: - DH 660-x00 SoM with 1xRMII PHY - DH 660-x00 SoM with 2xRMII PHY - PDK2: - DH 505-200 Display board in edge connector X12 via direct LVDS - DH 531-100 SPI/I2C board in header X21 - DH 531-200 SPI/I2C board in header X22 - DH 560-200 Display board in edge connector X12 - PDK3: - DH 505-200 Display board in edge connector X36 via direct LVDS - DH 531-100 SPI/I2C board in header X40 - DH 531-200 SPI/I2C board in header X41 - DH 560-300 Display board in edge connector X36 - EA muRata 2AE M.2 A/E-Key card in connector X20 - NXP SPF-29853-C1 MINISASTOCSI with OV5640 sensor in connector X31 - NXP SPF-29853-C1 MINISASTOCSI with OV5640 sensor in connector X29 - PicoITX: - DH 626-100 Display board in edge connector X2 Signed-off-by: Marek Vasut <marex@nabladev.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-06-05Merge tag 'kvmarm-fixes-7.1-5' of ↵Paolo Bonzini
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 fixes for 7.1, take #5 - Correctly drop the ITS translation cache reference when it actually gets invalidated - Take the SRCU lock for SW page table walks - Restore POR_EL0 access to host EL0, avoiding POR_EL0 becoming inaccessible from EL0 after running a guest - Reassign nested_mmus array behind mmu_lock, ensuring that vcpu init and MMU notifiers are mutually exclusive - Correctly handle FEAT_XNX at stage-2
2026-06-05KVM: RISC-V: SBI FWFT: Fix stale feature exposure after runtime extension ↵Yong-Xuan Wang
changes Fix a bug where FWFT features could be incorrectly exposed to guests after userspace disables their dependent ISA extensions at runtime. The 'supported' field in kvm_sbi_fwft_config was set once during vCPU initialization based on the initial hardware/extension availability. However, when userspace subsequently disables ISA extensions via the KVM ONE_REG interface, the 'supported' field was not updated. This caused the following issues: 1. FWFT features would remain visible and accessible to guests even after their prerequisite ISA extensions were disabled 2. Guests could configure FWFT features that depend on disabled extensions, leading to undefined behavior 3. The static 'supported' flag and the dynamic supported() callback could disagree about feature availability The fix introduces a two-layer checking mechanism: 1. Add an optional init() callback to the kvm_sbi_fwft_feature structure for features that require hardware probing during initialization. This separates the one-time hardware detection logic from the runtime availability check. 2. Add runtime checks in all FWFT-related functions that call feature->supported(vcpu) if the callback exists. This ensures feature availability is re-evaluated based on the current ISA extension state. This approach maintains the cached 'supported' field for initialization- time decisions while ensuring runtime availability is always determined by the current vCPU configuration, not initialization-time snapshots. Fixes: 6b72fd170592 ("RISC-V: KVM: add support for FWFT SBI extension") Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260601-kvm-get_reg_list-v2-v5-3-415d08a2813b@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-05KVM: RISC-V: SBI FWFT: Add optional init() callback for hardware probingYong-Xuan Wang
Add an optional init() callback to separate one-time hardware probing from runtime availability checks. For pointer masking, this allows probing supported PMM lengths during initialization while checking ISA extension availability at runtime. Fix try_to_set_pmm() to restore the previous HENVCFG.PMM value after probing, preventing side effects from hardware detection. Add preemption protection to ensure CSR probe sequences complete atomically on the same CPU. Fixes: 6f576fc0aeb9 ("RISC-V: KVM: Add support for SBI_FWFT_POINTER_MASKING_PMLEN") Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260601-kvm-get_reg_list-v2-v5-2-415d08a2813b@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-05KVM: RISC-V: SBI FWFT: Mark vCPU CSRs dirty after setting feature valueYong-Xuan Wang
Mark the vCPU CSRs as dirty after successfully setting an FWFT feature value. FWFT features may modify CSRs (e.g., pointer masking modifies henvcfg.PMM), and failing to mark them dirty can lead to the guest observing stale CSR state after vCPU scheduling or migration. Fixes: 1323a5cfe52c ("KVM: riscv: Skip CSR restore if VCPU is reloaded on the same core") Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260601-kvm-get_reg_list-v2-v5-1-415d08a2813b@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-05bpf: Replace scratch PTE atomically when allocating arena pagesTejun Heo
apply_range_set_cb() maps the pages for a new arena allocation and returned -EBUSY when the target PTE was already populated. Kernel-fault recovery leaves the per-arena scratch page in unallocated arena PTEs, so a later bpf_arena_alloc_pages() over such a page hits that -EBUSY, and every subsequent allocation of it fails the same way. Allocation must install the real page over scratch instead. Overwriting the scratch PTE in place is a valid->valid change, which arm64 forbids without break-before-make. Route through an invalid entry instead: ptep_try_set() fills only a none slot, so the PTE goes scratch->none->page. On finding scratch, clear it and flush_tlb_before_set() before retrying. The new flush_tlb_before_set() is a no-op except on arches like arm64 that need the break-before-make TLB invalidate. The loop also copes with a concurrent fault re-scratching the slot. Arches without ptep_try_set() never install the scratch page, so keep the must-be-empty check and set_pte_at() for them. Fixes: dc11a4dba246 ("bpf: Recover arena kernel faults with scratch page") Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Alexei Starovoitov <ast@kernel.org> Cc: David Hildenbrand <david@kernel.org> Acked-by: Kumar Kartikeya Dwivedi <memxor@gmail.com> Link: https://lore.kernel.org/r/20260601183728.1800490-1-tj@kernel.org Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2026-06-05RISC-V: KVM: Enhance the logging check for mmu mappingInochi Amaoto
When enabling dirty ring, the dirty bitmap is disable, and the logging check is always false as the RISC-V architecture does not select "NEED_KVM_DIRTY_RING_WITH_BITMAP". Although the dirty log is recorded since the write path already trying to add the dirty log, the logic for logging check is broken and some side effect will occurs. Enhance the logging check for mmu mapping so it can check both the dirty ring and the dirty bitmap. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260528113840.2629186-1-inochiama@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-05x86/cpu: Remove obsolete aperfmperf_get_khz() declarationJunxiao Chang
aperfmperf_get_khz() was replaced by arch_freq_get_on_cpu(). The remaining declaration in the header file is no longer used and should be removed. Fixes: f3eca381bd49 ("x86/aperfmperf: Replace arch_freq_get_on_cpu()") Signed-off-by: Junxiao Chang <junxiao.chang@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Nikolay Borisov <nik.borisov@suse.com> Link: https://patch.msgid.link/20260606021514.1433619-1-junxiao.chang@intel.com
2026-06-05KVM: arm64: Correctly identify executable PTEs at stage-2Oliver Upton
KVM invalidates the I-cache before installing an executable PTE on implementations without DIC. Unfortunately, support for FEAT_XNX broke this check as KVM_PTE_LEAF_ATTR_HI_S2_XN was expanded to a bitfield. Fix it by reusing kvm_pgtable_stage2_pte_prot() and testing the abstract permission bits instead. Fixes: 2608563b466b ("KVM: arm64: Add support for FEAT_XNX stage-2 permissions") Reported-by: Sashiko (gemini/gemini-3.1-pro-preview) Signed-off-by: Oliver Upton <oupton@kernel.org> Reviewed-by: Wei-Lin Chang <weilin.chang@arm.com> Link: https://patch.msgid.link/20260602165901.52800-3-oupton@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org
2026-06-05KVM: arm64: nv: Fix handling of XN[0] when !FEAT_XNXOliver Upton
XN has already been extracted from its bitfield position so using FIELD_PREP() on the mask that clears XN[0] is completely broken, having the effect of unconditionally granting execute permissions... Fix the obvious mistake by manipulating the right bit. Cc: stable@vger.kernel.org Fixes: d93febe2ed2e ("KVM: arm64: nv: Forward FEAT_XNX permissions to the shadow stage-2") Reviewed-by: Wei-Lin Chang <weilin.chang@arm.com> Signed-off-by: Oliver Upton <oupton@kernel.org> Link: https://patch.msgid.link/20260602165901.52800-2-oupton@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-06-05x86/kvmclock: Implement read_snapshot() for kvmclock clocksourceDavid Woodhouse
Implement the read_snapshot() callback for the kvmclock clocksource. This returns the kvmclock nanosecond value (for timekeeping) while also providing the raw TSC value that was used to compute it. The TSC is read inside the pvclock seqlock-protected region, ensuring the raw TSC and derived kvmclock value are atomically paired. This enables ktime_get_snapshot_id() to provide the raw TSC to consumers like the vmclock PTP driver, which currently has to do a separate call to get_cycles() to obtain a value at *approximately* the same time, to feed through the vmclock calculation. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Assisted-by: Kiro:claude-opus-4.6-1m Link: https://patch.msgid.link/20260604095755.64849-3-dwmw2@infradead.org
2026-06-05crypto: powerpc/aes - use min in ppc_{ecb,cbc,ctr,xts}_cryptThorsten Blum
Replace min_t() with the simpler min() macro since the values are unsigned and compatible. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2026-06-05arm64: arch_timer: reuse arch_timer_read_cnt{p,v}ct_el0() helpersBreno Leitao
__arch_counter_get_cntpct() and __arch_counter_get_cntvct() open-code the same ECV-aware ALTERNATIVE block that arch_timer_read_cntpct_el0() and arch_timer_read_cntvct_el0() already provide in the same header. The two pairs are byte-for-byte identical except for the trailing arch_counter_enforce_ordering() the __arch_counter_get_* variants add. Replace the duplicated inline assembly in __arch_counter_get_cntpct() and __arch_counter_get_cntvct() with calls to the corresponding helpers. This mirrors commit 00b39d150986 ("arm64: vdso: Use __arch_counter_get_cntvct()"), which removed similar duplication from the vDSO, and keeps the system-counter read sequence in a single place, reducing assembly code in the kernell No functional change: the resulting inline assembly, alternatives, and clobbers are unchanged; only the source-level expression of the read moves into the existing helper. Verified by rebuilding the consumers of these helpers before and after the change and comparing the resulting disassembly: - arch/arm64/kernel/vdso/vdso.so (final linked vDSO): bit-identical (same sha256 across rebuilds) - arch/arm64/kernel/vdso/vgettimeofday.o: identical disassembly - arch/arm64/lib/delay.o: identical disassembly - drivers/clocksource/arm_arch_timer.o: same 50 functions with byte-identical instruction streams; only difference is function ordering inside .text and NOP padding, with no opcodes added or removed. Signed-off-by: Breno Leitao <leitao@debian.org> Signed-off-by: Will Deacon <will@kernel.org>
2026-06-05KVM: arm64: Reassign nested_mmus array behind mmu_lockHyunwoo Kim
kvm->arch.nested_mmus[] is walked under kvm->mmu_lock, including from the MMU notifier path (kvm_unmap_gfn_range() -> kvm_nested_s2_unmap()), which can run at any time. kvm_vcpu_init_nested() reallocates the array and frees the old buffer while holding only kvm->arch.config_lock, so such a walker can reference the freed array. Allocate the new array outside of mmu_lock, as the allocation can sleep. Under the lock, copy the existing entries, fix up the back pointers and reassign the array. Free the old buffer after dropping the lock, as kvfree() can sleep as well. Fixes: 4f128f8e1aaac ("KVM: arm64: nv: Support multiple nested Stage-2 mmu structures") Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com> Reviewed-by: Oliver Upton <oupton@kernel.org> Link: https://patch.msgid.link/aiKIVVeIr1aAB1yp@v4bel Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger,kernel.org
2026-06-05KVM: arm64: Restore POR_EL0 access to host EL0Joey Gouly
CPTR_EL2.E0POE was being cleared in __deactivate_cptr_traps_vhe(), which meant that any accesses to POR_EL0 from host EL0 would trap and be reported to userspace as an Illegal instruction. This would happen after running any VM, regardless if it used POE or not. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Link: https://sashiko.dev/#/patchset/20260602155430.2088142-1-maz@kernel.org?part=1 Link: https://patch.msgid.link/20260604105434.2297268-1-joey.gouly@arm.com Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger,kernel.org
2026-06-05arm64/mm: Rename ptdesc_tAnshuman Khandual
ptdesc_t sounds very similar to the core MM struct ptdesc which is actually the memory descriptor for page table allocations. Hence rename this typedef element as ptval_t instead for better clarity and separation. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: David Hildenbrand <david@kernel.org> Cc: Mike Rapoport <rppt@kernel.org> Cc: linux-efi@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Acked-by: Mike Rapoport (Microsoft) <rppt@kernel.org> Acked-by: David Hildenbrand (Arm) <david@kernel.org> Suggested-by: David Hildenbrand (Arm) <david@kernel.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-06-05arm64: mm: Defer remap of linear alias of data/bssArd Biesheuvel
Marking the linear alias of data/bss invalid involves calling set_memory_valid(), which calls split_kernel_leaf_mapping() under the hood. On BBML2_NOABORT capable systems, this may result in the need to allocate page tables at a time when the generic memory allocation APIs are not yet available, resulting in a splat like WARNING: arch/arm64/mm/mmu.c:821 at split_kernel_leaf_mapping+0x15c/0x170, CPU#0: swapper/0 Modules linked in: CPU: 0 UID: 0 PID: 0 Comm: swapper Not tainted 7.1.0-rc6 #1 PREEMPT(undef) pstate: a04000c9 (NzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : split_kernel_leaf_mapping+0x15c/0x170 lr : update_range_prot+0x40/0x128 sp : ffffc99ad3863c80 ... Call trace: split_kernel_leaf_mapping+0x15c/0x170 (P) update_range_prot+0x40/0x128 set_memory_valid+0x94/0xe0 mark_linear_data_alias_valid+0x54/0x68 map_mem+0x1fc/0x240 paging_init+0x48/0x210 setup_arch+0x274/0x338 start_kernel+0x98/0x538 __primary_switched+0x88/0x98 as reported by CKI automated testing. So defer the boot-time call to mark_linear_data_alias_valid() to a later time when page allocations can be made normally. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
2026-06-05KVM: arm64: Omit tag sync on stage-2 mappings of the zero pageArd Biesheuvel
Commit f620d66af316 ("arm64: mte: Do not flag the zero page as PG_mte_tagged") removed the PG_mte_tagged flag from the zero page, but missed a KVM code path that may set this flag on the zero page when it is used in a stage-2 CoW mapping of anonymous memory. So disregard the zero page explicitly in sanitise_mte_tags(). Fixes: f620d66af316 ("arm64: mte: Do not flag the zero page as PG_mte_tagged") Cc: stable@vger.kernel.org # 5.10.x Suggested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2026-06-05arm64: Avoid double evaluation of __ptep_get()Ard Biesheuvel
Sashiko warns that the new pte_valid_noncont() macro is used in a manner where the argument (which performs a READ_ONCE() of the descriptor) is evaluated twice. Drop the macro that we just added, and move the check into the newly added users. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
2026-06-05arm64: Rename page table BSS section to .bss..pgtblArd Biesheuvel
Rename the .pgdir.bss section to .bss..pgtbl so that the compiler will notice the leading ".bss" and mark it as NOBITS by default (rather than PROGBITS, which would take up space in Image binary, forcing all of the preceding BSS to be emitted into the image as well). This supersedes the NOLOAD linker directive, which achieves the same thing, and can be therefore be dropped. Also, rename .pgdir to .pgtbl to be more generic, as page tables of various levels will reside here. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Mark Brown <broonie@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
2026-06-05x86/process: Convert rdmsr() to rdmsrq() in arch_post_acpi_subsys_init() to ↵HyeongJun An
address W=1 warning arch_post_acpi_subsys_init() reads MSR_K8_INT_PENDING_MSG with rdmsr() into a lo/hi pair but only uses the low 32 bits: K8_INTP_C1E_ACTIVE_MASK (0x18000000) lies entirely within them. The 'hi' half is never consumed, which triggers a -Wunused-but-set-variable warning under W=1: arch/x86/kernel/process.c: In function 'arch_post_acpi_subsys_init': arch/x86/kernel/process.c:972:17: warning: variable 'hi' set but not used Read the full MSR into a single u64 with rdmsrq() and test the mask against it, dropping the now-unnecessary lo/hi variables. No functional change intended. Signed-off-by: HyeongJun An <sammiee5311@gmail.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Jürgen Groß <jgross@suse.com> Link: https://patch.msgid.link/20260604150052.3337246-1-sammiee5311@gmail.com
2026-06-05KVM: arm64: Take the SRCU lock for page table walks in fault injection and ↵Hyunwoo Kim
AT emulation walk_s1() and kvm_walk_nested_s2() expect to be called while holding kvm->srcu to guard against memslot changes. While this is generally the case, __kvm_at_s12() and __kvm_find_s1_desc_level() call into the respective walkers without taking kvm->srcu. Fix by acquiring kvm->srcu prior to the table walk in both instances. Cc: stable@vger.kernel.org Fixes: 50f77dc87f13 ("KVM: arm64: Populate level on S1PTW SEA injection") Fixes: be04cebf3e78 ("KVM: arm64: nv: Add emulation of AT S12E{0,1}{R,W}") Suggested-by: Oliver Upton <oupton@kernel.org> Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com> Reviewed-by: Oliver Upton <oupton@kernel.org> Link: https://patch.msgid.link/aiAZfdeyanIvP8SD@v4bel Signed-off-by: Marc Zyngier <maz@kernel.org>
2026-06-05KVM: arm64: vgic-its: Drop the translation cache reference only for the ↵Hyunwoo Kim
erased entry vgic_its_invalidate_cache() walks the per-ITS translation cache with xa_for_each() and drops the cache's reference on each entry with vgic_put_irq(). It puts the iterated pointer, though, rather than the value returned by xa_erase(). The function is called from contexts that do not exclude one another: the ITS command handlers hold its_lock, the GITS_CTLR write path holds cmd_lock, and the path that clears EnableLPIs in a redistributor's GICR_CTLR holds neither. Two or more of them can drain the same cache concurrently, and if each one observes the same entry, erases it and then puts it, the single reference the cache holds on that entry is dropped more than once. The entry can then be freed while an ITE still maps it. xa_erase() is atomic and returns the previous entry, so put only the entry that this context actually removed. The cache reference is then dropped exactly once per entry even when the invalidations run concurrently, and the behavior is unchanged when only one context runs. Fixes: 8201d1028caa ("KVM: arm64: vgic-its: Maintain a translation cache per ITS") Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com> Reviewed-by: Oliver Upton <oupton@kernel.org> Link: https://patch.msgid.link/ah2c5lu4JbUg7dj-@v4bel Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org
2026-06-05x86/resctrl: Only check Intel systems for SNCTony Luck
topology_num_nodes_per_package() reports values greater than one on certain AMD systems resulting in resctrl's Intel model specific SNC detection printing the confusing message: "CoD enabled system? Resctrl not supported" Add a check for Intel systems before looking at the topology. [ reinette: Add Closes tag, fix tag typos, rework changelog ] Fixes: 59674fc9d0bf ("x86/resctrl: Fix SNC detection") Reported-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Tested-by: Babu Moger <babu.moger@amd.com> Link: https://patch.msgid.link/9849330f45ac86344cc5ac54df2d313906d70bc4.1780634584.git.reinette.chatre@intel.com Closes: https://lore.kernel.org/lkml/37ac0376-43a3-4283-a3d5-4d57b3bec578@amd.com/
2026-06-04Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Cross-merge networking fixes after downstream PR (net-7.1-rc7). Silent conflicts: net/wireless/nl80211.c cb9959ab5f99 ("wifi: cfg80211: enforce HE/EHT cap/oper consistency") a384ae969902 ("wifi: cfg80211: move AP HT/VHT/... operation to beacon info") https://lore.kernel.org/aiGJDaHV4UlCexIQ@sirena.org.uk Conflicts: drivers/net/wireless/intel/iwlwifi/mld/ap.c a342c99cb70d ("wifi: iwlwifi: mld: honor BSS_CHANGED_BEACON_ENABLED") 9bf1b409afc7 ("wifi: iwlwifi: mld: send tx power constraints before link activation") https://lore.kernel.org/ah2bfedhV45ZxMO8@sirena.org.uk drivers/net/wireless/intel/iwlwifi/pcie/drv.c 093305d801fa ("wifi: iwlwifi: pcie: simplify the resume flow if fast resume is not used") e2323929a68a ("wifi: iwlwifi: pcie: add debug print for resume flow if powered off") https://lore.kernel.org/ah2bfedhV45ZxMO8@sirena.org.uk Adjacent changes: drivers/net/ethernet/airoha/airoha_eth.c b38cae85d1c4 ("net: airoha: Fix use-after-free in metadata dst teardown") ec6c391bcca7 ("net: airoha: Introduce airoha_gdm_dev struct") drivers/net/ethernet/microchip/lan743x_main.c 8173d22b211f ("net: lan743x: permit VLAN-tagged packets up to configured MTU") e3c6508a46f5 ("net: lan743x: avoid netdev-based logging before netdev registration") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-04Merge tag 's390-7.1-4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux Pull s390 fixes from Alexander Gordeev: - Enable IOMMUFD and VFIO cdev such that PCI pass-through to QEMU/KVM can optionally utilize native IOMMUFD - With HAVE_ARCH_BUG_FORMAT enabled the BUG infrastructure might misinterpret flags or fault. Fix this by moving the "format" field emission into __BUG_ENTRY() - The generic version of _THIS_IP_ is known to be brittle and may break with current and future GCC and Clang optimizations. Fix it by overriding _THIS_IP_ * tag 's390-7.1-4' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: s390: Implement _THIS_IP_ using inline asm s390/bug: Always emit format word in __BUG_ENTRY s390/configs: Enable IOMMUFD and VFIO cdev in defconfigs
2026-06-04MIPS: VDSO: Only map the data pages when the vDSO is usedThomas Weißschuh
A future change will make it possible to disable the time-related vDSO. In that case there is no point in calling into the datastore. Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Link: https://patch.msgid.link/20260521-vdso-mips-kconfig-v1-4-2f79dcd6c78f@linutronix.de
2026-06-04MIPS: Introduce Kconfig MIPS_GENERIC_GETTIMEOFDAYThomas Weißschuh
The logic to enable the generic vDSO Kconfig symbols is about to become more complex. Introduce a new helper symbol to keep the configuration readable. Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Link: https://patch.msgid.link/20260521-vdso-mips-kconfig-v1-3-2f79dcd6c78f@linutronix.de
2026-06-04x86/microcode/AMD: Move the no-revision fixup to get_patch_level()Borislav Petkov (AMD)
On machines which don't have microcode applied yet, the revision is 0. However, this doesn't work with the Zen family/model/stepping patch arithmetic. So move the fixup to the patch level getter function and this way make sure the patch level is always proper and thus the arithmetic always works. And now that it can be called on any family, make this Zen-only. Assisted-by: claude/claude-opus-4-6 Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20260530024213.86137-1-bp@kernel.org
2026-06-04x86/pmem: Check for platform_device_alloc() retvalLi Jun
Add proper error handling for the case when platform_device_alloc() returns NULL due to memory allocation failure. This prevents a potential NULL pointer dereference when trying to use the pdev pointer without checking if allocation succeeded. [ bp: Massage commit message. ] Signed-off-by: Li Jun <lijun01@kylinos.cn> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20260602100711.2542568-1-lijun01@kylinos.cn
2026-06-04KVM: x86: Use <linux/lockdep.h> for lockdep header inclusionKai Huang
When KVM added a lockdep assertion to catch unexpected cases where guest CPUID lookups are performed in IRQ disabled context, it used "linux/lockdep.h" for header inclusion even though lockdep.h is a kernel wide header. Switch to using <linux/lockdep.h>. Fixes: 9717efbe5ba3 ("KVM: x86: Disallow guest CPUID lookups when IRQs are disabled") Signed-off-by: Kai Huang <kai.huang@intel.com> Link: https://patch.msgid.link/20260604011106.315176-1-kai.huang@intel.com [sean: add Fixes, Kai is too polite :-)] Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-06-04Merge tag 'socfpga_dts_updates_for_v7.2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt SoCFPGA DTS updates for v7.2 - dt-bindings updates: - Document compatible for Agilex5 socdk debug daughter card - Document compatible for Agilex7-M devkit - Add support for Agilex7-M devkit - Remove reg property in the PMU on 32-bit SoCFPGA - Set i3c alias on Agilex3 and Agilex5 - Update data-width of DMA controller on Agilex5 - Set phy-mode to rgmii on Agilex5 - Increase the JFFS2 rootfs partition on the Arria10 NAND SoCDK * tag 'socfpga_dts_updates_for_v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: socfpga: arria10: Increase JFFS2 rootfs partition size dt-bindings: altera: add compatible for agilex5 socdk debug daughter card arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay arm64: dts: socfpga: agilex5: update data-width for dmac arm64: dts: socfpga: agilex3: set alias for i3c controller arm64: dts: socfpga: agilex5: set alias for i3c controllers ARM: dts: socfpga: remove the reg property in the pmu arm64: dts: socfpga: agilex7m: Add SoCFPGA Agilex7-M devkit dt-bindings: arm: altera: document the Agilex7-M devkit Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-04perf/x86/amd/uncore: Use Node ID to identify DF and UMC domainsSandipan Das
For DF and UMC PMUs, a single context is shared across all CPUs that are connected to the same Data Fabric (DF) instance. Currently, the Package ID, which also happens to be the Socket ID, is used to identify DF instances. This approach works for configurations having a single IO Die (IOD) but fails in the following cases. * Older Zen 1 processors, where each chiplet has its own DF instance. * Any configurations with multiple DF instances or multiple IODs in the same package. The correct way to identify DF instances is through the Node ID (not to be confused with NUMA Node ID). This is available in ECX[7:0] of CPUID leaf 0x8000001e and returned via topology_amd_node_id(). Hence, replace usage of topology_logical_package_id() with topology_amd_node_id(). Fixes: 07888daa056e ("perf/x86/amd/uncore: Move discovery and registration") Signed-off-by: Sandipan Das <sandipan.das@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/e7a71a727c6a7b118c23d3e469929c538c4665aa.1780315832.git.sandipan.das@amd.com
2026-06-04perf/x86/intel/uncore: Implement global init callback for GNR uncoreZide Chen
On Sierra Forest and Clearwater Forest, the FRZ_ALL bit in the global control register defaults to 0 at boot, but UBOX PMON units do not work until the global control register is explicitly written with 0 to trigger hardware initialization properly. Implement the generic uncore_msr_global_init() callback and add it to gnr_uncore_init[], which is shared by GNR, GRR, SRF, and CWF. Fixes: 632c4bf6d007 ("perf/x86/intel/uncore: Support Granite Rapids") Signed-off-by: Zide Chen <zide.chen@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Link: https://patch.msgid.link/20260602144908.263680-8-zide.chen@intel.com
2026-06-04perf/x86/intel/uncore: Fix uncore_die_to_cpu() for offline diesZide Chen
If the die is offline when uncore_die_to_cpu() is called, it silently returns 0, which is misleading. Return -1 in this case to indicate that all CPUs on the die are offline and the caller can take care of it accordingly. Opportunistically, replace -EPERM with -ENODEV, as -ENODEV is the appropriate error when no CPUs are online across all dies. Signed-off-by: Zide Chen <zide.chen@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Link: https://patch.msgid.link/20260602144908.263680-7-zide.chen@intel.com
2026-06-04perf/x86/intel/uncore: Move die_to_cpu() to uncore.cZide Chen
Move die_to_cpu() into uncore.c so it can be reused by the MSR initialization path, preparing for the introduction of an MSR global initialization callback. Move the cpus_read_{lock,unlock}() out of the API, in order to make it possible to be called when the lock is being held. Add the uncore_ prefix for consistency with other uncore APIs. Signed-off-by: Zide Chen <zide.chen@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Link: https://patch.msgid.link/20260602144908.263680-6-zide.chen@intel.com
2026-06-04perf/x86/intel/uncore: Defer ADL global PMON enable to enable_box()Zide Chen
On some Raptor Cove CPUs, enabling uncore PMON globally at driver init may increase power consumption even when no perf events are in use. Drop adl_uncore_msr_init_box() and defer programming the global control register to enable_box(), so it is only set when a box is actually used. IMC and IMC freerunning counters use a separate control path and are unaffected. Fixes: 772ed05f3c5c ("perf/x86/intel/uncore: Add Alder Lake support") Signed-off-by: Zide Chen <zide.chen@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260602144908.263680-5-zide.chen@intel.com
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-19 19:15:29 +0000