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2026-06-15net: ti: icssg: Use undirected TX tag for XDP zero copy in HSR offload modeMeghana Malladi
emac_xsk_xmit_zc() has the same issue as the fixed emac_xmit_xdp_frame(): it always sets the CPPI5 descriptor destination tag to emac->port_id, which directs the PRU firmware to transmit on only one slave port in HSR mode, breaking redundancy. Apply the same fix: in HSR offload mode when NETIF_F_HW_HSR_DUP is set, use PRUETH_UNDIRECTED_PKT_DST_TAG (port 0) so the PRU duplicates frames to both ports. Also set PRUETH_UNDIRECTED_PKT_TAG_INS when NETIF_F_HW_HSR_TAG_INS is set so the PRU re-inserts the HSR sequence tag that was stripped by the PRU on RX before the XDP program saw the frame. This ensures XSK XDP_TX frames in HSR mode are treated identically to skb TX via hsr0. Fixes: 8756ef2eb078 ("net: ti: icssg-prueth: Add AF_XDP zero copy for TX") Signed-off-by: Meghana Malladi <m-malladi@ti.com> Link: https://patch.msgid.link/20260611185744.2498070-4-m-malladi@ti.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: ti: icssg: Use undirected TX tag for native XDP in HSR offload modeMeghana Malladi
emac_xmit_xdp_frame() always sets the CPPI5 descriptor destination tag to emac->port_id, which directs the PRU firmware to transmit the frame on that specific slave port only. In HSR offload mode this bypasses the firmware's HSR duplication logic: the frame goes out on one ring leg and never appears on the other, breaking HSR redundancy for XDP_TX paths. icssg_ndo_start_xmit() already handles this correctly: when HSR offload mode is active and NETIF_F_HW_HSR_DUP is set it substitutes PRUETH_UNDIRECTED_PKT_DST_TAG (port 0) so the PRU duplicates the frame to both slave ports. It also sets PRUETH_UNDIRECTED_PKT_TAG_INS in epib[1] when NETIF_F_HW_HSR_TAG_INS is set so the PRU inserts the HSR sequence tag, which XDP_TX frames lack (the tag is stripped by the PRU on RX before the frame reaches the XDP program). Apply the same logic in emac_xmit_xdp_frame() so XDP_TX frames in HSR mode are treated identically to skb TX via hsr0. Fixes: 62aa3246f462 ("net: ti: icssg-prueth: Add XDP support") Signed-off-by: Meghana Malladi <m-malladi@ti.com> Link: https://patch.msgid.link/20260611185744.2498070-3-m-malladi@ti.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: ti: icssg-prueth: Fix AF_XDP fill ring alloc and wakeup conditionMeghana Malladi
emac_rx_packet_zc() calls prueth_rx_alloc_zc() with count (frames received in the current NAPI poll) as the allocation budget. Two problems arise from this: 1. When the CPPI5 descriptor pool is exhausted (avail_desc == 0, FDQ already holds the maximum number of descriptors), count > 0 still triggers allocation attempts that all fail, spamming the kernel log with "rx push: failed to allocate descriptor" at high packet rates. 2. The XSK wakeup condition "ret < count" is wrong when avail_desc is zero: ret == 0 and count can be up to 64, so the condition is always true. This causes ~200 spurious ndo_xsk_wakeup() calls per second even when the FDQ is already full, wasting CPU cycles in repeated NAPI invocations that process zero frames. Fix both by introducing alloc_budget = min(budget, avail_desc): - When avail_desc == 0 no allocation is attempted, avoiding pool exhaustion errors. The wakeup condition "ret < alloc_budget" evaluates to 0 < 0 == false, correctly clearing the wakeup flag so the hardware IRQ re-arms NAPI without spurious kicks. - In steady state avail_desc == count <= budget, so alloc_budget == count and behaviour is unchanged. - After a dry-ring stall (count == 0, avail_desc > 0), alloc_budget > 0 causes new descriptors to be posted to the FDQ so the hardware can resume receiving immediately. Fixes: 7a64bb388df3 ("net: ti: icssg-prueth: Add AF_XDP zero copy for RX") Signed-off-by: Meghana Malladi <m-malladi@ti.com> Link: https://patch.msgid.link/20260611185744.2498070-2-m-malladi@ti.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: airoha: Fix MODULE_LICENSE to match SPDX GPL-2.0-only identifierWayen.Yan
Both airoha_eth.c and airoha_npu.c declare SPDX-License-Identifier: GPL-2.0-only but use MODULE_LICENSE("GPL"), which the kernel module loader interprets as GPL-2.0+ (any GPL version). This mismatch causes license compliance tools (FOSSology, ScanCode, etc.) to misidentify the effective license as more permissive than intended. Replace MODULE_LICENSE("GPL") with MODULE_LICENSE("GPL v2") to align with the GPL-2.0-only SPDX identifier. Per include/linux/module.h, "GPL v2" maps to GPL-2.0-only, matching the source files' declared license. Signed-off-by: Wayen <win847@gmail.com> Link: https://patch.msgid.link/6a2ded59.63d39acb.391892.7632@mx.google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net/mlx5: HWS: correct CONFIG_MLX5_HW_STEERING macro name in commentEthan Nelson-Moore
A comment in drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.h incorrectly refers to CONFIG_MLX5_HWS_STEERING instead of CONFIG_MLX5_HW_STEERING. Correct it. Discovered while searching for CONFIG_* symbols referenced in code but not defined in any Kconfig file. Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com> Reviewed-by: Gal Pressman <gal@nvidia.com> Link: https://patch.msgid.link/20260613225904.140791-1-enelsonmoore@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: airoha: Fix typos in comments and KconfigWayen.Yan
Fix several typos found during code review: - Kconfig: "Aiorha" -> "Airoha" in NET_AIROHA_FLOW_STATS help text - Comment: "CMD1" -> "CDM1" (Central DMA, not Command) - Comments: "GMD1/2/3/4" -> "GDM1/2/3/4" (Gigabit DMA, not GMD) These are pure comment and documentation fixes with no functional impact. Signed-off-by: Wayen.Yan <win847@gmail.com> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://patch.msgid.link/6a2ca74a.c5b1db4e.21a698.01e7@mx.google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: airoha: Fix always-true condition in PPE1 queue reservation loopWayen.Yan
In airoha_fe_pse_ports_init(), the inner condition for PPE1 queue reservation is identical to the for-loop bound, making it always true and the else branch dead code: for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) { if (q < pse_port_num_queues[FE_PSE_PORT_PPE1]) /* always true */ set RSV_PAGES; else set 0; /* unreachable */ } The intended behavior is to reserve pages only for the first half of the queues, matching the PPE2 implementation on line 334 which correctly uses the /2 divisor. Fix the PPE1 condition accordingly. Fixes: 23020f049327 ("net: airoha: Introduce ethernet support for EN7581 SoC") Signed-off-by: Wayen.Yan <win847@gmail.com> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://patch.msgid.link/6a2ca3de.ad59c0a6.147df9.2ac1@mx.google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: airoha: Fix non-standard return value in airoha_ppe_get_wdma_info()Wayen.Yan
airoha_ppe_get_wdma_info() returns -1 when the last path in the forwarding path stack is not of type DEV_PATH_MTK_WDMA. This is not a standard kernel error code. Replace it with -EINVAL since the input path type is invalid from the caller's perspective. Signed-off-by: Wayen.Yan <win847@gmail.com> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://patch.msgid.link/6a2ca3d9.ad59c0a6.147df9.2a62@mx.google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: add AQC113 PTP support in aq_ptp and driver coreSukhdeep Singh
aq_ptp.c / aq_ptp.h: - Add aq_ptp_state enum (AQ_PTP_FIRST_INIT, AQ_PTP_LINK_UP, AQ_PTP_NO_LINK) to distinguish first init from link-change events; on AQC113 only reset the TSG clock on first init to avoid disrupting ongoing synchronization. - Add aq_ptp_dpath_enable() for comprehensive L3/L4 PTP filter setup/teardown, replacing the previous single-filter approach with an array of 4 slots for IPv4 and IPv6 PTP multicast addresses (224.0.1.129, 224.0.0.107, ff0e::181, ff02::6b). - Add aq_ptp_parse_rx_filters() to map hwtstamp_rx_filters to L2/L4 enable flags and call aq_ptp_dpath_enable(). - Re-apply RX filters on link change (hardware state lost after reset). - Extend PTP ring alloc/init/start/stop to handle AQC113 PTP ring ops. - Add per-instance PTP offset table for AQC113 with empirically measured values at 100M/1G/2.5G/5G/10G link speeds. - Export aq_ptp_dpath_enable() and updated ring helpers in aq_ptp.h. aq_hw.h: - Include hw_atl2/hw_atl2.h for AQC113 PTP type definitions. aq_nic.c: - Account for PTP IRQ vector (AQ_HW_PTP_IRQS) in vector count math. - Call hw_atl2 PTP re-enable hook after hardware reset in aq_nic_update_link_status(). aq_pci_func.c: - Pass PTP IRQ index to aq_ptp_irq_alloc() in probe path. Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-13-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: add AQC113 TX timestamp polling and PTP TX classificationSukhdeep Singh
aq_ring.h / aq_ring.c: - Add ptp_ts_deadline field to aq_ring_s to track TX timestamp timeout. - In aq_ring_tx_clean(): when hw_ring_tx_ptp_get_ts() returns 0 (HW not yet written back the timestamp), clear buff->is_mapped and buff->pa before breaking to prevent double dma_unmap on retry. When ptp_ts_deadline expires, dequeue and drop the head of skb_ring to keep it in lockstep with buff_ring, then clear request_ts and free the skb via dev_kfree_skb_any() to unblock the ring. aq_main.c: - Add IPv6 PTP packet detection in aq_ndev_start_xmit() using ipv6_hdr()->nexthdr for ETH_P_IPV6 frames, steering them through aq_ptp_xmit() alongside the existing IPv4 path. - Use PTP_EV_PORT/PTP_GEN_PORT constants instead of magic numbers 319/320. - Remove duplicate aq_reapply_rxnfc_all_rules() and aq_filters_vlans_update() calls from aq_ndev_open() - now covered by aq_nic_start(), which also ensures filters are restored correctly after PM resume. aq_nic.c: - Move aq_reapply_rxnfc_all_rules() and aq_filters_vlans_update() into aq_nic_start() after hardware init, replacing the duplicate calls that were removed from aq_ndev_open(). Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-12-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: add AQC113 PTP hardware ops in hw_atl2Sukhdeep Singh
Add the hardware-layer PTP implementation for AQC113 (Antigua): - hw_atl2.h/hw_atl2_utils.h/hw_atl2_internal.h: add PTP offset constants, RX timestamp size (HW_ATL2_RX_TS_SIZE=8), and reduced HW_ATL2_RXBUF_MAX=172 (AQC113 on-chip RX packet buffer hardware limit for data TCs). - hw_atl2.c: implement hw_atl2_enable_ptp() to reset and enable TSG clocks and set PTP TC scheduling priority after hardware reset. - hw_atl2.c: implement hw_atl2_adj_sys_clock(), hw_atl2_adj_clock_freq(), and aq_get_ptp_ts() for TSG clock read/adjust/increment operations. - hw_atl2.c: implement hw_atl2_gpio_pulse() for PPS output generation via TSG pulse generator. - hw_atl2.c: implement hw_atl2_hw_tx_ptp_ring_init() and hw_atl2_hw_rx_ptp_ring_init() for PTP ring setup. - hw_atl2.c: implement hw_atl2_hw_ring_tx_ptp_get_ts() to read TX timestamp from descriptor writeback, and hw_atl2_hw_rx_extract_ts() to extract RX timestamp from the 8-byte packet trailer. - hw_atl2.c: add hw_atl2_hw_get_clk_sel() helper. - Wire all new ops into hw_atl2_ops. Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-11-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: extend hw_ops and TX descriptor for AQC113 PTPSukhdeep Singh
Extend the aq_hw_ops interface with new function pointers required for PTP support on AQC113: - enable_ptp: enable/disable PTP counter with clock selection - hw_ring_tx_ptp_get_ts: read TX timestamp from descriptor writeback - hw_tx_ptp_ring_init/hw_rx_ptp_ring_init: per-ring PTP initialization - hw_get_clk_sel: query active TSG clock selection Update existing hw_ops signatures to support AQC113 dual-clock architecture: - hw_gpio_pulse: add clk_sel and hightime parameters - hw_extts_gpio_enable: add channel parameter Add PTP-related hardware defines: - AQ_HW_TXD_CTL_TS_EN/TS_TSG0 for TX descriptor timestamp control - AQ2_HW_PTP_COUNTER_HZ for AQC113 TSG clock frequency - AQ_HW_PTP_IRQS for PTP interrupt vector accounting - PTP enable flags (L2/L4) and TSG clock selection constants Add request_ts and clk_sel bitfields to aq_ring_buff_s for per-packet TX timestamp request tracking. Update hw_atl_b0.c (AQC107) implementations: - Adapt gpio_pulse and extts_gpio_enable to new signatures - Add TX descriptor timestamp bits for AQC113 when ANTIGUA chip feature is detected Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-10-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: add AQC113 PTP traffic class and TX path setupSukhdeep Singh
Add PTP traffic class (TC) buffer reservation and TX path improvements for AQC113: - Reserve dedicated TX and RX buffer space for PTP TC when PTP is enabled, reducing user TC buffers accordingly (TX: 8KB, RX: 16KB). - Configure PTP TC with no flow control and highest priority scheduling to ensure timely PTP packet transmission. TX path improvements: - Increase TX data and descriptor read-request limits when firmware has already enabled extended PCIe tag mode. Also simplify RSS queue calculation in hw_atl2_hw_rss_set() by extracting to a local variable and use unsigned types for loop variables to match their usage. Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-9-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: implement AQC113 L2/L3/L4 RX filter opsSukhdeep Singh
Implement complete RX filter management for AQC113 hardware: - Add tag-based ethertype filter policy (hw_atl2_filter_tag_get/put) that allocates and releases ART tags for L2 ethertype filters. - Add L3/L4 filter sharing via serialized usage counters in hw_atl2_l3_filter/hw_atl2_l4_filter, managed through hw_atl2_rxf_l3_get/put and hw_atl2_rxf_l4_get/put. - Implement L3 (IPv4/IPv6 source/destination address and protocol) filter find, get (program HW and increment refcount), and put (decrement refcount and clear HW when last user releases). - Implement L4 (TCP/UDP/SCTP source/destination port) filter management with the same find/get/put pattern. - Add combined L3L4 filter configuration (hw_atl2_new_fl3l4_configure) that translates legacy aq_rx_filter_l3l4 commands into AQC113 separate L3+L4 filter programming with Action Resolver Table (ART) entries. - Add L2 ethertype filter set/clear (hw_atl2_hw_fl2_set/clear) with tag-based ART integration. - Wire .hw_filter_l2_set, .hw_filter_l2_clear, .hw_filter_l3l4_set into hw_atl2_ops. Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-8-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: fix AQC113 HW init: ART, L2 filter slot, MAC addressSukhdeep Singh
Fix initialization issues in hw_atl2 to correctly support AQC113: - hw_atl2_hw_reset: replace unconditional priv memset with selective field clears so that l3l4_filters[].l3_index and l4_index can be initialized to -1 (not allocated) rather than 0; 0 is a valid filter index and would incorrectly appear as an occupied slot after a reset. - hw_atl2_hw_init_new_rx_filters: use firmware-reported ART section base and count (clamped to 16) instead of hardcoded 0xFFFF mask; enable simultaneous IPv4/IPv6 L3 filter mode (rpf_l3_v6_v4_select); tag the UC MAC slot using firmware-supplied l2_filters_base_index instead of hardcoded HW_ATL2_MAC_UC. - hw_atl2_hw_init_rx_path: enable only the firmware-assigned MAC slot (priv->l2_filters_base_index) instead of always slot 0. - Add hw_atl2_hw_mac_addr_set() that programs the MAC address into the firmware-assigned L2 filter slot. Wire into hw_atl2_ops replacing the A1 hw_atl_b0_hw_mac_addr_set; call it from hw_init. - Wire .hw_get_regs into hw_atl2_ops. Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-7-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: add AQC113 filter data structures, firmware query and ↵Sukhdeep Singh
register dump Add filter infrastructure for AQC113 hardware: - Define L3 (IPv4/IPv6), L4 (TCP/UDP/SCTP), and combined L3L4 filter structures with serialized usage counter for filter sharing. - Define tag policy structure for ethertype filter management. - Add RPF L3/L4 command bit definitions for filter programming. - Add filter count constants for L3L4, L3V4, L4, VLAN, and ethertype. - Extend hw_atl2_priv with filter arrays, base indices, and counts discovered from firmware. Query filter capabilities from firmware shared memory at init time to discover available L2/L3/L4/VLAN/ethertype filter resources and ART (Action Resolver Table) configuration. Add hardware register dump utility for AQC113 debug support. Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-6-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: add AQC113 hardware register definitions and accessorsSukhdeep Singh
Add low-level hardware register definitions and accessor functions for AQC113 (Antigua) chip features: - L3/L4 filter command, tag, and address registers for IPv4/IPv6 - Ethertype filter tag registers - TSG (Time Stamp Generator) clock control, modification, and GPIO event generation/input timestamp registers - TX descriptor timestamp writeback, timestamp enable, and AVB enable registers - TX data/descriptor read request limit registers - TPB highest priority TC registers - PCIe extended tag enable register - RX descriptor timestamp request register - Action resolver section enable getter - GPIO special mode and TSG external GPIO TS input select Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-5-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: decouple aq_set_data_fl3l4() from driver internalsSukhdeep Singh
Refactor aq_set_data_fl3l4() to take an ethtool_rx_flow_spec pointer and an explicit HW register location instead of driver-internal structures (aq_nic_s, aq_rx_filter). This makes the function reusable for PTP filter setup which constructs flow specs independently. Key changes: - Add aq_is_ipv6_flow_type() helper to derive IPv6 status from the flow_type field, replacing the dependency on rx_fltrs->fl3l4.is_ipv6 shared state. - Change aq_set_data_fl3l4() signature to accept (fsp, data, location, add) and export it via aq_filters.h. - Update aq_add_del_fl3l4() to compute the HW register location and pass it explicitly. Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-4-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: move active_ipv4/ipv6 bitmap updates after HW writeSukhdeep Singh
Move active_ipv4/active_ipv6 bitmap updates from aq_set_data_fl3l4() into aq_add_del_fl3l4() after the hardware write succeeds. The bitmaps track which filter slots are actively programmed in hardware and must only be updated once the HW write is confirmed. The bitmap updates in aq_nic_reserve_filter() and aq_nic_release_filter() are intentionally retained: they guard the aq_check_approve_fl3l4() IPv4/IPv6 mixing validation for callers such as the AQC113 PTP path that program filters directly via hw_atl2_new_fl3l4_configure() without going through aq_add_del_fl3l4(). Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-3-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: atlantic: correct L3L4 filter flow_type masking and IPv6 handlingSukhdeep Singh
Correct three issues in aq_set_data_fl3l4() required for the AQC113 PTP filter path introduced later in this series: 1. Mask FLOW_EXT from flow_type before the protocol switch statement. Flow types with FLOW_EXT set (e.g. TCP_V4_FLOW | FLOW_EXT) fall through to the default case and skip protocol comparison flags. 2. Extend the L3 address comparison check to cover all four IPv6 words. The original code only checked ip_src[0]/ip_dst[0] and required !is_ipv6, so CMP_SRC_ADDR_L3/CMP_DEST_ADDR_L3 were never set for IPv6 filters. 3. Use explicit flow type checks for port extraction instead of negating IP_USER_FLOW/IPV6_USER_FLOW. The old check did not mask FLOW_EXT, so IP_USER_FLOW | FLOW_EXT would incorrectly attempt port extraction. Use the actual flow type to pick the correct union member directly. Signed-off-by: Sukhdeep Singh <sukhdeeps@marvell.com> Link: https://patch.msgid.link/20260610115448.272-2-sukhdeeps@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: dsa: netc: implement dynamic FDB entry ageingWei Fang
The NETC switch does not age out dynamic FDB entries automatically. Without software management, stale entries persist after topology changes and cause incorrect forwarding. Add a delayed work that periodically removes entries that have not been refreshed within the specified cycles. The effective ageing time is: ageing_time = fdbt_ageing_delay * 100 Default values are 3s interval and 100 cycles (300s total), matching the IEEE 802.1Q default ageing time. The work starts when the first port joins a bridge (tracked via br_cnt) and is cancelled when the last port leaves. All FDB operations are serialized under fdbt_lock. Implement .set_ageing_time() to allow the bridge layer to reconfigure ageing parameters on demand. Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260611021458.2629145-10-wei.fang@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: dsa: netc: add bridge mode supportWei Fang
Wire up the port_bridge_join, port_bridge_leave and port_vlan_filtering DSA callbacks to support both VLAN-unaware and VLAN-aware bridge modes. For VLAN-unaware bridges, each bridge instance is assigned a dedicated internal PVID via NETC_VLAN_UNAWARE_PVID(bridge.num), counting down from VID 4095. A VFT entry is created for this PVID with hardware MAC learning and flood-on-miss forwarding enabled. The CPU port is included as a VFT member so frames can reach the host. The reserved VID range is blocked in port_vlan_add to prevent user-space conflicts. Only one VLAN-aware bridge is supported at a time; this constraint is enforced in port_bridge_join and port_vlan_filtering. The per-port PVID is tracked in software and written to the BPDVR register whenever VLAN filtering is active. When a port leaves the bridge, its dynamic FDB entries are flushed right away in port_bridge_leave(), without waiting for the ageing cycle. When a link down event occurs on a port, netc_mac_link_down() will also clear the port's dynamic FDB entries via netc_port_remove_dynamic_entries(). Non-bridge ports have no dynamic FDB entries, so this call is always safe. Additionally, .port_fast_age() callback is added to flush the dynamic FDB entries associated to a port. Host flood rules are removed from the ingress port filter table when a port joins a bridge to avoid bypassing FDB lookup and MAC learning. Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260611021458.2629145-9-wei.fang@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: dsa: netc: add VLAN filter table and egress treatment managementWei Fang
Implement the DSA .port_vlan_add and .port_vlan_del operations to enable VLAN-aware bridge offloading on the NETC switch. VLAN membership is maintained in the VLAN Filter Table (VFT). Adding the first port to a VLAN creates a new VFT entry with hardware MAC learning and flood-on-miss forwarding; subsequent ports update the existing entry's membership bitmap. Removing the last port deletes the entry. Egress tagging is handled through the Egress Treatment Table (ETT). Each VLAN is allocated a group of ETT entries, one per available port. Ports are assigned a sequential ett_offset during initialisation, used to address each port's entry within the group. Untagged ports configure the ETT to strip the outer VLAN tag; tagged ports pass frames through unmodified. Each ETT group is optionally paired with an Egress Counter Table (ECT) group for per-port frame counting, allocated on a best-effort basis. When the egress rule of an ETT entry changes, the counter of the corresponding ECT entry will be recounted to track the number of frames that match the new egress rule. A software shadow list serialised by vft_lock tracks active VLAN state across both port membership and egress tagging. VID 0 is used for single port mode and is ignored by both callbacks. Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260611021458.2629145-8-wei.fang@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: enetc: add helpers to set/clear table bitmapWei Fang
NTMP index tables require software to allocate and manage entry IDs. Add two bitmap helper functions to facilitate this management: ntmp_lookup_free_eid(): finds the first zero bit in the given bitmap, sets it to mark the entry as in-use, and returns the corresponding entry ID. Returns NTMP_NULL_ENTRY_ID if no free entry is available. ntmp_clear_eid_bitmap(): clears the bit associated with the given entry ID in the bitmap to mark the entry as free. It is a no-op if the entry ID is NTMP_NULL_ENTRY_ID. Both functions are exported for use by other modules, such as the NETC switch driver which needs to manage group index bitmaps for the Egress Treatment Table (ETT) and Egress Count Table (ECT). Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260611021458.2629145-7-wei.fang@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: dsa: netc: initialize the group bitmap of ETT and ECTWei Fang
The Egress Treatment Table (ETT) and Egress Count Table (ECT) are both index tables whose entry IDs are allocated by software. Every num_ports entries form a group, where each entry in the group corresponds to one port. To facilitate group allocation and management, initialize the group index bitmaps for both tables based on hardware capabilities reported by ETTCAPR and ECTCAPR registers. The bitmap size per table is calculated as the total number of hardware entries divided by the number of available ports, which gives the number of groups available for software allocation. A set bit in the bitmap represents a group index that has been allocated. These bitmaps will be used by subsequent patches that add VLAN support. Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260611021458.2629145-6-wei.fang@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: enetc: add "Update" operation to the egress count tableWei Fang
The egress count table is a static bounded index table, egress related statistics are maintained in this table. The table is implemented as a linear array of entries accessed using an index (0, 1, 2, ..., n) that uniquely identifies an entry within the array. Egress Counter Entry ID (EC_EID) is used as an index to an entry in this table. The EC_EID is specified in the egress treatment table. Egress count table entries are always present and enabled. The table only supports access via entry ID, which is assigned by the software. And it supports Update, Query and Query followed by Update operations. Currently, only Update operation is supported. Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260611021458.2629145-5-wei.fang@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: enetc: add interfaces to manage egress treatment tableWei Fang
Each entry in the egress treatment table contains the egress packet processing actions to be applied to a grouping or scope of packets exiting on a particular egress port of the switch. A scope of packets, for example, could be the packets exiting a particular VLAN, matching a particular 802.1Q bridge forwarding entry or belonging to a stream identified at ingress. The egress treatment table is implemented as a linear array of entries accessed using an index (0,1, 2, ..., n) that uniquely identifies an entry within the array. The egress treatment table only supports access vid entry ID, which is assigned by the software. It supports Add, Update, Delete and Query operations. Note that only Query operation is not supported yet. Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260611021458.2629145-4-wei.fang@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: enetc: add "Update" and "Delete" operations to VLAN filter tableWei Fang
Add two interfaces to manage entries in the VLAN filter table: ntmp_vft_update_entry(): Update the configuration element data of the specified VLAN filter entry based on the given VLAN ID. It uses the exact key access method to locate the entry. ntmp_vft_delete_entry(): Delete the VLAN filter entry corresponding to the specified VLAN ID. It also uses the exact key access method to identify the target entry. In addition, introduce struct vft_req_qd to describe the request data buffer format for Query and Delete actions of the VLAN filter table, which contains a common request data header and a VLAN access key. Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260611021458.2629145-3-wei.fang@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: enetc: add interfaces to manage dynamic FDB entriesWei Fang
Add three interfaces to manage dynamic entries in the FDB table: ntmp_fdbt_update_activity_element(): Update the activity element of all dynamic FDB entries. For each entry, if its activity flag is not set, which means no packet has matched this entry since the last update, the activity counter is incremented. Otherwise, both the activity flag and activity counter are reset. The activity counter is used to track how long an FDB entry has been inactive, which is useful for implementing an ageing mechanism. ntmp_fdbt_delete_ageing_entries(): Delete all dynamic FDB entries whose activity flag is not set and whose activity counter is greater than or equal to the specified threshold. This is used to remove stale entries that have been inactive for too long. ntmp_fdbt_delete_port_dynamic_entries(): Delete all dynamic FDB entries associated with the specified switch port. This is typically called when a port goes down or is removed from a bridge. Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260611021458.2629145-2-wei.fang@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: sfp: extend SMBus supportJonas Jelonek
Commit 7662abf4db94 ("net: phy: sfp: Add support for SMBus module access") added SMBus access for SFP modules, but limited it to single-byte transfers. As a side effect, hwmon is disabled (16-bit reads cannot be guaranteed atomic) and a warning is printed. Many SMBus-only I2C controllers in the wild support more than just byte access, and SFP cages are often wired to such controllers rather than to a full-featured I2C controller -- e.g. the SMBus controllers in the Realtek longan and mango SoCs, which advertise word access and I2C block reads. Today, they cannot drive an SFP at all without falling back to the byte-only path. Extend sfp_smbus_read()/sfp_smbus_write() so that, in addition to the existing byte access, they also use SMBus word access and SMBus I2C block access whenever the adapter advertises them. Both directions are handled in a single read and a single write helper that pick the largest supported transfer per chunk and fall back as needed. I2C-block is preferred unconditionally when available: the protocol carries any length 1..32, so it can serve every chunk -- including the 1- and 2-byte tails -- without help from word or byte access. Note that this requires I2C_FUNC_SMBUS_I2C_BLOCK, which reads a caller-specified number of bytes. This deviates from the official SMBus Block Read (length is supplied by the slave) but is widely supported by Linux I2C controllers/drivers. Capability matrix this implementation supports: - BYTE only: works (unchanged behaviour); 1-byte xfers, hwmon disabled. - BYTE + WORD: word for >=2-byte chunks, byte for trailing odd byte. - I2C_BLOCK present (with or without BYTE/WORD): block as the universal transport for every chunk. - WORD only (no BYTE/BLOCK): accepted with WARN_ONCE. Even-length transfers work; odd-length transfers (e.g. the 3-byte cotsworks fixup write) hit the BYTE branch which the adapter does not implement, so the xfer returns an error and the operation is aborted. No mainline I2C driver was found to advertise WORD without BYTE; the warning lets us learn about it if it ever shows up. Adapters with asymmetric R/W capabilities (e.g. only READ_I2C_BLOCK but not WRITE_I2C_BLOCK) remain functionally correct -- the per-iteration fallback uses the direction-specific bits -- but the shared i2c_max_block_size is sized by the all-bits-set check, so a transfer in the better-supported direction is not upgraded. None of the mainline I2C bus drivers surveyed during review advertise such asymmetry; promoting i2c_max_block_size to per-direction sizes can be revisited if needed. Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Link: https://patch.msgid.link/20260614133418.2068201-3-jelonek.jonas@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: sfp: apply I2C adapter quirks to limit block sizeJonas Jelonek
The SFP driver assumes all I2C adapters support reading and writing the pre-defined block size SFP_EEPROM_BLOCK_SIZE of 16 bytes. This constant was probably chosen based on good guesses and known limitations of a range of I2C adapters and SFP modules. However, I2C adapters may even support less and usually need to specify this via I2C quirks. Theoretically, such an adapter may provide full functionality but only support a read and write length of e.g. 8 bytes. Currently, the SFP driver doesn't account for that. Add handling for I2C quirks in SFP I2C configuration taking the fields max_read_len and max_write_len in struct i2c_adapter_quirks into account to further limit the maximum block size if needed. Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Link: https://patch.msgid.link/20260614133418.2068201-2-jelonek.jonas@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15octeontx2-vf: clear stale mailbox IRQ state before request_irq()Runyu Xiao
otx2vf_register_mbox_intr() currently installs the VF mailbox IRQ handler before clearing stale mailbox interrupt state. The code then says that local interrupt bits should be cleared first to avoid spurious interrupts, but that clear still happens only after request_irq() has already made the handler reachable. A running system can reach this during VF mailbox interrupt registration while stale or latched RVU_VF_INT state is still present. If delivery happens in the request_irq()-to-clear window, otx2vf_vfaf_mbox_intr_handler() can run before local quiesce and touch the same vf->mbox and vf->mbox_wq carrier that probe and teardown later reuse or destroy. Move the stale mailbox interrupt clear ahead of request_irq(), but keep interrupt enabling after the handler is installed. This closes the pre-clear early-IRQ window without creating a new enable-before-handler window. Fixes: 3184fb5ba96e ("octeontx2-vf: Virtual function driver support") Cc: stable@vger.kernel.org Signed-off-by: Runyu Xiao <runyu.xiao@seu.edu.cn> Reviewed-by: Simon Horman <horms@kernel.org> Reviewed-by: Ratheesh Kannoth <rkannoth@marvell.com> Link: https://patch.msgid.link/20260611160014.3202224-3-runyu.xiao@seu.edu.cn Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15octeontx2-pf: clear stale mailbox IRQ state before request_irq()Runyu Xiao
otx2_register_mbox_intr() currently installs the PF mailbox IRQ handler before clearing stale mailbox interrupt state. The function itself then comments that the local interrupt bits must be cleared first to avoid spurious interrupts, but that clear happens only after request_irq() has already exposed the handler to irq delivery. A running system can reach this during PF mailbox interrupt registration while stale or latched RVU_PF_INT state is still present. If delivery happens in the request_irq()-to-clear window, otx2_pfaf_mbox_intr_handler() can run before local quiesce and touch the same pf->mbox and pf->mbox_wq carrier that probe and teardown later reuse or destroy. Move the stale mailbox interrupt clear ahead of request_irq(), but keep interrupt enabling after the handler is installed. This closes the pre-clear early-IRQ window without creating a new enable-before-handler window. Fixes: 5a6d7c9daef3 ("octeontx2-pf: Mailbox communication with AF") Cc: stable@vger.kernel.org Signed-off-by: Runyu Xiao <runyu.xiao@seu.edu.cn> Reviewed-by: Simon Horman <horms@kernel.org> Reviewed-by: Ratheesh Kannoth <rkannoth@marvell.com> Link: https://patch.msgid.link/20260611160014.3202224-2-runyu.xiao@seu.edu.cn Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: phy: sfp: detect presence via I2C when no MOD_DEF0 GPIOGreg Patrick
An SFP cage (compatible "sff,sfp") whose MOD_DEF0 signal is not wired to a GPIO currently falls back to sff_gpio_get_state(), which unconditionally reports the module as present. An empty cage therefore fails its probe and is parked in SFP_MOD_ERROR forever; because SFP_F_PRESENT never deasserts there is no REMOVE event to recover the state machine, so a module inserted after boot is never detected, and empty cages spam -EIO at boot. This affects boards that route none of the cage presence signal to a software-readable input. On the NicGiga S100-0800S-M (RTL9303, 8x SFP+) the cage I2C bus is the switch's SMBus master; TX_DISABLE is driven via a PCA9534 I/O expander, but no MOD_ABS/MOD_DEF0 line reaches a readable GPIO (the RTL9303 gpio0 lines read stuck-low, the single PCA9534 is fully consumed by TX_DISABLE, and there is no RTL8231). The Horaco ZX-SW82TS-L2P (RTL9302D, 2x SFP+) is independently affected in the same way. For such an SFP cage, derive presence from a throttled single-byte I2C read of the module EEPROM instead: a successful read asserts SFP_F_PRESENT, R_PROBE_ABSENT consecutive failures clear it (to ride out a transient error on a live module). The existing poll then emits SFP_E_INSERT / SFP_E_REMOVE normally, giving working hot-plug and silencing the boot-time -EIO spam on empty cages. Presence is re-probed every T_PROBE_PRESENT, so insertion is detected within that interval and removal within T_PROBE_PRESENT * R_PROBE_ABSENT. A soldered-down module (compatible "sff,sff") has no presence signal and is genuinely always present, so it continues to use sff_gpio_get_state(); the new path is gated on the cage type advertising SFP_F_PRESENT. Signed-off-by: Greg Patrick <gregspatrick@hotmail.com> Tested-by: Manuel Stocker <mensi@mensi.ch> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Link: https://patch.msgid.link/20260611175341.2223184-1-gregspatrick@hotmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: dsa: mv88e6xxx: Avoid devlink resource IDs collision with PARENT_TOPDavid Yang
The devlink resource ID for ATU collides with the sentinel DEVLINK_RESOURCE_ID_PARENT_TOP (0). As a result, ATU_bin_* are registered as in fact registered as top-level siblings, not as children of ATU. Whether intentional or unintentional, clarify it by keeping the real resource IDs starting at 1. Unfortunately ATU_bin_* are already registered at top-level, so keep their parent to PARENT_TOP. Signed-off-by: David Yang <mmyangfl@gmail.com> Link: https://patch.msgid.link/20260611070856.889700-5-mmyangfl@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: dsa: hellcreek: avoid devlink resource IDs collision with PARENT_TOPDavid Yang
This might not cause real problems, but the hellcreek devlink resource ID collides with the sentinel DEVLINK_RESOURCE_ID_PARENT_TOP (0). Avoid it by keeping the real resource IDs starting at 1. Signed-off-by: David Yang <mmyangfl@gmail.com> Acked-by: Kurt Kanzenbach <kurt@linutronix.de> Link: https://patch.msgid.link/20260611070856.889700-4-mmyangfl@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: dsa: b53: avoid devlink resource IDs collision with PARENT_TOPDavid Yang
This might not cause real problems, but the b53 devlink resource ID collides with the sentinel DEVLINK_RESOURCE_ID_PARENT_TOP (0). Avoid it by keeping the real resource IDs starting at 1. Signed-off-by: David Yang <mmyangfl@gmail.com> Link: https://patch.msgid.link/20260611070856.889700-3-mmyangfl@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net: dsa: dsa_loop: avoid devlink resource IDs collision with PARENT_TOPDavid Yang
This might not cause real problems, but the dsa_loop devlink resource ID collides with the sentinel DEVLINK_RESOURCE_ID_PARENT_TOP (0). Avoid it by keeping the real resource IDs starting at 1. Signed-off-by: David Yang <mmyangfl@gmail.com> Link: https://patch.msgid.link/20260611070856.889700-2-mmyangfl@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15pmdomain: core: fix unused variable warning with !PM_GENERIC_DOMAINS_OFJohan Hovold
The genpd provider bus is really only used when CONFIG_PM_GENERIC_DOMAINS_OF is enabled, and since the recent deferred initialisation of domain parent devices, the root device pointer is otherwise unused. Fix the unused variable warning by moving the definition of the root device pointer inside the corresponding ifdef. Fixes: 92b69eff8012 ("pmdomain: core: fix early domain registration") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202606111746.kAxaAbwg-lkp@intel.com/ Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-06-15net: dsa: hellcreek: replace kcalloc with struct_sizeRosen Penev
One fewer allocation for the priv struct. Signed-off-by: Rosen Penev <rosenp@gmail.com> Acked-by: Kurt Kanzenbach <kurt@linutronix.de> Link: https://patch.msgid.link/20260608045640.5172-1-rosenp@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net/mlx5: SD, enable SD over ECPF and allow switchdev transitionShay Drory
Remove the restriction blocking SD on embedded CPU PFs (ECPF), enabling SD functionality on BlueField DPUs. Remove the blocker preventing SD devices from transitioning to switchdev mode. The infrastructure added in earlier patches properly handles this case. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260612113904.537595-16-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net/mlx5: SD, defer vport metadata init until SD is readyShay Drory
Allow SD devices to transition to switchdev before the SD group is fully up. Metadata allocation requires the SD group to be ready, so defer it from esw_offloads_enable() until SD shared-FDB activation. Add mlx5_esw_offloads_init_deferred_metadata() which allocates per-vport metadata and refreshes the ingress ACLs that were previously programmed with metadata=0. The helper is idempotent and can be called multiple times. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260612113904.537595-15-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net/mlx5: E-Switch, Tie rep load/unload to SD LAG stateShay Drory
On an SD device, vport representors are not functional until the SD group is combined and shared FDB is active. Skip the initial load and the reload paths in that window; reps are loaded as part of the SD LAG activation flow once it becomes active. In addition, explicitly unload representors when SD LAG is destroyed. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260612113904.537595-14-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net/mlx5: LAG, add MPESW over SD LAG supportShay Drory
Enable MPESW LAG creation over SD LAG members, forming a composite LAG hierarchy. This allows bonding multiple SD groups together under a single MPESW configuration with shared FDB. When enabling composite MPESW, the individual SD LAG shared FDB configurations are temporarily torn down and recreated when the composite LAG is disabled. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260612113904.537595-13-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net/mlx5: LAG, introduce software vport LAG implementationShay Drory
SD LAG is a virtual LAG without hardware LAG support, so it cannot use the firmware vport LAG commands. Implement a software-based vport LAG using egress ACL bounce rules. Add esw_set_slave_egress_rule() to create an egress ACL rule on the slave's manager vport that bounces traffic to the master's manager vport. This achieves the same traffic steering as hardware vport LAG. Redirect mlx5_cmd_create_vport_lag() and mlx5_cmd_destroy_vport_lag() to the software implementation when operating in SD LAG mode. In addition, adjust lag_demux creation to check SD LAG mode as well. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260612113904.537595-12-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net/mlx5: LAG, disable both regular and SD LAG on lag_disable_changeShay Drory
Extend mlx5_lag_disable_change() to properly disable both regular LAG and SD LAG when requested. Each LAG type uses its own devcom component for locking. Use mlx5_sd_get_devcom() helper to retrieve the SD devcom component, needed for proper locking when disabling SD LAG. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260612113904.537595-11-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net/mlx5: LAG, store demux resources per master lag_funcShay Drory
The lag demux resources (flow table, flow group, and rules xarray) are stored on the shared ldev. With Socket Direct, multiple SD groups each create their own demux FT/FG during their master's IB device initialization. Since they all write to the same ldev fields, the second group's init overwrites the first group's pointers, leaking the first group's FT/FG. During teardown, the cleanup uses the overwritten pointers, destroying the wrong group's resources and leaving leaked flow tables in the LAG namespace. These leaked tables can interfere with subsequently created demux tables. Move the demux resources from the shared ldev to per-master lag_func instances. Each master device now owns its own independent demux state. The rule_add and rule_del helpers look up the appropriate master's lag_func via the existing filter/group infrastructure. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260612113904.537595-10-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net/mlx5: E-Switch, notify SD on eswitch disableShay Drory
When eswitch is disabled, notify the SD layer so it can clean up SD-specific resources such as the TX flow table root configuration on secondary devices. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260612113904.537595-9-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net/mlx5: SD, support switchdev mode transition with shared FDBShay Drory
When the eswitch transitions, propagate the change to SD: secondaries get their TX flow table root reconfigured for the new mode, and when all group devices move to switchdev, the per-group shared FDB is activated. Shared FDB activation is best-effort - failure does not block the eswitch transition; the next transition retries. Note: the existing mlx5_get_sd() guard that blocks switchdev for SD devices is intentionally retained. It will be removed once all supporting patches are in place. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260612113904.537595-8-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-15net/mlx5: SD, expend vport metadata for SD secondary devicesShay Drory
In Socket Direct configurations the primary and secondary PFs share the same native_port_num. The eswitch vport metadata encodes pf_num in its upper bits to distinguish vports across PFs. Without SD-awareness, both PFs generate identical metadata, causing FDB rules to steer traffic to the wrong representor. Add mlx5_sd_pf_num_get() which remaps the pf_num for SD devices. Use it so each PF in an SD group produces unique vport metadata. Signed-off-by: Shay Drory <shayd@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260612113904.537595-7-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-19 10:50:42 +0000