From a3b955ac911b2e53c2679bb681f233c1ab449377 Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Fri, 21 Feb 2025 18:03:40 +0000 Subject: arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS Update the description and contextually the help text of CONFIG_ARCH_VEXPRESS to reflect the inclusion of all ARM Ltd Platforms. Signed-off-by: Vincenzo Frascino Message-Id: <20250221180349.1413089-2-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla --- arch/arm64/Kconfig.platforms | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 02f9248f7c84..c468c23b2bba 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -374,13 +374,12 @@ config ARCH_UNIPHIER This enables support for Socionext UniPhier SoC family. config ARCH_VEXPRESS - bool "ARMv8 software model (Versatile Express)" + bool "ARM Ltd Platforms" select GPIOLIB select PM select PM_GENERIC_DOMAINS help - This enables support for the ARMv8 software model (Versatile - Express). + This enables support for the ARM Ltd Platforms. config ARCH_VISCONTI bool "Toshiba Visconti SoC Family" -- cgit v1.2.3 From 51e877f12d237af09d4c47312f1e94169ff07bb4 Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Fri, 21 Feb 2025 18:03:41 +0000 Subject: dt-bindings: arm: Add Morello compatibility Add compatibility to Arm Morello System Development Platform. Note: Morello is at the same time the name of an Architecture [1], an SoC [2] and a Board [2]. To distinguish in between Architecture/SoC and Board we refer to the first as arm,morello and to the second as arm,morello-sdp. [1] https://developer.arm.com/Architectures/Morello [2] https://www.morello-project.org/ Acked-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij Message-Id: <20250221180349.1413089-3-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla --- .../devicetree/bindings/arm/arm,morello.yaml | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,morello.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,morello.yaml b/Documentation/devicetree/bindings/arm/arm,morello.yaml new file mode 100644 index 000000000000..b4cfa8d048c4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,morello.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,morello.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Morello Platforms + +maintainers: + - Vincenzo Frascino + +description: |+ + The Morello architecture is an experimental extension to Armv8.2-A, + which extends the AArch64 state with the principles proposed in + version 7 of the Capability Hardware Enhanced RISC Instructions + (CHERI) ISA. + + ARM's Morello Platforms are built as a research project to explore + capability architectures based on arm. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Arm Morello System Development Platform + items: + - const: arm,morello-sdp + - const: arm,morello + +additionalProperties: true + +... -- cgit v1.2.3 From 73d251e7068cdedb5cd465cdebc8f76a4cd75d7f Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Fri, 21 Feb 2025 18:03:42 +0000 Subject: dt-bindings: arm: Add Morello fvp compatibility Add compatibility to Arm Morello Fixed Virtual Platform. Signed-off-by: Vincenzo Frascino Reviewed-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Message-Id: <20250221180349.1413089-4-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/arm/arm,morello.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/arm,morello.yaml b/Documentation/devicetree/bindings/arm/arm,morello.yaml index b4cfa8d048c4..e843b97fa485 100644 --- a/Documentation/devicetree/bindings/arm/arm,morello.yaml +++ b/Documentation/devicetree/bindings/arm/arm,morello.yaml @@ -23,9 +23,11 @@ properties: const: '/' compatible: oneOf: - - description: Arm Morello System Development Platform + - description: Arm Morello System Platforms items: - - const: arm,morello-sdp + - enum: + - arm,morello-sdp + - arm,morello-fvp - const: arm,morello additionalProperties: true -- cgit v1.2.3 From 91ee16438965f92b8f20ab3d3581aa7f1c2c07f1 Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Fri, 21 Feb 2025 18:03:43 +0000 Subject: dt-bindings: arm: Add Rainier compatibility The Arm Morello System Development Platform uses Rainier CPUs. Add compatibility to Rainier. Acked-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij Message-Id: <20250221180349.1413089-5-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 73dd73d2d4fa..2e666b2a4dcd 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -177,6 +177,7 @@ properties: - arm,neoverse-v2 - arm,neoverse-v3 - arm,neoverse-v3ae + - arm,rainier - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan -- cgit v1.2.3 From 807945ae7325f816f3099bb500f5dabce2ad378a Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Fri, 21 Feb 2025 18:03:44 +0000 Subject: dt-bindings: arm-pmu: Add support for ARM Rainier PMU Add support for the ARM Rainier CPU core PMU. Acked-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij Message-Id: <20250221180349.1413089-6-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/arm/pmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index a148ff54f2b8..295963a3cae7 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -67,6 +67,7 @@ properties: - arm,neoverse-v2-pmu - arm,neoverse-v3-pmu - arm,neoverse-v3ae-pmu + - arm,rainier-pmu - brcm,vulcan-pmu - cavium,thunder-pmu - nvidia,denver-pmu -- cgit v1.2.3 From 8fc53e26fdd8c6ad315d814ad079e0c37ff2c4af Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Fri, 21 Feb 2025 18:03:46 +0000 Subject: arm64: dts: morello: Add support for common functionalities The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share some functionalities that have conveniently been included in morello.dtsi to avoid duplication. Introduce morello.dtsi. Note: Morello fvp will be introduced with a future patch series. Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij Message-Id: <20250221180349.1413089-8-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/morello.dtsi | 323 +++++++++++++++++++++++++++++++++++ 1 file changed, 323 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi new file mode 100644 index 000000000000..0bab0b3ea969 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + */ + +#include + +/ { + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + + soc_refclk50mhz: clock-50000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "apb_pclk"; + }; + + soc_refclk85mhz: clock-85000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <85000000>; + clock-output-names = "iofpga:aclk"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,rainier"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_0>; + clocks = <&scmi_dvfs 0>; + + l2_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-size = <0x100000>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + compatible = "arm,rainier"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_1>; + clocks = <&scmi_dvfs 0>; + + l2_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu2: cpu@10000 { + compatible = "arm,rainier"; + reg = <0x0 0x10000>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_2>; + clocks = <&scmi_dvfs 1>; + + l2_2: l2-cache-2 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@10100 { + compatible = "arm,rainier"; + reg = <0x0 0x10100>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_3>; + clocks = <&scmi_dvfs 1>; + + l2_3: l2-cache-3 { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + }; + + firmware { + interrupt-parent = <&gic>; + + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 1 0>, <&mailbox 1 1>; + shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + device_type = "memory"; + /* [0x80000000-0xffffffff] */ + reg = <0x00000000 0x80000000 0x0 0x7f000000>; + }; + + memory@8080000000 { + device_type = "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg = <0x00000080 0x80000000 0x3 0x78000000>; + }; + + pmu { + compatible = "arm,rainier-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-firmware@ff000000 { + reg = <0x0 0xff000000 0x0 0x01000000>; + no-map; + }; + }; + + spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + ranges; + + uart0: serial@2a400000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2a400000 0x0 0x1000>; + interrupts = ; + clocks = <&soc_refclk50mhz>, <&soc_refclk50mhz>; + clock-names = "uartclk", "apb_pclk"; + + status = "disabled"; + }; + + gic: interrupt-controller@30000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x30000000 0x0 0x10000>, /* GICD */ + <0x0 0x300c0000 0x0 0x80000>; /* GICR */ + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its1: msi-controller@30040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30040000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its2: msi-controller@30060000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30060000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its_ccix: msi-controller@30080000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30080000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its_pcie: msi-controller@300a0000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x300a0000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + smmu_dp: iommu@2ce00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x2ce00000 0x0 0x40000>; + + interrupts = , + , + ; + interrupt-names = "eventq", "gerror", "cmdq-sync"; + #iommu-cells = <1>; + }; + + mailbox: mhu@45000000 { + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0x0 0x45000000 0x0 0x1000>; + + interrupts = , + ; + #mbox-cells = <2>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + }; + + sram: sram@6000000 { + compatible = "mmio-sram"; + reg = <0x0 0x06000000 0x0 0x8000>; + ranges = <0 0x0 0x06000000 0x8000>; + + #address-cells = <1>; + #size-cells = <1>; + + cpu_scp_hpri0: scp-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + cpu_scp_hpri1: scp-sram@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; -- cgit v1.2.3 From 7f6838da3c673a15cee118d083810adaed09d400 Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Fri, 21 Feb 2025 18:03:47 +0000 Subject: arm64: dts: morello: Add support for soc dts The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello SoC dts. Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij Message-Id: <20250221180349.1413089-9-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/morello-sdp.dts | 157 ++++++++++++++++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello-sdp.dts diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index d908e96d7ddc..869667bef7c0 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts new file mode 100644 index 000000000000..cee49dee7571 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model = "Arm Morello System Development Platform"; + compatible = "arm,morello-sdp", "arm,morello"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dpu_aclk: clock-350000000 { + /* 77.1 MHz derived from 24 MHz reference clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <350000000>; + clock-output-names = "aclk"; + }; + + dpu_pixel_clk: clock-148500000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + clock-output-names = "pxclk"; + }; + + i2c0: i2c@1c0f0000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x1c0f0000 0x0 0x1000>; + interrupts = ; + clocks = <&dpu_aclk>; + + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <100000>; + + hdmi_tx: hdmi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + video-ports = <0x234501>; + port { + tda998x_0_input: endpoint { + remote-endpoint = <&dp_pl0_out0>; + }; + }; + }; + }; + + dp0: display@2cc00000 { + compatible = "arm,mali-d32", "arm,mali-d71"; + reg = <0x0 0x2cc00000 0x0 0x20000>; + interrupts = <0 69 4>; + clocks = <&dpu_aclk>; + clock-names = "aclk"; + iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, + <&smmu_dp 8>; + + #address-cells = <1>; + #size-cells = <0>; + + pl0: pipeline@0 { + reg = <0>; + clocks = <&dpu_pixel_clk>; + clock-names = "pxclk"; + port { + dp_pl0_out0: endpoint { + remote-endpoint = <&tda998x_0_input>; + }; + }; + }; + }; + + smmu_ccix: iommu@4f000000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x4f000000 0x0 0x40000>; + + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent = <&its1 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + smmu_pcie: iommu@4f400000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x4f400000 0x0 0x40000>; + + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent = <&its2 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + pcie_ctlr: pcie@28c0000000 { + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + reg = <0x28 0xC0000000 0 0x10000000>; + ranges = <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>, + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>, + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>; + bus-range = <0 255>; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_pcie 0 0x10000>; + iommu-map = <0 &smmu_pcie 0 0x10000>; + }; + + ccix_pcie_ctlr: pcie@4fc0000000 { + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + reg = <0x4f 0xC0000000 0 0x10000000>; + ranges = <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>, + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>, + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_ccix 0 0x10000>; + iommu-map = <0 &smmu_ccix 0 0x10000>; + }; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From 34f3b3745ce5850c5ea3f8cb80449a65e60be54b Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Fri, 21 Feb 2025 18:03:48 +0000 Subject: arm64: dts: morello: Add support for fvp dts The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello fvp dts. Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij Message-Id: <20250221180349.1413089-10-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/Makefile | 2 +- arch/arm64/boot/dts/arm/morello-fvp.dts | 77 +++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/arm/morello-fvp.dts diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 869667bef7c0..f30ee045dc95 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,4 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/arm/morello-fvp.dts new file mode 100644 index 000000000000..2072c0b72325 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-fvp.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model = "Arm Morello Fixed Virtual Platform"; + compatible = "arm,morello-fvp", "arm,morello"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + bp_refclock24mhz: clock-24000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "bp:clock24mhz"; + }; + + block_0: virtio_block@1c170000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c170000 0x0 0x200>; + interrupts = ; + }; + + net_0: virtio_net@1c180000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c180000 0x0 0x200>; + interrupts = ; + }; + + rng_0: virtio_rng@1c190000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c190000 0x0 0x200>; + interrupts = ; + }; + + p9_0: virtio_p9@1c1a0000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c1a0000 0x0 0x200>; + interrupts = ; + }; + + kmi_0: kmi@1c150000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c150000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi_1: kmi@1c160000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c160000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + eth_0: ethernet@1d100000 { + compatible = "smsc,lan91c111"; + reg = <0x0 0x1d100000 0x0 0x10000>; + interrupts = ; + }; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From 6ceb0dd64727c9606fa8371c4fe23fea7b20b26d Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Fri, 21 Feb 2025 18:03:49 +0000 Subject: MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer Add Vincenzo Frascino as Arm Morello Software Development Platform Maintainer. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino Reviewed-by: Linus Walleij Message-Id: <20250221180349.1413089-11-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 896a307fa065..7d263e4409d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2751,6 +2751,13 @@ F: arch/arm/boot/dts/socionext/milbeaut* F: arch/arm/mach-milbeaut/ N: milbeaut +ARM/MORELLO PLATFORM +M: Vincenzo Frascino +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/arm/arm,morello.yaml +F: arch/arm64/boot/dts/arm/morello* + ARM/MOXA ART SOC M: Krzysztof Kozlowski L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- cgit v1.2.3 From 21b9f56cec8f8918b5bbb900d6d86eaf06d54537 Mon Sep 17 00:00:00 2001 From: Hugues KAMBA MPIANA Date: Mon, 3 Mar 2025 17:00:12 +0000 Subject: arm64: dts: corstone1000: Add definitions for secondary CPU cores Add cpu{1-3} device nodes to the corstone1000 device tree to enable the support for secondary CPU cores. This update facilitates symmetric multiprocessing (SMP) support on the corstone1000 Fixed Virtual Platform (FVP), allowing the secondary cores to be properly initialised and utilised. Only FVP platform will have SMP support and hence the secondary cpu definitions are not added to corstone1000.dtsi. Signed-off-by: Hugues KAMBA MPIANA Message-Id: <20250303170012.469576-1-hugues.kambampiana@arm.com> (sudeep.holla: Added psci enable-method for cpu0) Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 26 ++++++++++++++++++++++++++ arch/arm64/boot/dts/arm/corstone1000.dtsi | 3 ++- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts index abd013562995..66ba6b027193 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -49,3 +49,29 @@ clock-names = "smclk", "apb_pclk"; }; }; + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index bb9b96fb5314..56ada8728b60 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -21,7 +21,7 @@ stdout-path = "serial0:115200n8"; }; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; @@ -29,6 +29,7 @@ device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0>; + enable-method = "psci"; next-level-cache = <&L2_0>; }; }; -- cgit v1.2.3