From c0cb98e3230fd5959bb8075e059fef60d0477698 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:10 +0200 Subject: arm64: dts: imx8mp-var-som-symphony: enable ECSPI2 Enable the ECSPI2 bus on the Symphony carrier board and add the pinctrl configuration for the SPI signals and chip select GPIO. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index f8a4b5b2e9fb..387bbe3454c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -99,6 +99,13 @@ status = "okay"; }; +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &hdmi_pai { status = "okay"; }; @@ -327,6 +334,15 @@ >; }; + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x12 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x12 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x12 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12 + >; + }; + pinctrl_hdmi: hdmigrp { fsl,pins = < MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 -- cgit v1.2.3