kernel/git/stable/linux.git/Documentation/devicetree/bindings/phy, branch master

Merge tag 'phy-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2026-08-24T19:19:23+00:00

Pull phy updates from Vinod Koul: "As usual bunch of new device and driver support and updates to existing drivers and addition of Manivannan to help with reviews. New Support: - Mediatek MT8196 DSI PHY support - Renesas RZ/G3L usb2 support - Qualcomm SM8475 QMP USB PHY and PCIe phy, IPQ9650 QMP PCIe PHY, QUSB2 Phy for Shikra SoC, Hawi support for QMP PCIe phy and UFS PHY. Glymur QMP PCIe Multi-PHY driver and multiple link-mode support, ipq5210 PCIe phy support - Spacemit USB3/PCIe comb PHY driver Updates: - Samsung hdptx driver improvements for modernizing the register access and code cleanup - Qualcomm drop duplicate v8 DP headers, improved runtime handling for qmp drivers - Rockchip clock lane phase tuning and 2500 Mbps support and TMDS rate handling - Freescale imx8mq improvements for runtime pm, pd handling" * tag 'phy-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (76 commits) MAINTAINERS: Add Manivannan Sadhasivam as the Reviewer for Generic PHY Framework phy: rockchip-samsung-dcphy: fix out-of-range max_register phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY phy: rockchip: samsung-hdptx: Consistently use bitfield macros phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16() phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling phy: rockchip: samsung-hdptx: Consolidate consumer_put on error path phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL phy: rockchip: samsung-hdptx: Guard against clk rate integer underflow phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc phy: qcom: qmp-combo: Drop qmp_v4_calibrate_dp_phy phy: qcom: qmp-combo: Correct pre-emphasis table for QMP v4 DP PHYs phy: renesas: rcar-gen3-usb2: Ignore missing VBUS regulator phy: qcom: qmp-pcie: Add support for SM8475 Gen3x1 PCIe0 port phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHY ...

dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY

2026-08-11T16:54:03+00:00

Add qcom,glymur-qmp-gen5x8-pcie-phy.yaml as a standalone binding for the Glymur Gen5 PCIe PHY hardware block. This block supports two link modes, selected at runtime via a TCSR syscon register: 1. x8 - a single 8-lane PHY instance is exposed 2. x4+x4 - two independent 4-lane PHY instances are exposed Keep this as a separate schema from qcom,sc8280xp-qmp-pcie-phy.yaml rather than folding it into the shared compatible list there, since the two PHY instances active in x8 mode require twice as many clocks, resets, and power-domains as any other entry in that file, and adding Glymur-specific properties like qcom,link-mode and reg-names there would only apply to this one compatible. Document the required clocks, resets, and power-domains for both PHY instances, and use #phy-cells = <1>, where the cell value is the PHY index within the active link mode. Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Qiang Yu Link: https://patch.msgid.link/20260807-glymur_linkmode_0807-v9-1-dd1c7e236e29@oss.qualcomm.com Signed-off-by: Vinod Koul

dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHY

2026-08-07T06:23:37+00:00

SM8450 init sequence for this PHY varies significantly and can't be reused in SM8475. Add bindings for the PHY found in this SoC. Signed-off-by: Esteban Urrutia Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260715-sm8475-bup-pcie-v2-1-48bd91a19abf@proton.me Signed-off-by: Vinod Koul

dt-bindings: phy: qcom,sa8775p-dwmac-sgmii-phy: add named voltage rails and deprecate phy-supply

2026-08-07T06:10:37+00:00

The Qualcomm SGMII SerDes PHY has two distinct voltage supply rails, vdda-0p9 and vdda-1p2. The binding incorrectly described only a single generic supply via 'phy-supply'. Deprecate 'phy-supply' and instead add two named supply properties. The 0.9V rail draws a peak current of 46 mA and the 1.2V rail draws 15 mA. Fixes: 97b795125704 ("dt-bindings: phy: describe the Qualcomm SGMII PHY") Signed-off-by: Mohd Ayaan Anwar Reviewed-by: Krzysztof Kozlowski Reviewed-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20260804-b4-sgmiieth_serdes_regulator-v2-1-c4bc688177dd@oss.qualcomm.com Signed-off-by: Vinod Koul

dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add Hawi UFS PHY compatible

2026-08-07T06:06:39+00:00

Document QMP UFS PHY compatible for Hawi SoC. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Palash Kambar Link: https://patch.msgid.link/20260806161301.1010876-2-palash.kambar@oss.qualcomm.com Signed-off-by: Vinod Koul

dt-bindings: phy: rockchip-inno-csi-dphy: add rockchip,clk-lane-phase property

2026-08-06T16:05:36+00:00

Add support for the optional rockchip,clk-lane-phase device tree property to allow board-specific tuning of the clock lane sampling phase for improved signal integrity across supported data rates. Acked-by: Rob Herring (Arm) Acked-by: Michael Riesch Signed-off-by: Gerald Loacker Link: https://patch.msgid.link/20260725-feature-mipi-csi-dphy-4k60-v4-2-5b2c4626d31e@wolfvision.net Signed-off-by: Vinod Koul

dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8475 QMP PHY

2026-08-06T15:41:39+00:00

SM8450 init sequence for this PHY varies significantly and can't be used in SM8475. Add bindings for the PHY found in this SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Esteban Urrutia Link: https://patch.msgid.link/20260804-sm8475-bup-usbss-v3-1-9a5b9ebf62de@proton.me Signed-off-by: Vinod Koul

dt-bindings: phy: renesas,usb2-phy: Document RZ/G3L PHY bindings

2026-08-06T15:38:38+00:00

Add device tree binding support for the RZ/G3L (r9a08g046) USB2 PHY. The RZ/G3L USB PHY is almost identical to the RZ/G3S USB PHY, the difference being 2 OTG blocks on RZ/G3L compared to 1 on RZ/G3S. Acked-by: Krzysztof Kozlowski Signed-off-by: Biju Das Link: https://patch.msgid.link/20260806102236.149159-7-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul

dt-bindings: phy: qcom,m31-eusb2-phy: Document M31 eUSB2 PHY for Hawi

2026-08-06T15:35:05+00:00

Document the M31 eUSB2 PHY for Hawi which handles the USB2 path. Use fallback to indicate the compatibility of the M31 eUSB2 PHY on the Hawi with that on the SM8750. Signed-off-by: Ronak Raheja Reviewed-by: Krzysztof Kozlowski Signed-off-by: Mukesh Ojha Link: https://patch.msgid.link/20260803091441.3040830-3-mukesh.ojha@oss.qualcomm.com Signed-off-by: Vinod Koul

dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Hawi QMP PHY

2026-08-06T15:35:05+00:00

Document the Hawi compatible string for the QMP combo PHY. Hawi uses a new QSERDES V10 register layout with a new COM AON module and hardware-specific PHY init sequences compared to previous targets, requiring a dedicated compatible string. Signed-off-by: Ronak Raheja Acked-by: Rob Herring (Arm) Signed-off-by: Mukesh Ojha Link: https://patch.msgid.link/20260803091441.3040830-2-mukesh.ojha@oss.qualcomm.com Signed-off-by: Vinod Koul