kernel/git/stable/linux.git/Documentation/riscv/index.rst, branch master

docs: move riscv under arch

2023-10-10T19:37:43+00:00

and fix all in-tree references. Architecture-specific documentation is being moved into Documentation/arch/ as a way of cleaning up the top-level documentation directory and making the docs hierarchy more closely match the source hierarchy. Signed-off-by: Costa Shulyupin Reviewed-by: Conor Dooley Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20230930185354.3034118-1-costa.shul@redhat.com

Documentation: riscv: Add early boot document

2023-08-18T17:04:05+00:00

This document describes the constraints and requirements of the early boot process in a RISC-V kernel. Signed-off-by: Alexandre Ghiti Reviewed-by: Björn Töpel Reviewed-by: Conor Dooley Reviewed-by: Sunil V L Reviewed-by: Andrew Jones Reviewed-by: Palmer Dabbelt Reviewed-by: Atish Patra Reviewed-by: Song Shuai Reviewed-by: Randy Dunlap Acked-by: Palmer Dabbelt Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20230817130734.10387-2-alexghiti@rivosinc.com

RISC-V: Document the ISA string parsing rules for ACPI

2023-07-06T17:25:17+00:00

We've had a ton of issues around the ISA string parsing rules elsewhere in RISC-V, so let's at least be clear about what the rules are so we can try and avoid more issues. Link: https://lore.kernel.org/r/CAK9=C2Vy-4V9kgnga98tiC3TeHkR2LFPakyBbS8s_h3_Z=ieyQ@mail.gmail.com/ Link: https://lore.kernel.org/r/20230629031705.15575-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt

riscv: Add documentation for Vector

2023-06-08T14:16:57+00:00

This patch add a brief documentation of the userspace interface in regard to the RISC-V Vector extension. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu Reviewed-by: Vincent Chen Co-developed-by: Bagas Sanjaya Signed-off-by: Bagas Sanjaya Link: https://lore.kernel.org/r/20230605110724.21391-26-andy.chiu@sifive.com Signed-off-by: Palmer Dabbelt

RISC-V: Add a syscall for HW probing

2023-04-18T22:48:14+00:00

We don't have enough space for these all in ELF_HWCAP{,2} and there's no system call that quite does this, so let's just provide an arch-specific one to probe for hardware capabilities. This currently just provides m{arch,imp,vendor}id, but with the key-value pairs we can pass more in the future. Co-developed-by: Palmer Dabbelt Signed-off-by: Evan Green Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Reviewed-by: Paul Walmsley Link: https://lore.kernel.org/r/20230407231103.2622178-3-evan@rivosinc.com Signed-off-by: Palmer Dabbelt

doc: RISC-V: Document that misaligned accesses are supported

2022-10-12T15:58:10+00:00

The RISC-V ISA manual used to mandate that misaligned accesses were supported in user mode, but that requirement was removed in 2018 via riscv-isa-manual commit 61cadb9 ("Provide new description of misaligned load/store behavior compatible with privileged architecture."). Since the Linux uABI was already frozen at that point it's just been demoted to part of the uABI, but that was never written down. Link: https://lore.kernel.org/r/20220728210715.17214-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt

Documentation: riscv: remove non-existent directory from table of contents

2022-03-31T23:18:56+00:00

This subdir no longer exists: it was there to document some of the quirks and paths forward for handling them, but those have been dealt with as of Atish's recent patch set. Fixes: 23b1f18326ec ("Documentation: riscv: Remove the old documentation") Link: https://lore.kernel.org/linux-next/20220329133412.591d6882@canb.auug.org.au/ Reported-by: Stephen Rothwell Signed-off-by: Bagas Sanjaya [Palmer: commit text] Signed-off-by: Palmer Dabbelt

Documentation: riscv: Add documentation that describes the VM layout

2021-04-26T15:25:05+00:00

This new document presents the RISC-V virtual memory layout and is based one the x86 one: it describes the different limits of the different regions of the virtual address space. Signed-off-by: Alexandre Ghiti Signed-off-by: Palmer Dabbelt

docs: archis: add a per-architecture features list

2020-12-03T22:10:15+00:00

Add a feature list matrix for each architecture to their respective Kernel books. Signed-off-by: Mauro Carvalho Chehab Link: https://lore.kernel.org/r/9c39d4dd93e05c0008205527d2c3450912f029ed.1606748711.git.mchehab+huawei@kernel.org Signed-off-by: Jonathan Corbet

Documentation: riscv: add patch acceptance guidelines

2020-01-05T05:49:01+00:00

Formalize, in kernel documentation, the patch acceptance policy for arch/riscv. In summary, it states that as maintainers, we plan to only accept patches for new modules or extensions that have been frozen or ratified by the RISC-V Foundation. We've been following these guidelines for the past few months. In the meantime, we've received quite a bit of feedback that it would be helpful to have these guidelines formally documented. Based on a suggestion from Matthew Wilcox, we also add a link to this file to Documentation/process/index.rst, to make this document easier to find. The format of this document has also been changed to align to the format outlined in the maintainer entry profiles, in accordance with comments from Jon Corbet and Dan Williams. Signed-off-by: Paul Walmsley Reviewed-by: Palmer Dabbelt Cc: Palmer Dabbelt Cc: Albert Ou Cc: Krste Asanovic Cc: Andrew Waterman Cc: Matthew Wilcox Cc: Dan Williams Cc: Jonathan Corbet