<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/git/stable/linux.git/arch/arm/mach-tegra/flowctrl.c, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<id>https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/atom?h=master</id>
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<updated>2017-04-04T13:48:04+00:00</updated>
<entry>
<title>soc/tegra: Move Tegra flowctrl driver</title>
<updated>2017-04-04T13:48:04+00:00</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2017-03-28T12:42:54+00:00</published>
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<id>urn:sha1:7e10cf743634a6b0f3cf63046c49294b38254fe9</id>
<content type='text'>
The flowctrl driver is required for both ARM and ARM64 Tegra devices
and in order to enable support for it for ARM64, move the Tegra flowctrl
driver into drivers/soc/tegra.

By moving the flowctrl driver, tegra_flowctrl_init() is now called by
via an early initcall and to prevent this function from attempting to
mapping IO space for a non-Tegra device, a test for 'soc_is_tegra()'
is also added.

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Initialize flow controller from DT</title>
<updated>2014-08-26T17:43:55+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-08-26T06:14:04+00:00</published>
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<id>urn:sha1:783944feaab8383495ba067276a16e28c205fb13</id>
<content type='text'>
Use a matching device tree node to initialize the flow controller driver
instead of hard-coding the I/O address. This is necessary to get rid of
the iomap.h include, which in turn make it easier to share this code
with 64-bit Tegra SoCs.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Use a function to get the chip ID</title>
<updated>2014-07-17T11:36:41+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-11T07:52:41+00:00</published>
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<id>urn:sha1:304664eab93f9e95a8d28fbd9702ede88bb10cc5</id>
<content type='text'>
Instead of using a simple variable access to get at the Tegra chip ID,
use a function so that we can run additional code. This can be used to
determine where the chip ID is being accessed without being available.
That in turn will be handy for resolving boot sequence dependencies in
order to convert more code to regular initcalls rather than a sequence
fixed by Tegra SoC setup code.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Sort includes alphabetically</title>
<updated>2014-07-17T11:29:57+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-11T07:44:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a0524acc94c91c72c2968a76eddc6f3afe82f9f2'/>
<id>urn:sha1:a0524acc94c91c72c2968a76eddc6f3afe82f9f2</id>
<content type='text'>
If these aren't sorted alphabetically, then the logical choice is to
append new ones, however that creates a lot of potential for conflicts
because every change will then add new includes in the same location.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: add LP1 support code for Tegra124</title>
<updated>2013-10-18T22:28:10+00:00</updated>
<author>
<name>Joseph Lo</name>
<email>josephl@nvidia.com</email>
</author>
<published>2013-10-11T09:58:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f0c4ac1329452e5d31a03b4bb711c330065c0369'/>
<id>urn:sha1:f0c4ac1329452e5d31a03b4bb711c330065c0369</id>
<content type='text'>
The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
need to update the difference of the register address, then we can
continue to share the code.

Signed-off-by: Joseph Lo &lt;josephl@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: flowctrl: add support for cpu_suspend_enter/exit</title>
<updated>2013-07-19T16:08:08+00:00</updated>
<author>
<name>Joseph Lo</name>
<email>josephl@nvidia.com</email>
</author>
<published>2013-07-03T09:50:43+00:00</published>
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<id>urn:sha1:dd6fe9a927eaaa98f70b44464a810e6e4d33318c</id>
<content type='text'>
The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU goes into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.

For Tegra114, the setting is compatible with Tegra30.

Signed-off-by: Joseph Lo &lt;josephl@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit</title>
<updated>2013-01-28T18:20:38+00:00</updated>
<author>
<name>Joseph Lo</name>
<email>josephl@nvidia.com</email>
</author>
<published>2013-01-15T22:11:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=afec581c4b53e03a97d9ef1b7a746a67967573cf'/>
<id>urn:sha1:afec581c4b53e03a97d9ef1b7a746a67967573cf</id>
<content type='text'>
The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.

Signed-off-by: Joseph Lo &lt;josephl@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Make variables static</title>
<updated>2013-01-28T17:21:28+00:00</updated>
<author>
<name>Hiroshi Doyu</name>
<email>hdoyu@nvidia.com</email>
</author>
<published>2013-01-03T06:27:05+00:00</published>
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<id>urn:sha1:deeb8d194814c98be379a284e07d938c6af066f4</id>
<content type='text'>
No need to be public. Checked with:
  $ touch arch/arm/mach-tegra/*[ch] &amp;&amp; make C=1

Signed-off-by: Hiroshi Doyu &lt;hdoyu@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra30: flowctrl: add cpu_suspend_exter/exit function</title>
<updated>2012-11-15T22:09:21+00:00</updated>
<author>
<name>Joseph Lo</name>
<email>josephl@nvidia.com</email>
</author>
<published>2012-10-31T09:41:20+00:00</published>
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<id>urn:sha1:01459c69dd48badeb7833c3293e43f7b8ae75e31</id>
<content type='text'>
The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.

Signed-off-by: Joseph Lo &lt;josephl@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: move iomap.h to mach-tegra</title>
<updated>2012-11-05T18:36:06+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2012-10-04T20:24:09+00:00</published>
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<id>urn:sha1:2be39c079d692a07b55c8795051d40c0c94a3633</id>
<content type='text'>
Nothing outside mach-tegra uses this file, so there's no need for it to
be in &lt;mach/&gt;.

Since uncompress.h and debug-macro.S remain in include/mach, they need
to include "../../iomap.h" becaue of this change. uncompress.h will soon
be deleted in later multi-platform/single-zImage patches. debug-macro.S
will need to continue to include this header using an explicit relative
path, to avoid duplicating the physical-&gt;virtual address mapping that
iomap.h dictates.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
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